//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Evan Cheng and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/Instruction.h"
+#include "llvm/Intrinsics.h"
+#include "llvm/GlobalValue.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/Support/MathExtras.h"
: TargetLowering(TM), ARMPCLabelIndex(0) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
- // Uses VFP for Thumb libfuncs if available.
- if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) {
- // Single-precision floating-point arithmetic.
- setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
- setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
- setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
- setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
-
- // Double-precision floating-point arithmetic.
- setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
- setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
- setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
- setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
-
- // Single-precision comparisons.
- setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
- setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
- setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
- setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
- setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
- setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
- setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
- setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
-
- setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
- setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
- setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
- setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
-
- // Double-precision comparisons.
- setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
- setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
- setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
- setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
- setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
- setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
- setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
- setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
-
- setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
- setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
- setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
- setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
- setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
-
- // Floating-point to integer conversions.
- // i64 conversions are done via library routines even when generating VFP
- // instructions, so use the same ones.
- setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
- setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
- setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
- setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
-
- // Conversions between floating types.
- setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
- setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
-
- // Integer to floating-point conversions.
- // i64 conversions are done via library routines even when generating VFP
- // instructions, so use the same ones.
- // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
- // __floatunsidf vs. __floatunssidfvfp.
- setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
- setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
- setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
- setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
+ if (Subtarget->isTargetDarwin()) {
+ // Don't have these.
+ setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
+ setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
+
+ // Uses VFP for Thumb libfuncs if available.
+ if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
+ // Single-precision floating-point arithmetic.
+ setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
+ setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
+ setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
+ setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
+
+ // Double-precision floating-point arithmetic.
+ setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
+ setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
+ setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
+ setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
+
+ // Single-precision comparisons.
+ setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
+ setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
+ setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
+ setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
+ setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
+ setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
+ setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
+ setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
+
+ setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
+
+ // Double-precision comparisons.
+ setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
+ setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
+ setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
+ setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
+ setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
+ setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
+ setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
+ setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
+
+ setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
+ setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
+
+ // Floating-point to integer conversions.
+ // i64 conversions are done via library routines even when generating VFP
+ // instructions, so use the same ones.
+ setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
+ setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
+ setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
+ setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
+
+ // Conversions between floating types.
+ setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
+ setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
+
+ // Integer to floating-point conversions.
+ // i64 conversions are done via library routines even when generating VFP
+ // instructions, so use the same ones.
+ // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
+ // __floatunsidf vs. __floatunssidfvfp.
+ setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
+ setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
+ setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
+ setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
+ }
}
addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
+
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
}
+ computeRegisterProperties();
// ARM does not have f32 extending load.
setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+ // ARM does not have i1 sign extending load.
+ setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
+
// ARM supports all 4 flavors of integer indexed load / store.
for (unsigned im = (unsigned)ISD::PRE_INC;
im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
setOperationAction(ISD::MUL, MVT::i64, Expand);
setOperationAction(ISD::MULHU, MVT::i32, Expand);
setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
} else {
- setOperationAction(ISD::MUL, MVT::i64, Custom);
- setOperationAction(ISD::MULHU, MVT::i32, Custom);
+ setOperationAction(ISD::MUL, MVT::i64, Expand);
+ setOperationAction(ISD::MULHU, MVT::i32, Expand);
if (!Subtarget->hasV6Ops())
- setOperationAction(ISD::MULHS, MVT::i32, Custom);
+ setOperationAction(ISD::MULHS, MVT::i32, Expand);
}
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
// Support label based line numbers.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- // FIXME - use subtarget debug flags
- if (!Subtarget->isTargetDarwin())
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
setOperationAction(ISD::RET, MVT::Other, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
+ setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
// Expand mem operations genericly.
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
- setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
+ setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
-
+
// Use the default implementation.
- setOperationAction(ISD::VASTART , MVT::Other, Expand);
+ setOperationAction(ISD::VASTART , MVT::Other, Custom);
setOperationAction(ISD::VAARG , MVT::Other, Expand);
setOperationAction(ISD::VACOPY , MVT::Other, Expand);
setOperationAction(ISD::VAEND , MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
+ setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
+ setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
if (!Subtarget->hasV6Ops()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
// Turn f64->i64 into FMRRD iff target supports vfp2.
setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
-
+
+ // We want to custom lower some of our intrinsics.
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+
setOperationAction(ISD::SETCC , MVT::i32, Expand);
setOperationAction(ISD::SETCC , MVT::f32, Expand);
setOperationAction(ISD::SETCC , MVT::f64, Expand);
setOperationAction(ISD::BR_CC , MVT::f64, Custom);
setOperationAction(ISD::BR_JT , MVT::Other, Custom);
- setOperationAction(ISD::VASTART, MVT::Other, Custom);
- setOperationAction(ISD::VACOPY, MVT::Other, Expand);
- setOperationAction(ISD::VAEND, MVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
-
- // FP Constants can't be immediates.
- setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
- setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
-
- // We don't support sin/cos/fmod/copysign
+ // We don't support sin/cos/fmod/copysign/pow
setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
+ setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FPOW , MVT::f32, Expand);
// int <-> fp are custom expanded into bit_convert + ARMISD ops.
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ // We have target-specific dag combine patterns for the following nodes:
+ // ARMISD::FMRRD - No need to call setTargetDAGCombine
+
setStackPointerRegisterToSaveRestore(ARM::SP);
-
setSchedulingPreference(SchedulingForRegPressure);
- computeRegisterProperties();
+ setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
+ setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
+
+ maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
}
case ARMISD::Wrapper: return "ARMISD::Wrapper";
case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
case ARMISD::CALL: return "ARMISD::CALL";
+ case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
case ARMISD::tCALL: return "ARMISD::tCALL";
case ARMISD::BRCOND: return "ARMISD::BRCOND";
case ARMISD::FTOUI: return "ARMISD::FTOUI";
case ARMISD::SITOF: return "ARMISD::SITOF";
case ARMISD::UITOF: return "ARMISD::UITOF";
- case ARMISD::MULHILOU: return "ARMISD::MULHILOU";
- case ARMISD::MULHILOS: return "ARMISD::MULHILOS";
case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
case ARMISD::FMRRD: return "ARMISD::FMRRD";
case ARMISD::FMDRR: return "ARMISD::FMDRR";
+
+ case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
}
}
// node so that legalize doesn't hack it.
bool isDirect = false;
bool isARMFunc = false;
+ bool isLocalARMFunc = false;
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
GlobalValue *GV = G->getGlobal();
isDirect = true;
bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
getTargetMachine().getRelocationModel() != Reloc::Static;
isARMFunc = !Subtarget->isThumb() || isStub;
+ // ARM call to a local ARM function is predicable.
+ isLocalARMFunc = !Subtarget->isThumb() && !isExt;
// tBX takes a register source operand.
if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
} else {
CallOpc = (isDirect || Subtarget->hasV5TOps())
- ? ARMISD::CALL : ARMISD::CALL_NOLINK;
+ ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
+ : ARMISD::CALL_NOLINK;
}
if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag };
- Chain = DAG.getNode(ISD::CALLSEQ_END,
- DAG.getNodeValueTypes(MVT::Other, MVT::Flag),
- ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3);
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(NumBytes, MVT::i32),
+ DAG.getConstant(0, MVT::i32),
+ InFlag);
if (RetVT != MVT::Other)
InFlag = Chain.getValue(1);
if (Op.getValueType() == MVT::f32) {
Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
} else if (Op.getValueType() == MVT::f64) {
- // Recursively legalize f64 -> i64.
- Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
- return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
- DAG.getConstant(0, MVT::i32));
+ // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
+ // available.
+ Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
+ SDOperand Sign = DAG.getConstant(0, MVT::i32);
+ return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
+ Op.getValue(1), Sign);
}
Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
- if (DAG.getMachineFunction().liveout_empty())
- DAG.getMachineFunction().addLiveOut(ARM::R0);
+ if (DAG.getMachineFunction().getRegInfo().liveout_empty())
+ DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
break;
case 5:
Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
// If we haven't noted the R0+R1 are live out, do so now.
- if (DAG.getMachineFunction().liveout_empty()) {
- DAG.getMachineFunction().addLiveOut(ARM::R0);
- DAG.getMachineFunction().addLiveOut(ARM::R1);
+ if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
+ DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
+ DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
}
break;
}
return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
}
+// Lower ISD::GlobalTLSAddress using the "general dynamic" model
+SDOperand
+ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
+ SelectionDAG &DAG) {
+ MVT::ValueType PtrVT = getPointerTy();
+ unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
+ ARMConstantPoolValue *CPV =
+ new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
+ PCAdj, "tlsgd", true);
+ SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
+ Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
+ SDOperand Chain = Argument.getValue(1);
+
+ SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
+
+ // call __tls_get_addr.
+ ArgListTy Args;
+ ArgListEntry Entry;
+ Entry.Node = Argument;
+ Entry.Ty = (const Type *) Type::Int32Ty;
+ Args.push_back(Entry);
+ std::pair<SDOperand, SDOperand> CallResult =
+ LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
+ CallingConv::C, false,
+ DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
+ return CallResult.first;
+}
+
+// Lower ISD::GlobalTLSAddress using the "initial exec" or
+// "local exec" model.
+SDOperand
+ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
+ SelectionDAG &DAG) {
+ GlobalValue *GV = GA->getGlobal();
+ SDOperand Offset;
+ SDOperand Chain = DAG.getEntryNode();
+ MVT::ValueType PtrVT = getPointerTy();
+ // Get the Thread Pointer
+ SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
+
+ if (GV->isDeclaration()){
+ // initial exec model
+ unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
+ ARMConstantPoolValue *CPV =
+ new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
+ PCAdj, "gottpoff", true);
+ Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
+ Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
+ Chain = Offset.getValue(1);
+
+ SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
+
+ Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
+ } else {
+ // local exec model
+ ARMConstantPoolValue *CPV =
+ new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
+ Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
+ Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
+ }
+
+ // The address of the thread local variable is the add of the thread
+ // pointer with the offset of the variable.
+ return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
+}
+
+SDOperand
+ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
+ // TODO: implement the "local dynamic" model
+ assert(Subtarget->isTargetELF() &&
+ "TLS not implemented for non-ELF targets");
+ GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
+ // If the relocation model is PIC, use the "General Dynamic" TLS Model,
+ // otherwise use the "Local Exec" TLS Model
+ if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
+ return LowerToTLSGeneralDynamicModel(GA, DAG);
+ else
+ return LowerToTLSExecModels(GA, DAG);
+}
+
+SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
+ SelectionDAG &DAG) {
+ MVT::ValueType PtrVT = getPointerTy();
+ GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
+ Reloc::Model RelocM = getTargetMachine().getRelocationModel();
+ if (RelocM == Reloc::PIC_) {
+ bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
+ ARMConstantPoolValue *CPV =
+ new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
+ SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
+ SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ SDOperand Chain = Result.getValue(1);
+ SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
+ Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
+ if (!UseGOTOFF)
+ Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
+ return Result;
+ } else {
+ SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
+ return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ }
+}
+
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
-/// even in dynamic-no-pic mode.
-static bool GVIsIndirectSymbol(GlobalValue *GV) {
- return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
- (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
+/// even in non-static mode.
+static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
+ return RelocM != Reloc::Static &&
+ (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
+ (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
}
-SDOperand ARMTargetLowering::LowerGlobalAddress(SDOperand Op,
- SelectionDAG &DAG) {
+SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
+ SelectionDAG &DAG) {
MVT::ValueType PtrVT = getPointerTy();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
- bool IsIndirect = Subtarget->isTargetDarwin() && GVIsIndirectSymbol(GV);
+ bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
SDOperand CPAddr;
if (RelocM == Reloc::Static)
CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
return Result;
}
+SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
+ SelectionDAG &DAG){
+ assert(Subtarget->isTargetELF() &&
+ "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
+ MVT::ValueType PtrVT = getPointerTy();
+ unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
+ ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
+ ARMPCLabelIndex,
+ ARMCP::CPValue, PCAdj);
+ SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
+ SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
+}
+
+static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
+ MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
+ switch (IntNo) {
+ default: return SDOperand(); // Don't custom lower most intrinsics.
+ case Intrinsic::arm_thread_pointer:
+ return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
+ }
+}
+
static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
unsigned VarArgsFrameIndex) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
- SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
- return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
- SV->getOffset());
+ const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
+ return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
}
static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
- unsigned *vRegs, unsigned ArgNo,
- unsigned &NumGPRs, unsigned &ArgOffset) {
+ unsigned ArgNo, unsigned &NumGPRs,
+ unsigned &ArgOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
SDOperand Root = Op.getOperand(0);
std::vector<SDOperand> ArgValues;
- SSARegMap *RegMap = MF.getSSARegMap();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
static const unsigned GPRArgRegs[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
SDOperand ArgValue;
if (ObjGPRs == 1) {
- unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
- vRegs[NumGPRs] = VReg;
+ unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
if (ObjectVT == MVT::f32)
ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
} else if (ObjGPRs == 2) {
- unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
- vRegs[NumGPRs] = VReg;
+ unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
- VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
- vRegs[NumGPRs+1] = VReg;
+ VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
- if (ObjectVT == MVT::i64)
- ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
- else
- ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
+ assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
+ ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
}
NumGPRs += ObjGPRs;
if (ObjSize) {
- // If the argument is actually used, emit a load from the right stack
- // slot.
- if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
- MachineFrameInfo *MFI = MF.getFrameInfo();
- int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
- if (ObjGPRs == 0)
- ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
- else {
- SDOperand ArgValue2 =
- DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
- if (ObjectVT == MVT::i64)
- ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
- else
- ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
- }
- } else {
- // Don't emit a dead load.
- ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
+ SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+ if (ObjGPRs == 0)
+ ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
+ else {
+ SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
+ assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
+ ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
}
ArgOffset += ObjSize; // Move on to the next argument.
SDOperand Root = Op.getOperand(0);
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
- unsigned VRegs[4];
unsigned NumArgs = Op.Val->getNumValues()-1;
for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
- ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
+ ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
NumGPRs, ArgOffset));
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
};
MachineFunction &MF = DAG.getMachineFunction();
- SSARegMap *RegMap = MF.getSSARegMap();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
MachineFrameInfo *MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
SmallVector<SDOperand, 4> MemOps;
for (; NumGPRs < 4; ++NumGPRs) {
- unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
+ unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
/// isFloatingPointZero - Return true if this is +0.0.
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
- return CFP->isExactlyValue(0.0);
+ return CFP->getValueAPF().isPosZero();
else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
// Maybe this has already been legalized into the constant pool?
if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
- return CFP->isExactlyValue(0.0);
+ return CFP->getValueAPF().isPosZero();
}
}
return false;
if (LHS.getValueType() == MVT::i32) {
SDOperand ARMCC;
+ SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
- return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
+ return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
}
ARMCC::CondCodes CondCode, CondCode2;
std::swap(TrueVal, FalseVal);
SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
- ARMCC, Cmp);
+ ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
- Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
+ Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
}
return Result;
}
if (LHS.getValueType() == MVT::i32) {
SDOperand ARMCC;
+ SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
- return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
+ return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
}
assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
- SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
+ SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
+ SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
if (CondCode2 != ARMCC::AL) {
ARMCC = DAG.getConstant(CondCode2, MVT::i32);
- SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
- Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
+ SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
+ Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
}
return Res;
}
Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
- Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
+ Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy,
+ Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
if (isPIC)
Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
- return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
+ SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
-static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
- // Turn f64->i64 into FMRRD.
- assert(Op.getValueType() == MVT::i64 &&
- Op.getOperand(0).getValueType() == MVT::f64);
+SDOperand ARMTargetLowering::LowerMEMCPYInline(SDOperand Chain,
+ SDOperand Dest,
+ SDOperand Source,
+ unsigned Size,
+ unsigned Align,
+ SelectionDAG &DAG) {
+ // Do repeated 4-byte loads and stores. To be improved.
+ assert((Align & 3) == 0 && "Expected 4-byte aligned addresses!");
+ unsigned BytesLeft = Size & 3;
+ unsigned NumMemOps = Size >> 2;
+ unsigned EmittedNumMemOps = 0;
+ unsigned SrcOff = 0, DstOff = 0;
+ MVT::ValueType VT = MVT::i32;
+ unsigned VTSize = 4;
+ unsigned i = 0;
+ const unsigned MAX_LOADS_IN_LDM = 6;
+ SDOperand TFOps[MAX_LOADS_IN_LDM];
+ SDOperand Loads[MAX_LOADS_IN_LDM];
+
+ // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
+ // same number of stores. The loads and stores will get combined into
+ // ldm/stm later on.
+ while (EmittedNumMemOps < NumMemOps) {
+ for (i = 0;
+ i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
+ Loads[i] = DAG.getLoad(VT, Chain,
+ DAG.getNode(ISD::ADD, MVT::i32, Source,
+ DAG.getConstant(SrcOff, MVT::i32)),
+ NULL, 0);
+ TFOps[i] = Loads[i].getValue(1);
+ SrcOff += VTSize;
+ }
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
+
+ for (i = 0;
+ i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
+ TFOps[i] = DAG.getStore(Chain, Loads[i],
+ DAG.getNode(ISD::ADD, MVT::i32, Dest,
+ DAG.getConstant(DstOff, MVT::i32)),
+ NULL, 0);
+ DstOff += VTSize;
+ }
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
- Op = Op.getOperand(0);
- SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
- &Op, 1);
-
- // Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1));
-}
+ EmittedNumMemOps += i;
+ }
-static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
- // FIXME: All this code is target-independent. Create a new target-indep
- // MULHILO node and move this code to the legalizer.
- //
- assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!");
-
- SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
- DAG.getConstant(0, MVT::i32));
- SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
- DAG.getConstant(0, MVT::i32));
+ if (BytesLeft == 0)
+ return Chain;
- const TargetLowering &TL = DAG.getTargetLoweringInfo();
- unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0));
- unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1));
-
- SDOperand Lo, Hi;
- // Figure out how to lower this multiply.
- if (LHSSB >= 33 && RHSSB >= 33) {
- // If the input values are both sign extended, we can emit a mulhs+mul.
- Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
- Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL);
- } else if (LHSSB == 32 && RHSSB == 32 &&
- TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
- TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
- // If the inputs are zero extended, use mulhu.
- Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
- Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL);
- } else {
- SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
- DAG.getConstant(1, MVT::i32));
- SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
- DAG.getConstant(1, MVT::i32));
-
- // Lo,Hi = umul LHS, RHS.
- SDOperand Ops[] = { LL, RL };
- SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU,
- DAG.getVTList(MVT::i32, MVT::i32), Ops, 2);
- Lo = UMul64;
- Hi = UMul64.getValue(1);
- RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH);
- LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL);
- Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH);
- Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH);
+ // Issue loads / stores for the trailing (1 - 3) bytes.
+ unsigned BytesLeftSave = BytesLeft;
+ i = 0;
+ while (BytesLeft) {
+ if (BytesLeft >= 2) {
+ VT = MVT::i16;
+ VTSize = 2;
+ } else {
+ VT = MVT::i8;
+ VTSize = 1;
+ }
+
+ Loads[i] = DAG.getLoad(VT, Chain,
+ DAG.getNode(ISD::ADD, MVT::i32, Source,
+ DAG.getConstant(SrcOff, MVT::i32)),
+ NULL, 0);
+ TFOps[i] = Loads[i].getValue(1);
+ ++i;
+ SrcOff += VTSize;
+ BytesLeft -= VTSize;
}
-
- // Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
-}
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
+
+ i = 0;
+ BytesLeft = BytesLeftSave;
+ while (BytesLeft) {
+ if (BytesLeft >= 2) {
+ VT = MVT::i16;
+ VTSize = 2;
+ } else {
+ VT = MVT::i8;
+ VTSize = 1;
+ }
-static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
- return DAG.getNode(ARMISD::MULHILOU,
- DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
+ TFOps[i] = DAG.getStore(Chain, Loads[i],
+ DAG.getNode(ISD::ADD, MVT::i32, Dest,
+ DAG.getConstant(DstOff, MVT::i32)),
+ NULL, 0);
+ ++i;
+ DstOff += VTSize;
+ BytesLeft -= VTSize;
+ }
+ return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
}
-static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) {
- SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
- return DAG.getNode(ARMISD::MULHILOS,
- DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
+static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
+ // Turn f64->i64 into FMRRD.
+ assert(N->getValueType(0) == MVT::i64 &&
+ N->getOperand(0).getValueType() == MVT::f64);
+
+ SDOperand Op = N->getOperand(0);
+ SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
+ &Op, 1);
+
+ // Merge the pieces into a single i64 value.
+ return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
}
-static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG,
- const ARMSubtarget *ST) {
- assert(Op.getValueType() == MVT::i64 &&
- (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
+static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
+ assert(N->getValueType(0) == MVT::i64 &&
+ (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
"Unknown shift to lower!");
// We only lower SRA, SRL of 1 here, all others use generic lowering.
- if (!isa<ConstantSDNode>(Op.getOperand(1)) ||
- cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1)
- return SDOperand();
+ if (!isa<ConstantSDNode>(N->getOperand(1)) ||
+ cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
+ return 0;
// If we are in thumb mode, we don't have RRX.
- if (ST->isThumb()) return SDOperand();
+ if (ST->isThumb()) return 0;
// Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
DAG.getConstant(0, MVT::i32));
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
DAG.getConstant(1, MVT::i32));
-
+
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
// captures the result into a carry flag.
- unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
+ unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
// The low part is an ARMISD::RRX operand, which shifts the carry in.
Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
}
+
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
default: assert(0 && "Don't know how to custom lower this!"); abort();
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
- case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
+ case ISD::GlobalAddress:
+ return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
+ LowerGlobalAddressELF(Op, DAG);
+ case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
case ISD::CALL: return LowerCALL(Op, DAG);
case ISD::RET: return LowerRET(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
- case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
- case ISD::MUL: return LowerMUL(Op, DAG);
- case ISD::MULHU: return LowerMULHU(Op, DAG);
- case ISD::MULHS: return LowerMULHS(Op, DAG);
- case ISD::SRL:
- case ISD::SRA: return LowerSRx(Op, DAG, Subtarget);
- case ISD::FORMAL_ARGUMENTS:
- return LowerFORMAL_ARGUMENTS(Op, DAG);
+ case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
+ case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
+ case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
+ case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
+
+
+ // FIXME: Remove these when LegalizeDAGTypes lands.
+ case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
+ case ISD::SRL:
+ case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
}
return SDOperand();
}
+
+/// ExpandOperationResult - Provide custom lowering hooks for expanding
+/// operations.
+SDNode *ARMTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
+ switch (N->getOpcode()) {
+ default: assert(0 && "Don't know how to custom expand this!"); abort();
+ case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG);
+ case ISD::SRL:
+ case ISD::SRA: return ExpandSRx(N, DAG, Subtarget);
+ }
+}
+
+
//===----------------------------------------------------------------------===//
// ARM Scheduler Hooks
//===----------------------------------------------------------------------===//
MachineBasicBlock *
-ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
+ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
switch (MI->getOpcode()) {
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
- .addImm(MI->getOperand(3).getImm());
+ .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
// ARM Optimization Hooks
//===----------------------------------------------------------------------===//
-/// isLegalAddressingMode - Return true if the addressing mode represented
-/// by AM is legal for this target, for a load/store of the specified type.
-bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
- const Type *Ty) const {
- if (!isLegalAddressImmediate(AM.BaseOffs, Ty))
- return false;
-
- // Can never fold addr of global into load/store.
- if (AM.BaseGV)
- return false;
-
- switch (AM.Scale) {
- case 0: // no scale reg, must be "r+i" or "r", or "i".
- break;
- case 1:
- if (Subtarget->isThumb())
- return false;
-
- default:
- switch (getValueType(Ty)) {
- default: return false;
- case MVT::i1:
- case MVT::i8:
- case MVT::i32:
- case MVT::i64:
- // This assumes i64 is legalized to a pair of i32. If not (i.e.
- // ldrd / strd are used, then its address mode is same as i16.
- // r + r
- if (AM.Scale == 1)
- return true;
- // r + r << imm
- if (!isPowerOf2_32(AM.Scale & ~1))
- return false;
- case MVT::i16:
- // r + r
- if (((unsigned)AM.HasBaseReg + AM.Scale) <= 2)
- return true;
+/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
+static SDOperand PerformFMRRDCombine(SDNode *N,
+ TargetLowering::DAGCombinerInfo &DCI) {
+ // fmrrd(fmdrr x, y) -> x,y
+ SDOperand InDouble = N->getOperand(0);
+ if (InDouble.getOpcode() == ARMISD::FMDRR)
+ return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
+ return SDOperand();
+}
- case MVT::isVoid:
- // Note, we allow "void" uses (basically, uses that aren't loads or
- // stores), because arm allows folding a scale into many arithmetic
- // operations. This should be made more precise and revisited later.
-
- // Allow r << imm, but the imm has to be a multiple of two.
- if (AM.Scale & 1) return false;
- return isPowerOf2_32(AM.Scale);
- }
- break;
+SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ switch (N->getOpcode()) {
+ default: break;
+ case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
}
- return true;
+
+ return SDOperand();
}
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
-bool ARMTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
+static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
+ const ARMSubtarget *Subtarget) {
if (V == 0)
return true;
- MVT::ValueType VT = getValueType(Ty);
if (Subtarget->isThumb()) {
if (V < 0)
return false;
if ((V & (Scale - 1)) != 0)
return false;
V /= Scale;
- return V == V & ((1LL << 5) - 1);
+ return V == (V & ((1LL << 5) - 1));
}
if (V < 0)
case MVT::i8:
case MVT::i32:
// +- imm12
- return V == V & ((1LL << 12) - 1);
+ return V == (V & ((1LL << 12) - 1));
case MVT::i16:
// +- imm8
- return V == V & ((1LL << 8) - 1);
+ return V == (V & ((1LL << 8) - 1));
case MVT::f32:
case MVT::f64:
if (!Subtarget->hasVFP2())
return false;
- if ((V % 3) != 0)
+ if ((V & 3) != 0)
return false;
V >>= 2;
- return V == V & ((1LL << 8) - 1);
+ return V == (V & ((1LL << 8) - 1));
}
}
-bool ARMTargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
- return false;
-}
-
-/// isLegalAddressScale - Return true if the integer value can be used as
-/// the scale of the target addressing mode for load / store of the given
-/// type.
-bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
- if (Subtarget->isThumb())
+/// isLegalAddressingMode - Return true if the addressing mode represented
+/// by AM is legal for this target, for a load/store of the specified type.
+bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
+ const Type *Ty) const {
+ if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
return false;
-
- MVT::ValueType VT = getValueType(Ty);
- switch (VT) {
- default: return false;
- case MVT::i1:
- case MVT::i8:
- case MVT::i32:
- if (S < 0) S = -S;
- if (S == 1) return true; // Allow: r + r
+
+ // Can never fold addr of global into load/store.
+ if (AM.BaseGV)
+ return false;
+
+ switch (AM.Scale) {
+ case 0: // no scale reg, must be "r+i" or "r", or "i".
+ break;
+ case 1:
+ if (Subtarget->isThumb())
+ return false;
+ // FALL THROUGH.
+ default:
+ // ARM doesn't support any R+R*scale+imm addr modes.
+ if (AM.BaseOffs)
+ return false;
+
+ int Scale = AM.Scale;
+ switch (getValueType(Ty)) {
+ default: return false;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i32:
+ case MVT::i64:
+ // This assumes i64 is legalized to a pair of i32. If not (i.e.
+ // ldrd / strd are used, then its address mode is same as i16.
+ // r + r
+ if (Scale < 0) Scale = -Scale;
+ if (Scale == 1)
+ return true;
+ // r + r << imm
+ return isPowerOf2_32(Scale & ~1);
+ case MVT::i16:
+ // r + r
+ if (((unsigned)AM.HasBaseReg + Scale) <= 2)
+ return true;
+ return false;
- // Allow: r << imm
- // Allow: r + r << imm
- S &= ~1;
- return isPowerOf2_32(S);
- case MVT::isVoid:
- // Note, we allow "void" uses (basically, uses that aren't loads or
- // stores), because arm allows folding a scale into many arithmetic
- // operations. This should be made more precise and revisited later.
- if (S == 1) return true; // Allow: r + r
-
- // Allow r << imm, but the imm has to be a multiple of two.
- if (S & 1) return false;
- return isPowerOf2_32(S);
+ case MVT::isVoid:
+ // Note, we allow "void" uses (basically, uses that aren't loads or
+ // stores), because arm allows folding a scale into many arithmetic
+ // operations. This should be made more precise and revisited later.
+
+ // Allow r << imm, but the imm has to be a multiple of two.
+ if (AM.Scale & 1) return false;
+ return isPowerOf2_32(AM.Scale);
+ }
+ break;
}
+ return true;
}
+
static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
bool isSEXTLoad, SDOperand &Base,
SDOperand &Offset, bool &isInc,
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
- VT = LD->getLoadedVT();
+ VT = LD->getMemoryVT();
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Ptr = ST->getBasePtr();
- VT = ST->getStoredVT();
+ VT = ST->getMemoryVT();
} else
return false;
SDOperand Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
- VT = LD->getLoadedVT();
+ VT = LD->getMemoryVT();
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
- VT = ST->getStoredVT();
+ VT = ST->getMemoryVT();
} else
return false;
}
void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
- uint64_t Mask,
- uint64_t &KnownZero,
- uint64_t &KnownOne,
+ const APInt &Mask,
+ APInt &KnownZero,
+ APInt &KnownOne,
+ const SelectionDAG &DAG,
unsigned Depth) const {
- KnownZero = 0;
- KnownOne = 0;
+ KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
switch (Op.getOpcode()) {
default: break;
case ARMISD::CMOV: {
// Bits are known zero/one if known on the LHS and RHS.
- ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+ DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
if (KnownZero == 0 && KnownOne == 0) return;
- uint64_t KnownZeroRHS, KnownOneRHS;
- ComputeMaskedBits(Op.getOperand(1), Mask,
- KnownZeroRHS, KnownOneRHS, Depth+1);
+ APInt KnownZeroRHS, KnownOneRHS;
+ DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
+ KnownZeroRHS, KnownOneRHS, Depth+1);
KnownZero &= KnownZeroRHS;
KnownOne &= KnownOneRHS;
return;
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