Fixes ARM LNT bot from SLP change in O3

[oota-llvm.git] / lib / Target / ARM / ARMExpandPseudoInsts.cpp

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 8ed6b751f3eff6ab1f30b7c656ec90b7d46bc7af..beb843ca9aa8eecc38368e986647e0b227de5e20 100644 (file)
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -23,10 +23,10 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/Target/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
+#include "llvm/Target/TargetFrameLowering.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 using namespace llvm;
 
 static cl::opt<bool>
@@ -103,9 +103,9 @@ namespace {
     bool IsLoad;
     bool isUpdating;
     bool hasWritebackOperand;
-    NEONRegSpacing RegSpacing;
-    unsigned char NumRegs; // D registers loaded or stored
-    unsigned char RegElts; // elements per D register; used for lane ops
+    uint8_t RegSpacing; // One of type NEONRegSpacing
+    uint8_t NumRegs; // D registers loaded or stored
+    uint8_t RegElts; // elements per D register; used for lane ops
     // FIXME: Temporary flag to denote whether the real instruction takes
     // a single register (like the encoding) or all of the registers in
     // the list (like the asm syntax and the isel DAG). When all definitions
@@ -377,7 +377,7 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
 
   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
   assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
-  NEONRegSpacing RegSpc = TableEntry->RegSpacing;
+  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
   unsigned NumRegs = TableEntry->NumRegs;
 
   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
@@ -442,7 +442,7 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
 
   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
   assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
-  NEONRegSpacing RegSpc = TableEntry->RegSpacing;
+  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
   unsigned NumRegs = TableEntry->NumRegs;
 
   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
@@ -493,7 +493,7 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
 
   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
   assert(TableEntry && "NEONLdStTable lookup failed");
-  NEONRegSpacing RegSpc = TableEntry->RegSpacing;
+  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
   unsigned NumRegs = TableEntry->NumRegs;
   unsigned RegElts = TableEntry->RegElts;
 
@@ -777,9 +777,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
       MI.eraseFromParent();
       return true;
     }
-    case ARM::Int_eh_sjlj_dispatchsetup:
-    case ARM::Int_eh_sjlj_dispatchsetup_nofp:
-    case ARM::tInt_eh_sjlj_dispatchsetup: {
+    case ARM::Int_eh_sjlj_dispatchsetup: {
       MachineFunction &MF = *MI.getParent()->getParent();
       const ARMBaseInstrInfo *AII =
         static_cast<const ARMBaseInstrInfo*>(TII);
@@ -1208,57 +1206,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
       ExpandLaneOp(MBBI);
       return true;
 
-    case ARM::VSETLNi8Q:
-    case ARM::VSETLNi16Q: {
-      // Expand VSETLNs acting on a Q register to equivalent VSETLNs acting
-      // on the respective D register.
-
-      unsigned QReg  = MI.getOperand(1).getReg();
-      unsigned QLane = MI.getOperand(3).getImm();
-
-      unsigned NewOpcode, DLane, DSubReg;
-      switch (Opcode) {
-      default: llvm_unreachable("Invalid opcode!");
-      case ARM::VSETLNi8Q:
-        // 4 possible 8-bit lanes per DPR:
-        NewOpcode = ARM::VSETLNi8;
-        DLane = QLane % 8;
-        DSubReg  = (QLane / 8) ? ARM::dsub_1 : ARM::dsub_0;
-        break;
-      case ARM::VSETLNi16Q:
-        // 4 possible 16-bit lanes per DPR.
-        NewOpcode = ARM::VSETLNi16;
-        DLane = QLane % 4;
-        DSubReg  = (QLane / 4) ? ARM::dsub_1 : ARM::dsub_0;
-        break;
-      }
-
-      MachineInstrBuilder MIB =
-        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpcode));
-
-      unsigned DReg = TRI->getSubReg(QReg, DSubReg);
-
-      MIB.addReg(DReg, RegState::Define); // Output DPR
-      MIB.addReg(DReg);                   // Input DPR
-      MIB.addOperand(MI.getOperand(2));   // Input GPR
-      MIB.addImm(DLane);                  // Lane
-
-      // Add the predicate operands.
-      MIB.addOperand(MI.getOperand(4));
-      MIB.addOperand(MI.getOperand(5));
-
-      if (MI.getOperand(1).isKill()) // Add an implicit kill for the Q register.
-        MIB->addRegisterKilled(QReg, TRI, true);
-      // And an implicit def of the output register (which should always be the
-      // same as the input register).
-      MIB->addRegisterDefined(QReg, TRI);
-
-      TransferImpOps(MI, MIB, MIB);
-
-      MI.eraseFromParent();
-      return true;
-    }
-
     case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
     case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
     case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;