//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Chris Lattner and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
: MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
};
- /// Branches - Keep track of all the immediate branch instructions.
+ /// ImmBranches - Keep track of all the immediate branch instructions.
///
std::vector<ImmBranch> ImmBranches;
MachineInstr *CPEMI, unsigned Disp,
bool DoDump);
bool WaterIsInRange(unsigned UserOffset, MachineBasicBlock *Water,
- unsigned Disp);
+ CPUser &U);
bool OffsetIsInRange(unsigned UserOffset, unsigned TrialOffset,
unsigned Disp, bool NegativeOK);
bool BBIsInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
/// print block size and offset information - debugging
void ARMConstantIslands::dumpBBs() {
for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) {
- DOUT << "block" << J << " offset" << BBOffsets[J] <<
- " size" << BBSizes[J] << "\n";
+ DOUT << "block " << J << " offset " << BBOffsets[J] <<
+ " size " << BBSizes[J] << "\n";
}
}
const TargetData &TD = *Fn.getTarget().getTargetData();
for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
- unsigned Size = TD.getTypeSize(CPs[i].getType());
+ unsigned Size = TD.getABITypeSize(CPs[i].getType());
// Verify that all constant pool entries are a multiple of 4 bytes. If not,
// we would have to pad them out or something so that instructions stay
// aligned.
/// Water (a basic block) will be in range for the specific MI.
bool ARMConstantIslands::WaterIsInRange(unsigned UserOffset,
- MachineBasicBlock* Water, unsigned MaxDisp)
+ MachineBasicBlock* Water, CPUser &U)
{
+ unsigned MaxDisp = U.MaxDisp;
MachineFunction::iterator I = next(MachineFunction::iterator(Water));
unsigned CPEOffset = BBOffsets[Water->getNumber()] +
BBSizes[Water->getNumber()];
// the offset of the instruction. (Currently applies only to ARM, so
// no alignment compensation attempted here.)
if (CPEOffset < UserOffset)
- UserOffset += 4;
+ UserOffset += U.CPEMI->getOperand(2).getImm();
return OffsetIsInRange (UserOffset, CPEOffset, MaxDisp, !isThumb);
}
delta -= 2;
}
}
- // Thumb jump tables require padding. They can be at the end, or
- // followed by an unconditional branch.
+ // Thumb jump tables require padding. They should be at the end;
+ // following unconditional branches are removed by AnalyzeBranch.
MachineInstr *ThumbJTMI = NULL;
if (prior(MBB->end())->getOpcode() == ARM::tBR_JTr)
ThumbJTMI = prior(MBB->end());
- else if (prior(MBB->end()) != MBB->begin() &&
- prior(prior(MBB->end()))->getOpcode() == ARM::tBR_JTr)
- ThumbJTMI = prior(prior(MBB->end()));
if (ThumbJTMI) {
unsigned newMIOffset = GetOffsetOf(ThumbJTMI);
unsigned oldMIOffset = newMIOffset - delta;
for (std::vector<MachineBasicBlock*>::iterator IP = prior(WaterList.end()),
B = WaterList.begin();; --IP) {
MachineBasicBlock* WaterBB = *IP;
- if (WaterIsInRange(UserOffset, WaterBB, U.MaxDisp)) {
+ if (WaterIsInRange(UserOffset, WaterBB, U)) {
if (isThumb &&
(BBOffsets[WaterBB->getNumber()] +
BBSizes[WaterBB->getNumber()])%4 != 0) {
// L2:
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
CC = ARMCC::getOppositeCondition(CC);
+ unsigned CCReg = MI->getOperand(2).getReg();
// If the branch is at the end of its MBB and that has a fall-through block,
// direct the updated conditional branch to the fall-through block. Otherwise,
// Insert a new conditional branch and a new unconditional branch.
// Also update the ImmBranch as well as adding a new entry for the new branch.
- BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB).addImm(CC);
+ BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB)
+ .addImm(CC).addReg(CCReg);
Br.MI = &MBB->back();
BBSizes[MBB->getNumber()] += ARM::GetInstSize(&MBB->back());
BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB);
bool MadeChange = false;
for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
MachineInstr *MI = PushPopMIs[i];
- if (MI->getNumOperands() == 1) {
- if (MI->getOpcode() == ARM::tPOP_RET &&
- MI->getOperand(0).getReg() == ARM::PC)
- BuildMI(MI->getParent(), TII->get(ARM::tBX_RET));
- MI->eraseFromParent();
- MadeChange = true;
+ if (MI->getOpcode() == ARM::tPOP_RET &&
+ MI->getOperand(0).getReg() == ARM::PC &&
+ MI->getNumExplicitOperands() == 1) {
+ BuildMI(MI->getParent(), TII->get(ARM::tBX_RET));
+ MI->eraseFromParent();
+ MadeChange = true;
}
}
return MadeChange;