Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool

[oota-llvm.git] / lib / Target / ARM / ARMCodeEmitter.cpp

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 479152b15fa3880b3fcd5e7cef779793d95409d5..f4ee6b0f64997dc5cc98859de7408c004ad9033b 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -55,7 +55,7 @@ namespace {
 
     void emitInstruction(const MachineInstr &MI);
     int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
-    unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
+    unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
     unsigned getBinaryCodeForInstr(const MachineInstr &MI);
 
     void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
@@ -103,8 +103,8 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
 }
 
 /// getBaseOpcodeFor - Return the opcode value
-unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
-  return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
+unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
+  return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
 }
 
 /// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
@@ -134,7 +134,7 @@ int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
   intptr_t rv = 0;
   const MachineOperand &MO = MI.getOperand(OpIndex);
   if (MO.isRegister()) {
-    assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
+    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
     rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
   } else if (MO.isImmediate()) {
     rv = MO.getImm();
@@ -143,11 +143,11 @@ int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
   } else if (MO.isExternalSymbol()) {
     emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
   } else if (MO.isConstantPoolIndex()) {
-    emitConstPoolAddress(MO.getConstantPoolIndex(), ARM::reloc_arm_relative);
+    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
   } else if (MO.isJumpTableIndex()) {
-    emitJumpTableAddress(MO.getJumpTableIndex(), ARM::reloc_arm_relative);
+    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
   } else if (MO.isMachineBasicBlock()) {
-    emitMachineBasicBlock(MO.getMachineBasicBlock());
+    emitMachineBasicBlock(MO.getMBB());
   }
 
   return rv;
@@ -201,15 +201,15 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
 }
 
 unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
-  const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
-  const unsigned opcode = MI.getOpcode();
+  const TargetInstrDesc &Desc = MI.getDesc();
+  unsigned opcode = Desc.Opcode;
   // initial instruction mask
   unsigned Value = 0xE0000000;
   unsigned op;
 
-  switch (Desc->TSFlags & ARMII::AddrModeMask) {
+  switch (Desc.TSFlags & ARMII::AddrModeMask) {
   case ARMII::AddrModeNone: {
-    switch(Desc->TSFlags & ARMII::FormMask) {
+    switch(Desc.TSFlags & ARMII::FormMask) {
     default: {
       assert(0 && "Unknown instruction subtype!");
       // treat special instruction CLZ
@@ -241,7 +241,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
       unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
       Value |= BaseOpcode << 4;
 
-      unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+      unsigned Format = (Desc.TSFlags & ARMII::FormMask);
       if (Format == ARMII::MulSMUL)
         Value |= 1 << 22;
 
@@ -342,7 +342,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
 
     // treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
     // MOVrx.
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     if (Format == ARMII::DPRdMisc) {
       Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
       Value |= getMachineOpValue(MI,1);
@@ -475,10 +475,10 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
         }
       }
       // set the field related to shift operations (except rrx).
-      if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
-        if(IsShiftByRegister) {
+      if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
+        if (IsShiftByRegister) {
           // set the value of bit[11:8] (register Rs).
-          assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
+          assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
           op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
           assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
           Value |= op << ARMII::RegRsShift;
@@ -487,6 +487,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
           op = ARM_AM::getSORegOffset(MO2.getImm());
           Value |= op << 7;
         }
+      }
       break;
     }
     default: assert(false && "Unknown operand type!");
@@ -499,7 +500,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     // bit 26 is always 1
     Value |= 1 << 26;
 
-    unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+    unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
     // if the instruction uses offset addressing or pre-indexed addressing,
     // set bit P(24) to 1
     if (Index == ARMII::IndexModePre || Index == 0)
@@ -508,7 +509,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     if (Index == ARMII::IndexModePre)
       Value |= 1 << 21;
 
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     // If it is a load instruction (except LDRD), set bit L(20) to 1
     if (Format == ARMII::LdFrm)
       Value |= 1 << ARMII::L_BitShift;
@@ -540,7 +541,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
 
     // set bit I(25), because this is not in immediate enconding.
     Value |= 1 << ARMII::I_BitShift;
-    assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
+    assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
     // set bit[3:0] to the corresponding Rm register
     Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
 
@@ -555,14 +556,13 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     break;
   }
   case ARMII::AddrMode3: {
-
-    unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+    unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
     // if the instruction uses offset addressing or pre-indexed addressing,
     // set bit P(24) to 1
     if (Index == ARMII::IndexModePre || Index == 0)
       Value |= 1 << ARMII::IndexShift;
 
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     // If it is a load instruction (except LDRD), set bit L(20) to 1
     if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
       Value |= 1 << ARMII::L_BitShift;
@@ -607,7 +607,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     // bit 27 is always 1
     Value |= 1 << 27;
 
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     // if it is a load instr, set bit L(20) to 1
     if (Format == ARMII::LdFrm)
       Value |= 1 << ARMII::L_BitShift;
@@ -641,7 +641,8 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) {
       const MachineOperand &MOR = MI.getOperand(i);
       unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg());
-      assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16);
+      assert(TargetRegisterInfo::isPhysicalRegister(MOR.getReg()) &&
+             RegNumber < 16);
       Value |= 0x1 << RegNumber;
     }