-//===- ARMBaseRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
+//===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// Return the opcode that implements 'Op', or 0 if no opcode
unsigned getOpcode(int Op) const;
- // If 'opcode' is an instruction with an unsigned offset that also
- // has a version with a signed offset, return the opcode for the
- // version with the signed offset. In 'NumBits' return the number of
- // bits for the signed offset.
- unsigned unsignedOffsetOpcodeToSigned(unsigned opcode,
- unsigned *NumBits) const;
-
public:
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// ARM::LR, return the number that it corresponds to (e.g. 14). It
BitVector getReservedRegs(const MachineFunction &MF) const;
- const TargetRegisterClass *getPointerRegClass() const;
+ const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
getAllocationOrder(const TargetRegisterClass *RC,
bool hasFP(const MachineFunction &MF) const;
+ bool cannotEliminateFrame(const MachineFunction &MF) const;
+
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS = NULL) const;
virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
private:
+ unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
+
unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;