#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallString.h"
-#include "llvm/Constants.h"
-#include "llvm/DebugInfo.h"
-#include "llvm/Module.h"
-#include "llvm/Type.h"
#include "llvm/Assembly/Writer.h"
-#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/DebugInfo.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h"
-#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCObjectStreamer.h"
+#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/DataLayout.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/Mangler.h"
+#include "llvm/Target/TargetMachine.h"
#include <cctype>
using namespace llvm;
const size_t TagHeaderSize = 1 + 4;
Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
- Streamer.EmitBytes(CurrentVendor, 0);
+ Streamer.EmitBytes(CurrentVendor);
Streamer.EmitIntValue(0, 1); // '\0'
Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
// emit each field as its type (ULEB or String)
for (unsigned int i=0; i<Contents.size(); ++i) {
AttributeItemType item = Contents[i];
- Streamer.EmitULEB128IntValue(item.Tag, 0);
+ Streamer.EmitULEB128IntValue(item.Tag);
switch (item.Type) {
default: llvm_unreachable("Invalid attribute type");
case AttributeItemType::NumericAttribute:
- Streamer.EmitULEB128IntValue(item.IntValue, 0);
+ Streamer.EmitULEB128IntValue(item.IntValue);
break;
case AttributeItemType::TextAttribute:
- Streamer.EmitBytes(item.StringValue.upper(), 0);
+ Streamer.EmitBytes(item.StringValue.upper());
Streamer.EmitIntValue(0, 1); // '\0'
break;
}
unsigned Reg = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
assert(!MO.getSubReg() && "Subregs should be eliminated!");
+ if(ARM::GPRPairRegClass.contains(Reg)) {
+ const MachineFunction &MF = *MI->getParent()->getParent();
+ const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
+ Reg = TRI->getSubReg(Reg, ARM::gsub_0);
+ }
O << ARMInstPrinter::getRegisterName(Reg);
break;
}
const MachineOperand &MO = MI->getOperand(OpNum);
if (!MO.isReg())
return true;
- const TargetRegisterClass &RC = ARM::GPRRegClass;
const MachineFunction &MF = *MI->getParent()->getParent();
const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
-
- unsigned RegIdx = TRI->getEncodingValue(MO.getReg());
- RegIdx |= 1; //The odd register is also the higher-numbered one of a pair.
-
- unsigned Reg = RC.getRegister(RegIdx);
+ unsigned Reg = MO.getReg();
+ if(!ARM::GPRPairRegClass.contains(Reg))
+ return false;
+ Reg = TRI->getSubReg(Reg, ARM::gsub_1);
O << ARMInstPrinter::getRegisterName(Reg);
return false;
}
if (MCSym.getInt())
// External to current translation unit.
- OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
+ OutStreamer.EmitIntValue(0, 4/*size*/);
else
// Internal to current translation unit.
//
// We need to fill in the value for the NLP in those cases.
OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
OutContext),
- 4/*size*/, 0/*addrspace*/);
+ 4/*size*/);
}
Stubs.clear();
OutStreamer.EmitValue(MCSymbolRefExpr::
Create(Stubs[i].second.getPointer(),
OutContext),
- 4/*size*/, 0/*addrspace*/);
+ 4/*size*/);
}
Stubs.clear();
// generates code that does this, it is always safe to set.
OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
}
+ // FIXME: This should eventually end up somewhere else where more
+ // intelligent flag decisions can be made. For now we are just maintaining
+ // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
+ if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&OutStreamer))
+ MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
}
//===----------------------------------------------------------------------===//
OutContext);
// If this isn't a TBB or TBH, the entries are direct branch instructions.
if (OffsetWidth == 4) {
- MCInstBuilder(ARM::t2B)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
.addExpr(MBBSymbolExpr)
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
continue;
}
// Otherwise it's an offset from the dispatch instruction. Construct an
case ARM::t2LEApcrel: {
// FIXME: Need to also handle globals and externals
MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
- MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
+ OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
+ ARM::t2LEApcrel ? ARM::t2ADR
: (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
: ARM::ADR))
.addReg(MI->getOperand(0).getReg())
.addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
// Add predicate operands.
.addImm(MI->getOperand(2).getImm())
- .addReg(MI->getOperand(3).getReg())
- .emit(OutStreamer);
+ .addReg(MI->getOperand(3).getReg()));
return;
}
case ARM::LEApcrelJT:
MCSymbol *JTIPICSymbol =
GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
MI->getOperand(2).getImm());
- MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
+ OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
+ ARM::t2LEApcrelJT ? ARM::t2ADR
: (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
: ARM::ADR))
.addReg(MI->getOperand(0).getReg())
.addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
// Add predicate operands.
.addImm(MI->getOperand(3).getImm())
- .addReg(MI->getOperand(4).getReg())
- .emit(OutStreamer);
+ .addReg(MI->getOperand(4).getReg()));
return;
}
// Darwin call instructions are just normal call instructions with different
// clobber semantics (they clobber R9).
case ARM::BX_CALL: {
- MCInstBuilder(ARM::MOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::LR)
.addReg(ARM::PC)
// Add predicate operands.
.addImm(ARMCC::AL)
.addReg(0)
// Add 's' bit operand (always reg0 for this)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::BX)
- .addReg(MI->getOperand(0).getReg())
- .emit(OutStreamer);
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
+ .addReg(MI->getOperand(0).getReg()));
return;
}
case ARM::tBX_CALL: {
- MCInstBuilder(ARM::tMOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ARM::LR)
.addReg(ARM::PC)
// Add predicate operands.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tBX)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
.addReg(MI->getOperand(0).getReg())
// Add predicate operands.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
case ARM::BMOVPCRX_CALL: {
- MCInstBuilder(ARM::MOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::LR)
.addReg(ARM::PC)
// Add predicate operands.
.addImm(ARMCC::AL)
.addReg(0)
// Add 's' bit operand (always reg0 for this)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::MOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::PC)
- .addImm(MI->getOperand(0).getReg())
+ .addReg(MI->getOperand(0).getReg())
// Add predicate operands.
.addImm(ARMCC::AL)
.addReg(0)
// Add 's' bit operand (always reg0 for this)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
case ARM::BMOVPCB_CALL: {
- MCInstBuilder(ARM::MOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
.addReg(ARM::LR)
.addReg(ARM::PC)
// Add predicate operands.
.addImm(ARMCC::AL)
.addReg(0)
// Add 's' bit operand (always reg0 for this)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
const GlobalValue *GV = MI->getOperand(0).getGlobal();
MCSymbol *GVSym = Mang->getSymbol(GV);
const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
- MCInstBuilder(ARM::Bcc)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
.addExpr(GVSymExpr)
// Add predicate operands.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
case ARM::MOVi16_ga_pcrel:
OutContext));
// Form and emit the add.
- MCInstBuilder(ARM::tADDhirr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(0).getReg())
.addReg(ARM::PC)
// Add predicate operands.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
case ARM::PICADD: {
OutContext));
// Form and emit the add.
- MCInstBuilder(ARM::ADDrr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
.addReg(MI->getOperand(0).getReg())
.addReg(ARM::PC)
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(3).getImm())
.addReg(MI->getOperand(4).getReg())
// Add 's' bit operand (always reg0 for this)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
case ARM::PICSTR:
case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
}
- MCInstBuilder(Opcode)
+ OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
.addReg(MI->getOperand(0).getReg())
.addReg(ARM::PC)
.addReg(MI->getOperand(1).getReg())
.addImm(0)
// Add predicate operands.
.addImm(MI->getOperand(3).getImm())
- .addReg(MI->getOperand(4).getReg())
- .emit(OutStreamer);
+ .addReg(MI->getOperand(4).getReg()));
return;
}
}
case ARM::t2BR_JT: {
// Lower and emit the instruction itself, then the jump table following it.
- MCInstBuilder(ARM::tMOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg())
// Add predicate operands.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
// Output the data for the jump table itself
EmitJump2Table(MI);
}
case ARM::t2TBB_JT: {
// Lower and emit the instruction itself, then the jump table following it.
- MCInstBuilder(ARM::t2TBB)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
.addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg())
// Add predicate operands.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
// Output the data for the jump table itself
EmitJump2Table(MI);
}
case ARM::t2TBH_JT: {
// Lower and emit the instruction itself, then the jump table following it.
- MCInstBuilder(ARM::t2TBH)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
.addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg())
// Add predicate operands.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
// Output the data for the jump table itself
EmitJump2Table(MI);
case ARM::BR_JTadd: {
// Lower and emit the instruction itself, then the jump table following it.
// add pc, target, idx
- MCInstBuilder(ARM::ADDrr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
.addReg(ARM::PC)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(ARMCC::AL)
.addReg(0)
// Add 's' bit operand (always reg0 for this)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
// Output the data for the jump table itself
EmitJumpTable(MI);
}
break;
}
+ case ARM::TRAPNaCl: {
+ //.long 0xe7fedef0 @ trap
+ uint32_t Val = 0xe7fedef0UL;
+ OutStreamer.AddComment("trap");
+ OutStreamer.EmitIntValue(Val, 4);
+ return;
+ }
case ARM::tTRAP: {
// Non-Darwin binutils don't yet support the "trap" mnemonic.
// FIXME: Remove this special case when they do.
unsigned ValReg = MI->getOperand(1).getReg();
MCSymbol *Label = GetARMSJLJEHLabel();
OutStreamer.AddComment("eh_setjmp begin");
- MCInstBuilder(ARM::tMOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ValReg)
.addReg(ARM::PC)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tADDi3)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
.addReg(ValReg)
// 's' bit operand
.addReg(ARM::CPSR)
.addImm(7)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tSTRi)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
.addReg(ValReg)
.addReg(SrcReg)
// The offset immediate is #4. The operand value is scaled by 4 for the
.addImm(1)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tMOVi8)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
.addReg(ARM::R0)
.addReg(ARM::CPSR)
.addImm(0)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
- MCInstBuilder(ARM::tB)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
.addExpr(SymbolExpr)
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
OutStreamer.AddComment("eh_setjmp end");
- MCInstBuilder(ARM::tMOVi8)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
.addReg(ARM::R0)
.addReg(ARM::CPSR)
.addImm(1)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
OutStreamer.EmitLabel(Label);
return;
unsigned ValReg = MI->getOperand(1).getReg();
OutStreamer.AddComment("eh_setjmp begin");
- MCInstBuilder(ARM::ADDri)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
.addReg(ValReg)
.addReg(ARM::PC)
.addImm(8)
.addImm(ARMCC::AL)
.addReg(0)
// 's' bit operand (always reg0 for this).
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::STRi12)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
.addReg(ValReg)
.addReg(SrcReg)
.addImm(4)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::MOVi)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
.addReg(ARM::R0)
.addImm(0)
// Predicate.
.addImm(ARMCC::AL)
.addReg(0)
// 's' bit operand (always reg0 for this).
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::ADDri)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
.addReg(ARM::PC)
.addReg(ARM::PC)
.addImm(0)
.addImm(ARMCC::AL)
.addReg(0)
// 's' bit operand (always reg0 for this).
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
OutStreamer.AddComment("eh_setjmp end");
- MCInstBuilder(ARM::MOVi)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
.addReg(ARM::R0)
.addImm(1)
// Predicate.
.addImm(ARMCC::AL)
.addReg(0)
// 's' bit operand (always reg0 for this).
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
case ARM::Int_eh_sjlj_longjmp: {
// bx $scratch
unsigned SrcReg = MI->getOperand(0).getReg();
unsigned ScratchReg = MI->getOperand(1).getReg();
- MCInstBuilder(ARM::LDRi12)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
.addReg(ARM::SP)
.addReg(SrcReg)
.addImm(8)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::LDRi12)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
.addReg(ScratchReg)
.addReg(SrcReg)
.addImm(4)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::LDRi12)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
.addReg(ARM::R7)
.addReg(SrcReg)
.addImm(0)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::BX)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
.addReg(ScratchReg)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
case ARM::tInt_eh_sjlj_longjmp: {
// bx $scratch
unsigned SrcReg = MI->getOperand(0).getReg();
unsigned ScratchReg = MI->getOperand(1).getReg();
- MCInstBuilder(ARM::tLDRi)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
.addReg(ScratchReg)
.addReg(SrcReg)
// The offset immediate is #8. The operand value is scaled by 4 for the
.addImm(2)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tMOVr)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
.addReg(ARM::SP)
.addReg(ScratchReg)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tLDRi)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
.addReg(ScratchReg)
.addReg(SrcReg)
.addImm(1)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tLDRi)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
.addReg(ARM::R7)
.addReg(SrcReg)
.addImm(0)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
- MCInstBuilder(ARM::tBX)
+ OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
.addReg(ScratchReg)
// Predicate.
.addImm(ARMCC::AL)
- .addReg(0)
- .emit(OutStreamer);
+ .addReg(0));
return;
}
}
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