class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
-class Triple;
+class TargetTuple;
class raw_pwrite_stream;
class raw_ostream;
MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU);
+ const TargetTuple &TT, StringRef CPU);
MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
raw_pwrite_stream &OS);