AMDGPU: Remove unused multiclass argument

[oota-llvm.git] / lib / Target / AMDGPU / AMDGPURegisterInfo.h

diff --git a/lib/Target/AMDGPU/AMDGPURegisterInfo.h b/lib/Target/AMDGPU/AMDGPURegisterInfo.h
index 5863807a1392322e2d96791c5979a20f08bef77f..cfd800bdc7030a38a4258e153c722b66f9fb4573 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPURegisterInfo.h
+++ b/lib/Target/AMDGPU/AMDGPURegisterInfo.h
@@ -7,36 +7,58 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file contains the TargetRegisterInfo interface that is implemented
-// by all hw codegen targets.
+/// \file
+/// \brief TargetRegisterInfo interface that is implemented by all hw codegen
+/// targets.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef AMDGPUREGISTERINFO_H_
-#define AMDGPUREGISTERINFO_H_
+#ifndef LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
+#define LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
 
-#include "AMDILRegisterInfo.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+
+#define GET_REGINFO_HEADER
+#define GET_REGINFO_ENUM
+#include "AMDGPUGenRegisterInfo.inc"
 
 namespace llvm {
 
-class AMDGPUTargetMachine;
+class AMDGPUSubtarget;
 class TargetInstrInfo;
 
-struct AMDGPURegisterInfo : public AMDILRegisterInfo
-{
-  AMDGPUTargetMachine &TM;
-  const TargetInstrInfo &TII;
+struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
+  static const MCPhysReg CalleeSavedReg;
+
+  AMDGPURegisterInfo();
+
+  BitVector getReservedRegs(const MachineFunction &MF) const override {
+    assert(!"Unimplemented");  return BitVector();
+  }
+
+  virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
+    assert(!"Unimplemented"); return nullptr;
+  }
+
+  virtual unsigned getHWRegIndex(unsigned Reg) const {
+    assert(!"Unimplemented"); return 0;
+  }
+
+  /// \returns the sub reg enum value for the given \p Channel
+  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
+  unsigned getSubRegFromChannel(unsigned Channel) const;
 
-  AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+  const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
+  void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
+                           unsigned FIOperandNum,
+                           RegScavenger *RS) const override;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
-  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+  unsigned getIndirectSubReg(unsigned IndirectIndex) const;
 
-  /// getISARegClass - rc is an AMDIL reg class.  This function returns the
-  /// ISA reg class that is equivalent to the given AMDIL reg class.
-  virtual const TargetRegisterClass *
-    getISARegClass(const TargetRegisterClass * rc) const = 0;
 };
 
 } // End namespace llvm
 
-#endif // AMDIDSAREGISTERINFO_H_
+#endif