#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/EndianStream.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
AArch64MCCodeEmitter(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
void operator=(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT
public:
- AArch64MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
- MCContext &ctx)
- : Ctx(ctx) {}
+ AArch64MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) : Ctx(ctx) {}
- ~AArch64MCCodeEmitter() {}
+ ~AArch64MCCodeEmitter() override {}
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
- void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; }
-
- void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
- // Output the constant in little endian byte order.
- for (unsigned i = 0; i != Size; ++i) {
- EmitByte(Val & 255, OS);
- Val >>= 8;
- }
- }
-
- void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+ void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
- const MCSubtargetInfo &STI,
MCContext &Ctx) {
- return new AArch64MCCodeEmitter(MCII, STI, Ctx);
+ return new AArch64MCCodeEmitter(MCII, Ctx);
}
/// getMachineOpValue - Return binary encoding of operand. If the machine
else {
assert(MO.isExpr() && "unable to encode load/store imm operand");
MCFixupKind Kind = MCFixupKind(FixupKind);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
}
MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
: MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
- Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
MCNumFixups += 1;
// Encode the 12 bits of the fixup.
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
- Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
++MCNumFixups;
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
return MO.getImm();
assert(MO.isExpr() && "Unexpected movz/movk immediate");
- Fixups.push_back(MCFixup::Create(
+ Fixups.push_back(MCFixup::create(
0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
++MCNumFixups;
assert(MO.isExpr() && "Unexpected ADR target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch14);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
MCFixupKind Kind = MI.getOpcode() == AArch64::BL
? MCFixupKind(AArch64::fixup_aarch64_pcrel_call26)
: MCFixupKind(AArch64::fixup_aarch64_pcrel_branch26);
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
+ Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
return 3;
}
- assert(false && "Invalid value for vector shift amount!");
- return 0;
+ llvm_unreachable("Invalid value for vector shift amount!");
}
uint32_t
return EncodedValue & ~(1u << 30);
}
-void AArch64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MI.getOpcode() == AArch64::TLSDESCCALL) {
// following (BLR) instruction. It doesn't emit any code itself so it
// doesn't go through the normal TableGenerated channels.
MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
- Fixups.push_back(MCFixup::Create(0, MI.getOperand(0).getExpr(), Fixup));
+ Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
return;
}
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
- EmitConstant(Binary, 4, OS);
+ support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
++MCNumEmitted; // Keep track of the # of mi's emitted.
}