64, (sequence "D%u", 0, 31)>;
def FPR128 : RegisterClass<"AArch64",
- [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+ [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 31)>;
def FPR64Lo : RegisterClass<"AArch64",
64, (sequence "D%u", 0, 15)>;
def FPR128Lo : RegisterClass<"AArch64",
- [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+ [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 15)>;
//===----------------------------------------------------------------------===//