//===----------------------------------------------------------------------===//
void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
- Triple TT(TM.getTargetTriple());
+ const Triple &TT = TM.getTargetTriple();
if (TT.isOSBinFormatMachO()) {
// Funny Darwin hack: This flag tells the linker that no global symbols
// contain code that falls through to other global symbols (e.g. the obvious
// avoid addends on the relocation?), ELF has no such concept and
// uses a normal private symbol.
if (getDataLayout().getLinkerPrivateGlobalPrefix()[0])
- return OutContext.GetOrCreateSymbol(
+ return OutContext.getOrCreateSymbol(
Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
Twine(getFunctionNumber()) + "_" + Twine(CPID));
- return OutContext.GetOrCreateSymbol(
+ return OutContext.getOrCreateSymbol(
Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
Twine(getFunctionNumber()) + "_" + Twine(CPID));
}
// FIXME: Can we get anything other than a plain symbol here?
assert(!MO.getTargetFlags() && "Unknown operand target flag!");
- O << *Sym;
+ Sym->print(O, MAI);
printOffset(MO.getOffset(), O);
break;
}
case AArch64::TCRETURNri: {
MCInst TmpInst;
TmpInst.setOpcode(AArch64::BR);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
MCInst Adrp;
Adrp.setOpcode(AArch64::ADRP);
- Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Adrp.addOperand(MCOperand::createReg(AArch64::X0));
Adrp.addOperand(SymTLSDesc);
EmitToStreamer(*OutStreamer, Adrp);
MCInst Ldr;
Ldr.setOpcode(AArch64::LDRXui);
- Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
- Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Ldr.addOperand(MCOperand::createReg(AArch64::X1));
+ Ldr.addOperand(MCOperand::createReg(AArch64::X0));
Ldr.addOperand(SymTLSDescLo12);
- Ldr.addOperand(MCOperand::CreateImm(0));
+ Ldr.addOperand(MCOperand::createImm(0));
EmitToStreamer(*OutStreamer, Ldr);
MCInst Add;
Add.setOpcode(AArch64::ADDXri);
- Add.addOperand(MCOperand::CreateReg(AArch64::X0));
- Add.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Add.addOperand(MCOperand::createReg(AArch64::X0));
+ Add.addOperand(MCOperand::createReg(AArch64::X0));
Add.addOperand(SymTLSDescLo12);
- Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
+ Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
EmitToStreamer(*OutStreamer, Add);
// Emit a relocation-annotation. This expands to no code, but requests
MCInst Blr;
Blr.setOpcode(AArch64::BLR);
- Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
+ Blr.addOperand(MCOperand::createReg(AArch64::X1));
EmitToStreamer(*OutStreamer, Blr);
return;