#include "llvm/Support/TargetParser.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Twine.h"
#include <cctype>
using namespace llvm;
// features they correspond to (use getFPUFeatures).
// FIXME: TableGen this.
// The entries must appear in the order listed in ARM::FPUKind for correct indexing
-struct {
- const char * Name;
+static const struct {
+ const char *NameCStr;
+ size_t NameLength;
ARM::FPUKind ID;
ARM::FPUVersion FPUVersion;
ARM::NeonSupportLevel NeonSupport;
ARM::FPURestriction Restriction;
+
+ StringRef getName() const { return StringRef(NameCStr, NameLength); }
} FPUNames[] = {
#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
- { NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION },
+ { NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION },
#include "llvm/Support/ARMTargetParser.def"
};
// of the triples and are not conforming with their official names.
// Check to see if the expectation should be changed.
// FIXME: TableGen this.
-struct {
- const char *Name;
+static const struct {
+ const char *NameCStr;
+ size_t NameLength;
+ const char *CPUAttrCStr;
+ size_t CPUAttrLength;
+ const char *SubArchCStr;
+ size_t SubArchLength;
+ unsigned DefaultFPU;
+ unsigned ArchBaseExtensions;
ARM::ArchKind ID;
- const char *CPUAttr; // CPU class in build attributes.
- const char *SubArch; // Sub-Arch name.
ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
+
+ StringRef getName() const { return StringRef(NameCStr, NameLength); }
+
+ // CPU class in build attributes.
+ StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
+
+ // Sub-Arch name.
+ StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
} ARCHNames[] = {
-#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR) \
- { NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR },
+#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
+ {NAME, sizeof(NAME) - 1, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \
+ sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, ID, ARCH_ATTR},
#include "llvm/Support/ARMTargetParser.def"
};
+
// List of Arch Extension names.
// FIXME: TableGen this.
-struct {
- const char *Name;
+static const struct {
+ const char *NameCStr;
+ size_t NameLength;
unsigned ID;
+ const char *Feature;
+ const char *NegFeature;
+
+ StringRef getName() const { return StringRef(NameCStr, NameLength); }
} ARCHExtNames[] = {
-#define ARM_ARCH_EXT_NAME(NAME, ID) { NAME, ID },
+#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
+ { NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE },
#include "llvm/Support/ARMTargetParser.def"
};
+
// List of HWDiv names (use getHWDivSynonym) and which architectural
// features they correspond to (use getHWDivFeatures).
// FIXME: TableGen this.
-struct {
- const char *Name;
+static const struct {
+ const char *NameCStr;
+ size_t NameLength;
unsigned ID;
+
+ StringRef getName() const { return StringRef(NameCStr, NameLength); }
} HWDivNames[] = {
-#define ARM_HW_DIV_NAME(NAME, ID) { NAME, ID },
+#define ARM_HW_DIV_NAME(NAME, ID) { NAME, sizeof(NAME) - 1, ID },
#include "llvm/Support/ARMTargetParser.def"
};
+
// List of CPU names and their arches.
// The same CPU can have multiple arches and can be default on multiple arches.
// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
// When this becomes table-generated, we'd probably need two tables.
// FIXME: TableGen this.
-struct {
- const char *Name;
+static const struct {
+ const char *NameCStr;
+ size_t NameLength;
ARM::ArchKind ArchID;
- ARM::FPUKind DefaultFPU;
bool Default; // is $Name the default CPU for $ArchID ?
+ unsigned DefaultExtensions;
+
+ StringRef getName() const { return StringRef(NameCStr, NameLength); }
} CPUNames[] = {
-#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT) \
- { NAME, ID, DEFAULT_FPU, IS_DEFAULT },
+#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
+ { NAME, sizeof(NAME) - 1, ID, IS_DEFAULT, DEFAULT_EXT },
#include "llvm/Support/ARMTargetParser.def"
};
// Information by ID
// ======================================================= //
-const char *llvm::ARM::getFPUName(unsigned FPUKind) {
+StringRef llvm::ARM::getFPUName(unsigned FPUKind) {
if (FPUKind >= ARM::FK_LAST)
- return nullptr;
- return FPUNames[FPUKind].Name;
+ return StringRef();
+ return FPUNames[FPUKind].getName();
}
unsigned llvm::ARM::getFPUVersion(unsigned FPUKind) {
return FPUNames[FPUKind].Restriction;
}
-unsigned llvm::ARM::getDefaultFPU(StringRef CPU) {
- for (const auto C : CPUNames) {
- if (CPU == C.Name)
- return C.DefaultFPU;
- }
- return ARM::FK_INVALID;
+unsigned llvm::ARM::getDefaultFPU(StringRef CPU, unsigned ArchKind) {
+ if (CPU == "generic")
+ return ARCHNames[ArchKind].DefaultFPU;
+
+ return StringSwitch<unsigned>(CPU)
+#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
+ .Case(NAME, DEFAULT_FPU)
+#include "llvm/Support/ARMTargetParser.def"
+ .Default(ARM::FK_INVALID);
+}
+
+unsigned llvm::ARM::getDefaultExtensions(StringRef CPU, unsigned ArchKind) {
+ if (CPU == "generic")
+ return ARCHNames[ArchKind].ArchBaseExtensions;
+
+ return StringSwitch<unsigned>(CPU)
+#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
+ .Case(NAME, ARCHNames[ID].ArchBaseExtensions | DEFAULT_EXT)
+#include "llvm/Support/ARMTargetParser.def"
+ .Default(ARM::AEK_INVALID);
}
bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
return true;
}
+bool llvm::ARM::getExtensionFeatures(unsigned Extensions,
+ std::vector<const char *> &Features) {
+
+ if (Extensions == ARM::AEK_INVALID)
+ return false;
+
+ if (Extensions & ARM::AEK_CRC)
+ Features.push_back("+crc");
+ else
+ Features.push_back("-crc");
+
+ if (Extensions & ARM::AEK_DSP)
+ Features.push_back("+dsp");
+ else
+ Features.push_back("-dsp");
+
+ return getHWDivFeatures(Extensions, Features);
+}
+
bool llvm::ARM::getFPUFeatures(unsigned FPUKind,
std::vector<const char *> &Features) {
// crypto includes neon, so we handle this similarly to FPU version.
switch (FPUNames[FPUKind].NeonSupport) {
case ARM::NS_Crypto:
+ Features.push_back("+neon");
Features.push_back("+crypto");
break;
case ARM::NS_Neon:
return true;
}
-const char *llvm::ARM::getArchName(unsigned ArchKind) {
+StringRef llvm::ARM::getArchName(unsigned ArchKind) {
if (ArchKind >= ARM::AK_LAST)
- return nullptr;
- return ARCHNames[ArchKind].Name;
+ return StringRef();
+ return ARCHNames[ArchKind].getName();
}
-const char *llvm::ARM::getCPUAttr(unsigned ArchKind) {
+StringRef llvm::ARM::getCPUAttr(unsigned ArchKind) {
if (ArchKind >= ARM::AK_LAST)
- return nullptr;
- return ARCHNames[ArchKind].CPUAttr;
+ return StringRef();
+ return ARCHNames[ArchKind].getCPUAttr();
}
-const char *llvm::ARM::getSubArch(unsigned ArchKind) {
+StringRef llvm::ARM::getSubArch(unsigned ArchKind) {
if (ArchKind >= ARM::AK_LAST)
- return nullptr;
- return ARCHNames[ArchKind].SubArch;
+ return StringRef();
+ return ARCHNames[ArchKind].getSubArch();
}
unsigned llvm::ARM::getArchAttr(unsigned ArchKind) {
return ARCHNames[ArchKind].ArchAttr;
}
-const char *llvm::ARM::getArchExtName(unsigned ArchExtKind) {
+StringRef llvm::ARM::getArchExtName(unsigned ArchExtKind) {
for (const auto AE : ARCHExtNames) {
if (ArchExtKind == AE.ID)
- return AE.Name;
+ return AE.getName();
}
+ return StringRef();
+}
+
+const char *llvm::ARM::getArchExtFeature(StringRef ArchExt) {
+ if (ArchExt.startswith("no")) {
+ StringRef ArchExtBase(ArchExt.substr(2));
+ for (const auto AE : ARCHExtNames) {
+ if (AE.NegFeature && ArchExtBase == AE.getName())
+ return AE.NegFeature;
+ }
+ }
+ for (const auto AE : ARCHExtNames) {
+ if (AE.Feature && ArchExt == AE.getName())
+ return AE.Feature;
+ }
+
return nullptr;
}
-const char *llvm::ARM::getHWDivName(unsigned HWDivKind) {
+StringRef llvm::ARM::getHWDivName(unsigned HWDivKind) {
for (const auto D : HWDivNames) {
if (HWDivKind == D.ID)
- return D.Name;
+ return D.getName();
}
- return nullptr;
+ return StringRef();
}
-const char *llvm::ARM::getDefaultCPU(StringRef Arch) {
+StringRef llvm::ARM::getDefaultCPU(StringRef Arch) {
unsigned AK = parseArch(Arch);
if (AK == ARM::AK_INVALID)
- return nullptr;
+ return StringRef();
// Look for multiple AKs to find the default for pair AK+Name.
for (const auto CPU : CPUNames) {
if (CPU.ArchID == AK && CPU.Default)
- return CPU.Name;
+ return CPU.getName();
}
- return nullptr;
+
+ // If we can't find a default then target the architecture instead
+ return "generic";
}
// ======================================================= //
static StringRef getArchSynonym(StringRef Arch) {
return StringSwitch<StringRef>(Arch)
- .Case("v6sm", "v6s-m")
- .Case("v6m", "v6-m")
- .Case("v7a", "v7-a")
+ .Case("v5", "v5t")
+ .Case("v5e", "v5te")
+ .Case("v6j", "v6")
+ .Case("v6hl", "v6k")
+ .Cases("v6m", "v6sm", "v6s-m", "v6-m")
+ .Cases("v6z", "v6zk", "v6kz")
+ .Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
.Case("v7r", "v7-r")
.Case("v7m", "v7-m")
.Case("v7em", "v7e-m")
.Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
.Case("v8.1a", "v8.1-a")
+ .Case("v8.2a", "v8.2-a")
.Default(Arch);
}
unsigned llvm::ARM::parseHWDiv(StringRef HWDiv) {
StringRef Syn = getHWDivSynonym(HWDiv);
for (const auto D : HWDivNames) {
- if (Syn == D.Name)
+ if (Syn == D.getName())
return D.ID;
}
return ARM::AEK_INVALID;
unsigned llvm::ARM::parseFPU(StringRef FPU) {
StringRef Syn = getFPUSynonym(FPU);
for (const auto F : FPUNames) {
- if (Syn == F.Name)
+ if (Syn == F.getName())
return F.ID;
}
return ARM::FK_INVALID;
Arch = getCanonicalArchName(Arch);
StringRef Syn = getArchSynonym(Arch);
for (const auto A : ARCHNames) {
- if (StringRef(A.Name).endswith(Syn))
+ if (A.getName().endswith(Syn))
return A.ID;
}
return ARM::AK_INVALID;
unsigned llvm::ARM::parseArchExt(StringRef ArchExt) {
for (const auto A : ARCHExtNames) {
- if (ArchExt == A.Name)
+ if (ArchExt == A.getName())
return A.ID;
}
return ARM::AEK_INVALID;
unsigned llvm::ARM::parseCPUArch(StringRef CPU) {
for (const auto C : CPUNames) {
- if (CPU == C.Name)
+ if (CPU == C.getName())
return C.ArchID;
}
return ARM::AK_INVALID;
switch (parseArch(Arch)) {
case ARM::AK_ARMV6M:
case ARM::AK_ARMV7M:
- case ARM::AK_ARMV6SM:
case ARM::AK_ARMV7EM:
return ARM::PK_M;
case ARM::AK_ARMV7R:
return ARM::PK_R;
- case ARM::AK_ARMV7:
case ARM::AK_ARMV7A:
- case ARM::AK_ARMV7L:
+ case ARM::AK_ARMV7K:
case ARM::AK_ARMV8A:
case ARM::AK_ARMV8_1A:
+ case ARM::AK_ARMV8_2A:
return ARM::PK_A;
}
return ARM::PK_INVALID;
case ARM::AK_ARMV4:
case ARM::AK_ARMV4T:
return 4;
- case ARM::AK_ARMV5:
case ARM::AK_ARMV5T:
case ARM::AK_ARMV5TE:
case ARM::AK_IWMMXT:
case ARM::AK_IWMMXT2:
case ARM::AK_XSCALE:
- case ARM::AK_ARMV5E:
case ARM::AK_ARMV5TEJ:
return 5;
case ARM::AK_ARMV6:
- case ARM::AK_ARMV6J:
case ARM::AK_ARMV6K:
case ARM::AK_ARMV6T2:
- case ARM::AK_ARMV6Z:
- case ARM::AK_ARMV6ZK:
+ case ARM::AK_ARMV6KZ:
case ARM::AK_ARMV6M:
- case ARM::AK_ARMV6SM:
- case ARM::AK_ARMV6HL:
return 6;
- case ARM::AK_ARMV7:
case ARM::AK_ARMV7A:
case ARM::AK_ARMV7R:
case ARM::AK_ARMV7M:
- case ARM::AK_ARMV7L:
- case ARM::AK_ARMV7HL:
case ARM::AK_ARMV7S:
case ARM::AK_ARMV7EM:
case ARM::AK_ARMV7K:
return 7;
case ARM::AK_ARMV8A:
case ARM::AK_ARMV8_1A:
+ case ARM::AK_ARMV8_2A:
return 8;
}
return 0;
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