[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error...

[oota-llvm.git] / lib / Makefile

diff --git a/lib/Makefile b/lib/Makefile
index 26f98caf3bd7fbaa1804203da1eff96b04b3ea6d..cfe992668de114010658640acd01201655e6c662 100644 (file)
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -1,15 +1,18 @@
 ##===- lib/Makefile ----------------------------------------*- Makefile -*-===##
-# 
+#
 #                     The LLVM Compiler Infrastructure
 #
-# This file was developed by the LLVM research group and is distributed under
-# the University of Illinois Open Source License. See LICENSE.TXT for details.
-# 
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
 ##===----------------------------------------------------------------------===##
 LEVEL = ..
 
-PARALLEL_DIRS = VMCore AsmParser Bytecode Bitcode Analysis Transforms CodeGen \
-                Target ExecutionEngine Debugger Linker 
+include $(LEVEL)/Makefile.config
+
+PARALLEL_DIRS := IR AsmParser Bitcode Analysis Transforms CodeGen \
+                 Target ExecutionEngine Linker LTO MC Object Option DebugInfo \
+                                                                IRReader
 
 include $(LEVEL)/Makefile.common