using namespace llvm;
-MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
-
-/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
-/// with feature string). Recompute feature bits and scheduling model.
-void
-MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
+static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
+ ArrayRef<SubtargetFeatureKV> ProcDesc,
+ ArrayRef<SubtargetFeatureKV> ProcFeatures) {
SubtargetFeatures Features(FS);
- FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
- ProcFeatures, NumFeatures);
-
- InitCPUSchedModel(CPU);
+ return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
}
-void
-MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
+void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
+ FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
if (!CPU.empty())
- CPUSchedModel = getSchedModelForCPU(CPU);
+ CPUSchedModel = &getSchedModelForCPU(CPU);
else
- CPUSchedModel = &MCSchedModel::DefaultSchedModel;
+ CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
}
-void
-MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
- const SubtargetFeatureKV *PF,
- const SubtargetFeatureKV *PD,
- const SubtargetInfoKV *ProcSched,
- const MCWriteProcResEntry *WPR,
- const MCWriteLatencyEntry *WL,
- const MCReadAdvanceEntry *RA,
- const InstrStage *IS,
- const unsigned *OC,
- const unsigned *FP,
- unsigned NF, unsigned NP) {
- TargetTriple = TT;
- ProcFeatures = PF;
- ProcDesc = PD;
- ProcSchedModels = ProcSched;
- WriteProcResTable = WPR;
- WriteLatencyTable = WL;
- ReadAdvanceTable = RA;
-
- Stages = IS;
- OperandCycles = OC;
- ForwardingPaths = FP;
- NumFeatures = NF;
- NumProcs = NP;
+void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
+ FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
+}
+MCSubtargetInfo::MCSubtargetInfo(
+ const Triple &TT, StringRef C, StringRef FS,
+ ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
+ const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
+ const InstrStage *IS, const unsigned *OC, const unsigned *FP)
+ : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
+ ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
+ ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
InitMCProcessorInfo(CPU, FS);
}
/// ToggleFeature - Toggle a feature and returns the re-computed feature
/// bits. This version does not change the implied bits.
-uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
+FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
+ FeatureBits.flip(FB);
+ return FeatureBits;
+}
+
+FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
FeatureBits ^= FB;
return FeatureBits;
}
/// ToggleFeature - Toggle a feature and returns the re-computed feature
/// bits. This version will also change all implied bits.
-uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
- SubtargetFeatures Features;
- FeatureBits = Features.ToggleFeature(FeatureBits, FS,
- ProcFeatures, NumFeatures);
+FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
+ SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
return FeatureBits;
}
+FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
+ SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
+ return FeatureBits;
+}
-const MCSchedModel *
-MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
+const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
assert(ProcSchedModels && "Processor machine model not available!");
-#ifndef NDEBUG
- for (size_t i = 1; i < NumProcs; i++) {
- assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
- "Processor machine model table is not sorted");
- }
-#endif
+ ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
- // Find entry
- const SubtargetInfoKV *Found = SubtargetFeatures::Find(CPU, ProcSchedModels,
- NumProcs, "processor");
- if (!Found)
- return &MCSchedModel::DefaultSchedModel;
+ assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
+ [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
+ return strcmp(LHS.Key, RHS.Key) < 0;
+ }) &&
+ "Processor machine model table is not sorted");
+ // Find entry
+ auto Found =
+ std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
+ if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
+ if (CPU != "help") // Don't error if the user asked for help.
+ errs() << "'" << CPU
+ << "' is not a recognized processor for this target"
+ << " (ignoring processor)\n";
+ return MCSchedModel::GetDefaultSchedModel();
+ }
assert(Found->Value && "Missing processor SchedModel value");
- return (const MCSchedModel *)Found->Value;
+ return *(const MCSchedModel *)Found->Value;
}
InstrItineraryData
MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
- const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
+ const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
}
/// Initialize an InstrItineraryData instance.
void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
- InstrItins =
- InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
+ InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
+ ForwardingPaths);
}