}
EmitCommentsAndEOL();
}
+
+ void EmitSyntaxDirective() override;
+
void EmitCommentsAndEOL();
/// isVerboseAsm - Return true if this streamer supports verbose assembly at
void MCAsmStreamer::AddComment(const Twine &T) {
if (!IsVerboseAsm) return;
- // Make sure that CommentStream is flushed.
- CommentStream.flush();
-
T.toVector(CommentToEmit);
// Each comment goes on its own line.
CommentToEmit.push_back('\n');
-
- // Tell the comment stream that the vector changed underneath it.
- CommentStream.resync();
}
void MCAsmStreamer::EmitCommentsAndEOL() {
return;
}
- CommentStream.flush();
StringRef Comments = CommentToEmit;
assert(Comments.back() == '\n' &&
} while (!Comments.empty());
CommentToEmit.clear();
- // Tell the comment stream that the vector changed underneath it.
- CommentStream.resync();
}
static inline int64_t truncateToSize(int64_t Value, unsigned Bytes) {
EmitEOL();
}
+void MCAsmStreamer::EmitSyntaxDirective() {
+ if (MAI->getAssemblerDialect() == 1)
+ OS << "\t.intel_syntax noprefix\n";
+ // FIXME: Currently emit unprefix'ed registers.
+ // The intel_syntax directive has one optional argument
+ // with may have a value of prefix or noprefix.
+}
+
void MCAsmStreamer::BeginCOFFSymbolDef(const MCSymbol *Symbol) {
OS << "\t.def\t ";
Symbol->print(OS, MAI);
}
void MCAsmStreamer::EmitCOFFSafeSEH(MCSymbol const *Symbol) {
- OS << "\t.safeseh\t" << *Symbol;
+ OS << "\t.safeseh\t";
+ Symbol->print(OS, MAI);
EmitEOL();
}
SmallVector<MCFixup, 4> Fixups;
raw_svector_ostream VecOS(Code);
Emitter->encodeInstruction(Inst, VecOS, Fixups, STI);
- VecOS.flush();
// If we are showing fixups, create symbolic markers in the encoded
// representation. We do this by making a per-bit map to the fixup item index,