//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
: TII(*mf.getTarget().getInstrInfo()), MF(mf),
Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
- ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1) {
+ Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1) {
grow();
}
void VirtRegMap::grow() {
- unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
+ unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg();
Virt2PhysMap.grow(LastVirtReg);
Virt2StackSlotMap.grow(LastVirtReg);
Virt2ReMatIdMap.grow(LastVirtReg);
Virt2SplitMap.grow(LastVirtReg);
+ Virt2SplitKillMap.grow(LastVirtReg);
ReMatMap.grow(LastVirtReg);
}
int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign stack slot to already spilled register");
- const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
+ const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
RC->getAlignment());
Virt2StackSlotMap[virtReg] = frameIndex;
}
void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign stack slot to already spilled register");
assert((frameIndex >= 0 ||
}
int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign re-mat id to already spilled register");
Virt2ReMatIdMap[virtReg] = ReMatId;
}
void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
- assert(MRegisterInfo::isVirtualRegister(virtReg));
+ assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
"attempt to assign re-mat id to already spilled register");
Virt2ReMatIdMap[virtReg] = id;
}
void VirtRegMap::print(std::ostream &OS) const {
- const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
+ const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo();
OS << "********** REGISTER MAP **********\n";
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
- e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
+ for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
+ e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
- OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
+ OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n";
}
- for (unsigned i = MRegisterInfo::FirstVirtualRegister,
- e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
+ for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
+ e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
OS << '\n';
DOUT << "********** REWRITE MACHINE CODE **********\n";
DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
+
// LoadedRegs - Keep track of which vregs are loaded, so that we only load
// each vreg once (in the case where a spilled vreg is used by multiple
MachineInstr &MI = *MII;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
- if (MO.isRegister() && MO.getReg())
- if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ if (MO.isRegister() && MO.getReg()) {
+ if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned VirtReg = MO.getReg();
unsigned PhysReg = VRM.getPhys(VirtReg);
if (!VRM.isAssignedReg(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg);
const TargetRegisterClass* RC =
- MF.getSSARegMap()->getRegClass(VirtReg);
+ MF.getRegInfo().getRegClass(VirtReg);
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
- MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
+ TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DOUT << '\t' << *prior(MII);
}
if (MO.isDef()) {
- MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
+ TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
+ StackSlot, RC);
++NumStores;
}
}
- MF.setPhysRegUsed(PhysReg);
+ MF.getRegInfo().setPhysRegUsed(PhysReg);
MI.getOperand(i).setReg(PhysReg);
} else {
- MF.setPhysRegUsed(MO.getReg());
+ MF.getRegInfo().setPhysRegUsed(MO.getReg());
}
+ }
}
DOUT << '\t' << MI;
/// blocks that have low register pressure (the vreg may be spilled due to
/// register pressure in other blocks).
class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
- SSARegMap *RegMap;
- const MRegisterInfo *MRI;
+ MachineRegisterInfo *RegInfo;
+ const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
public:
bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
- RegMap = MF.getSSARegMap();
- MRI = MF.getTarget().getRegisterInfo();
+ RegInfo = &MF.getRegInfo();
+ TRI = MF.getTarget().getRegisterInfo();
TII = MF.getTarget().getInstrInfo();
DOUT << "\n**** Local spiller rewriting function '"
<< MF.getFunction()->getName() << "':\n";
- DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n";
+ DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
+ " ****\n";
DEBUG(MF.dump());
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
MachineBasicBlock::iterator &MII,
int Idx, unsigned PhysReg, int StackSlot,
const TargetRegisterClass *RC,
- MachineInstr *&LastStore,
+ bool isAvailable, MachineInstr *&LastStore,
AvailableSpills &Spills,
SmallSet<MachineInstr*, 4> &ReMatDefs,
BitVector &RegKills,
std::vector<MachineOperand*> &KillOps,
- VirtRegMap &VRM, bool StoreMaybeDead);
+ VirtRegMap &VRM);
void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
};
}
/// this bit and addAvailable sets it if.
namespace {
class VISIBILITY_HIDDEN AvailableSpills {
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
// SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
void ClobberPhysRegOnly(unsigned PhysReg);
public:
- AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
- : MRI(mri), TII(tii) {
+ AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
+ : TRI(tri), TII(tii) {
}
- const MRegisterInfo *getRegInfo() const { return MRI; }
+ const TargetRegisterInfo *getRegInfo() const { return TRI; }
/// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
/// available in a physical register, return that PhysReg, otherwise
DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
else
DOUT << "Remembering SS#" << SlotOrReMat;
- DOUT << " in physreg " << MRI->getName(Reg) << "\n";
+ DOUT << " in physreg " << TRI->getName(Reg) << "\n";
}
/// canClobberPhysReg - Return true if the spiller is allowed to change the
"Value not available!");
return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
}
-
+
/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
/// stackslot register. The register is still available but is no longer
/// allowed to be modifed.
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
"Bidirectional map mismatch!");
SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
- DOUT << "PhysReg " << MRI->getName(PhysReg)
+ DOUT << "PhysReg " << TRI->getName(PhysReg)
<< " copied, it is available for use but can no longer be modified\n";
}
}
/// stackslot register and its aliases. The register and its aliases may
/// still available but is no longer allowed to be modifed.
void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
- for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
+ for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
disallowClobberPhysRegOnly(*AS);
disallowClobberPhysRegOnly(PhysReg);
}
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
"Bidirectional map mismatch!");
SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
- DOUT << "PhysReg " << MRI->getName(PhysReg)
+ DOUT << "PhysReg " << TRI->getName(PhysReg)
<< " clobbered, invalidating ";
if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
/// value. We use this to invalidate any info about stuff we thing lives in
/// it and any of its aliases.
void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
- for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
+ for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
ClobberPhysRegOnly(*AS);
ClobberPhysRegOnly(PhysReg);
}
}
}
+/// InvalidateKill - A MI that defines the specified register is being deleted,
+/// invalidate the register kill information.
+static void InvalidateKill(unsigned Reg, BitVector &RegKills,
+ std::vector<MachineOperand*> &KillOps) {
+ if (RegKills[Reg]) {
+ KillOps[Reg]->setIsKill(false);
+ KillOps[Reg] = NULL;
+ RegKills.reset(Reg);
+ }
+}
+
/// InvalidateRegDef - If the def operand of the specified def MI is now dead
/// (since it's spill instruction is removed), mark it isDead. Also checks if
/// the def MI has other definition operands that are not dead. Returns it by
/// over.
static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
std::vector<MachineOperand*> &KillOps) {
- const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
+ const TargetInstrDesc &TID = MI.getDesc();
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isRegister() || !MO.isUse())
if (RegKills[Reg]) {
// That can't be right. Register is killed but not re-defined and it's
// being reused. Let's fix that.
- KillOps[Reg]->unsetIsKill();
- if (i < TID->numOperands &&
- TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
+ KillOps[Reg]->setIsKill(false);
+ KillOps[Reg] = NULL;
+ RegKills.reset(Reg);
+ if (i < TID.getNumOperands() &&
+ TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
// Unless it's a two-address operand, this is the new kill.
MO.setIsKill();
}
-
if (MO.isKill()) {
RegKills.set(Reg);
KillOps[Reg] = &MO;
}
}
+/// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
+///
+static void ReMaterialize(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator &MII,
+ unsigned DestReg, unsigned Reg,
+ const TargetRegisterInfo *TRI,
+ VirtRegMap &VRM) {
+ TRI->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
+ MachineInstr *NewMI = prior(MII);
+ for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = NewMI->getOperand(i);
+ if (!MO.isRegister() || MO.getReg() == 0)
+ continue;
+ unsigned VirtReg = MO.getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
+ continue;
+ assert(MO.isUse());
+ unsigned SubIdx = MO.getSubReg();
+ unsigned Phys = VRM.getPhys(VirtReg);
+ assert(Phys);
+ unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
+ MO.setReg(RReg);
+ }
+ ++NumReMats;
+}
+
// ReusedOp - For each reused operand, we keep track of a bit of information, in
// case we need to rollback upon processing a new operand. See comments below.
std::vector<ReusedOp> Reuses;
BitVector PhysRegsClobbered;
public:
- ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
- PhysRegsClobbered.resize(mri->getNumRegs());
+ ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
+ PhysRegsClobbered.resize(tri->getNumRegs());
}
bool hasReuses() const {
BitVector &RegKills,
std::vector<MachineOperand*> &KillOps,
VirtRegMap &VRM) {
+ const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
+ .getInstrInfo();
+
if (Reuses.empty()) return PhysReg; // This is most often empty.
for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
// value aliases the new register. If so, codegen the previous reload
// and use this one.
unsigned PRRU = Op.PhysRegReused;
- const MRegisterInfo *MRI = Spills.getRegInfo();
- if (MRI->areAliases(PRRU, PhysReg)) {
+ const TargetRegisterInfo *TRI = Spills.getRegInfo();
+ if (TRI->areAliases(PRRU, PhysReg)) {
// Okay, we found out that an alias of a reused register
// was used. This isn't good because it means we have
// to undo a previous reuse.
MachineBasicBlock *MBB = MI->getParent();
const TargetRegisterClass *AliasRC =
- MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
+ MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
// Copy Op out of the vector and remove it, we're going to insert an
// explicit load for it.
MI, Spills, MaybeDeadStores,
Rejected, RegKills, KillOps, VRM);
+ MachineBasicBlock::iterator MII = MI;
if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
- MRI->reMaterialize(*MBB, MI, NewPhysReg,
- VRM.getReMaterializedMI(NewOp.VirtReg));
- ++NumReMats;
+ ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TRI, VRM);
} else {
- MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
+ TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg,
NewOp.StackSlotOrReMat, AliasRC);
// Any stores to this stack slot are not dead anymore.
MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
- MachineBasicBlock::iterator MII = MI;
--MII;
UpdateKills(*MII, RegKills, KillOps);
DOUT << '\t' << *MII;
/// xorl %edi, %eax
/// movl %eax, -32(%ebp)
/// movl -36(%ebp), %eax
-/// orl %eax, -32(%ebp)
+/// orl %eax, -32(%ebp)
/// ==>
/// xorl %edi, %eax
/// orl -36(%ebp), %eax
DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1)
continue;
UnfoldPR = PhysReg;
- UnfoldedOpc = MRI->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
+ UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
false, true);
}
}
if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
continue;
unsigned VirtReg = MO.getReg();
- if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
+ if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
continue;
if (VRM.isAssignedReg(VirtReg)) {
unsigned PhysReg = VRM.getPhys(VirtReg);
- if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR))
+ if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
return false;
} else if (VRM.isReMaterialized(VirtReg))
continue;
int SS = VRM.getStackSlot(VirtReg);
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
if (PhysReg) {
- if (MRI->regsOverlap(PhysReg, UnfoldPR))
+ if (TRI->regsOverlap(PhysReg, UnfoldPR))
return false;
continue;
}
PhysReg = VRM.getPhys(VirtReg);
- if (!MRI->regsOverlap(PhysReg, UnfoldPR))
+ if (!TRI->regsOverlap(PhysReg, UnfoldPR))
continue;
// Ok, we'll need to reload the value into a register which makes
// unfolded. This allows us to perform the store unfolding
// optimization.
SmallVector<MachineInstr*, 4> NewMIs;
- if (MRI->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
+ if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
assert(NewMIs.size() == 1);
MachineInstr *NewMI = NewMIs.back();
NewMIs.clear();
assert(Idx != -1);
SmallVector<unsigned, 2> Ops;
Ops.push_back(Idx);
- MachineInstr *FoldedMI = MRI->foldMemoryOperand(NewMI, Ops, SS);
+ MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
if (FoldedMI) {
if (!VRM.hasPhys(UnfoldVR))
VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
/// findSuperReg - Find the SubReg's super-register of given register class
/// where its SubIdx sub-register is SubReg.
static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
- unsigned SubIdx, const MRegisterInfo *MRI) {
+ unsigned SubIdx, const TargetRegisterInfo *TRI) {
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I) {
unsigned Reg = *I;
- if (MRI->getSubReg(Reg, SubIdx) == SubReg)
+ if (TRI->getSubReg(Reg, SubIdx) == SubReg)
return Reg;
}
return 0;
MachineBasicBlock::iterator &MII,
int Idx, unsigned PhysReg, int StackSlot,
const TargetRegisterClass *RC,
- MachineInstr *&LastStore,
+ bool isAvailable, MachineInstr *&LastStore,
AvailableSpills &Spills,
SmallSet<MachineInstr*, 4> &ReMatDefs,
BitVector &RegKills,
std::vector<MachineOperand*> &KillOps,
- VirtRegMap &VRM, bool StoreMaybeDead) {
- MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
+ VirtRegMap &VRM) {
+ TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
DOUT << "Store:\t" << *next(MII);
// If there is a dead store to this stack slot, nuke it now.
}
}
- MachineInstr *NewStore = next(MII);
- LastStore = StoreMaybeDead ? NewStore : NULL;
+ LastStore = next(MII);
// If the stack slot value was previously available in some other
// register, change it now. Otherwise, make the register available,
// in PhysReg.
Spills.ModifyStackSlotOrReMat(StackSlot);
Spills.ClobberPhysReg(PhysReg);
- Spills.addAvailable(StackSlot, NewStore, PhysReg);
+ Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable);
++NumStores;
}
DOUT << MBB.getBasicBlock()->getName() << ":\n";
MachineFunction &MF = *MBB.getParent();
-
+
// Spills - Keep track of which spilled values are available in physregs so
// that we can choose to reuse the physregs instead of emitting reloads.
- AvailableSpills Spills(MRI, TII);
+ AvailableSpills Spills(TRI, TII);
// MaybeDeadStores - When we need to write a value back into a stack slot,
// keep track of the inserted store. If the stack slot value is never read
SmallSet<MachineInstr*, 4> ReMatDefs;
// Keep track of kill information.
- BitVector RegKills(MRI->getNumRegs());
+ BitVector RegKills(TRI->getNumRegs());
std::vector<MachineOperand*> KillOps;
- KillOps.resize(MRI->getNumRegs(), NULL);
+ KillOps.resize(TRI->getNumRegs(), NULL);
for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
MII != E; ) {
NextMII = next(MII);
MachineInstr &MI = *MII;
- const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
+ const TargetInstrDesc &TID = MI.getDesc();
// Insert restores here if asked to.
if (VRM.isRestorePt(&MI)) {
std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
- unsigned VirtReg = RestoreRegs[i];
+ unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
if (!VRM.getPreSplitReg(VirtReg))
continue; // Split interval spilled again.
unsigned Phys = VRM.getPhys(VirtReg);
- MF.setPhysRegUsed(Phys);
+ RegInfo->setPhysRegUsed(Phys);
if (VRM.isReMaterialized(VirtReg)) {
- MRI->reMaterialize(MBB, &MI, Phys,
- VRM.getReMaterializedMI(VirtReg));
- ++NumReMats;
+ ReMaterialize(MBB, MII, Phys, VirtReg, TRI, VRM);
} else {
- const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
- MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), RC);
+ const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
+ TII->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
+ RC);
++NumLoads;
}
// This invalidates Phys.
// Insert spills here if asked to.
if (VRM.isSpillPt(&MI)) {
- std::vector<unsigned> &SpillRegs = VRM.getSpillPtSpills(&MI);
+ std::vector<std::pair<unsigned,bool> > &SpillRegs =
+ VRM.getSpillPtSpills(&MI);
for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
- unsigned VirtReg = SpillRegs[i];
+ unsigned VirtReg = SpillRegs[i].first;
+ bool isKill = SpillRegs[i].second;
if (!VRM.getPreSplitReg(VirtReg))
continue; // Split interval spilled again.
- const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
+ const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
unsigned Phys = VRM.getPhys(VirtReg);
int StackSlot = VRM.getStackSlot(VirtReg);
- MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
- SpillRegToStackSlot(MBB, MII, i, Phys, StackSlot, RC, LastStore,
- Spills, ReMatDefs, RegKills, KillOps, VRM, false);
+ TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
+ MachineInstr *StoreMI = next(MII);
+ DOUT << "Store:\t" << StoreMI;
+ VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
}
+ NextMII = next(MII);
}
/// ReusedOperands - Keep track of operand reuse in case we need to undo
/// reuse.
- ReuseInfo ReusedOperands(MI, MRI);
- // Process all of the spilled uses and all non spilled reg references.
+ ReuseInfo ReusedOperands(MI, TRI);
+ SmallVector<unsigned, 4> VirtUseOps;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isRegister() || MO.getReg() == 0)
continue; // Ignore non-register operands.
unsigned VirtReg = MO.getReg();
- if (MRegisterInfo::isPhysicalRegister(VirtReg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
// Ignore physregs for spilling, but remember that it is used by this
// function.
- MF.setPhysRegUsed(VirtReg);
+ RegInfo->setPhysRegUsed(VirtReg);
continue;
}
-
- assert(MRegisterInfo::isVirtualRegister(VirtReg) &&
- "Not a virtual or a physical register?");
- // Assumes this is the last use of a split interval. IsKill will be unset
- // if reg is use later unless it's a two-address operand.
- if (MO.isUse() && VRM.getPreSplitReg(VirtReg) &&
- TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
- MI.getOperand(i).setIsKill();
+ // We want to process implicit virtual register uses first.
+ if (MO.isImplicit())
+ VirtUseOps.insert(VirtUseOps.begin(), i);
+ else
+ VirtUseOps.push_back(i);
+ }
+
+ // Process all of the spilled uses and all non spilled reg references.
+ for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
+ unsigned i = VirtUseOps[j];
+ MachineOperand &MO = MI.getOperand(i);
+ unsigned VirtReg = MO.getReg();
+ assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
+ "Not a virtual register?");
unsigned SubIdx = MO.getSubReg();
if (VRM.isAssignedReg(VirtReg)) {
// This virtual register was assigned a physreg!
unsigned Phys = VRM.getPhys(VirtReg);
- MF.setPhysRegUsed(Phys);
+ RegInfo->setPhysRegUsed(Phys);
if (MO.isDef())
ReusedOperands.markClobbered(Phys);
- unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys;
+ unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
MI.getOperand(i).setReg(RReg);
continue;
}
// Check to see if this stack slot is available.
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
- if (!PhysReg && DoReMat) {
- // This use is rematerializable. But perhaps the value is available in
- // a register if the definition is not deleted. If so, check if we can
- // reuse the value.
- ReuseSlot = VRM.getStackSlot(VirtReg);
- if (ReuseSlot != VirtRegMap::NO_STACK_SLOT)
- PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot);
- }
// If this is a sub-register use, make sure the reuse register is in the
// right register class. For example, for x86 not all of the 32-bit
// the right register file.
if (PhysReg &&
(SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
- const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
+ const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
if (!RC->contains(PhysReg))
PhysReg = 0;
}
// aren't allowed to modify the reused register. If none of these cases
// apply, reuse it.
bool CanReuse = true;
- int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
+ int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
if (ti != -1 &&
MI.getOperand(ti).isRegister() &&
MI.getOperand(ti).getReg() == VirtReg) {
else
DOUT << "Reusing SS#" << ReuseSlot;
DOUT << " from physreg "
- << MRI->getName(PhysReg) << " for vreg"
+ << TRI->getName(PhysReg) << " for vreg"
<< VirtReg <<" instead of reloading into physreg "
- << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
// The only technical detail we have is that we don't know that
DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
else
DOUT << "Reusing SS#" << ReuseSlot;
- DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
+ DOUT << " from physreg " << TRI->getName(PhysReg) << " for vreg"
<< VirtReg
<< " instead of reloading into same physreg.\n";
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
ReusedOperands.markClobbered(RReg);
++NumReused;
continue;
}
- const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
- MF.setPhysRegUsed(DesignatedReg);
+ const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
+ RegInfo->setPhysRegUsed(DesignatedReg);
ReusedOperands.markClobbered(DesignatedReg);
- MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
+ TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
MachineInstr *CopyMI = prior(MII);
UpdateKills(*CopyMI, RegKills, KillOps);
Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
unsigned RReg =
- SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
+ SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
MI.getOperand(i).setReg(RReg);
DOUT << '\t' << *prior(MII);
++NumReused;
PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Spills, MaybeDeadStores, RegKills, KillOps, VRM);
- MF.setPhysRegUsed(PhysReg);
+ RegInfo->setPhysRegUsed(PhysReg);
ReusedOperands.markClobbered(PhysReg);
if (DoReMat) {
- MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
- ++NumReMats;
+ ReMaterialize(MBB, MII, PhysReg, VirtReg, TRI, VRM);
} else {
- const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
- MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
+ const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
+ TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
++NumLoads;
}
// This invalidates PhysReg.
Spills.addAvailable(SSorRMId, &MI, PhysReg);
// Assumes this is the last use. IsKill will be unset if reg is reused
// unless it's a two-address operand.
- if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
+ if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
MI.getOperand(i).setIsKill();
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
UpdateKills(*prior(MII), RegKills, KillOps);
DOUT << '\t' << *prior(MII);
if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
DOUT << "Promoted Load To Copy: " << MI;
if (DestReg != InReg) {
- const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
- MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
+ const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
+ TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
// Revisit the copy so we make sure to notice the effects of the
// operation on the destreg (either needing to RA it if it's
// virtual or needing to clobber any values if it's physical).
NextMII = &MI;
--NextMII; // backtrack to the copy.
BackTracked = true;
- } else
+ } else {
DOUT << "Removing now-noop copy: " << MI;
+ // Unset last kill since it's being reused.
+ InvalidateKill(InReg, RegKills, KillOps);
+ }
VRM.RemoveMachineInstrFromMaps(&MI);
MBB.erase(&MI);
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
SmallVector<MachineInstr*, 4> NewMIs;
if (PhysReg &&
- MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
+ TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
MBB.insert(MII, NewMIs[0]);
VRM.RemoveMachineInstrFromMaps(&MI);
MBB.erase(&MI);
if (MR & VirtRegMap::isModRef) {
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
SmallVector<MachineInstr*, 4> NewMIs;
+ // We can reuse this physreg as long as we are allowed to clobber
+ // the value and there isn't an earlier def that has already clobbered
+ // the physreg.
if (PhysReg &&
+ !TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
- MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
+ TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
MBB.insert(MII, NewMIs[0]);
NewStore = NewMIs[1];
MBB.insert(MII, NewStore);
int StackSlot;
if (!(MR & VirtRegMap::isRef)) {
if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
- assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Src hasn't been allocated yet?");
// Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
// this as a potentially dead store in case there is a subsequent
continue;
unsigned VirtReg = MO.getReg();
- if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
+ if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
// Check to see if this is a noop copy. If so, eliminate the
// instruction before considering the dest reg to be changed.
unsigned Src, Dst;
// The only vregs left are stack slot definitions.
int StackSlot = VRM.getStackSlot(VirtReg);
- const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
+ const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
// If this def is part of a two-address operand, make sure to execute
// the store from the correct physical register.
unsigned PhysReg;
- int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
+ int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
if (TiedOp != -1) {
PhysReg = MI.getOperand(TiedOp).getReg();
if (SubIdx) {
- unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI);
- assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
+ unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
+ assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
"Can't find corresponding super-register!");
PhysReg = SuperReg;
}
}
}
- MF.setPhysRegUsed(PhysReg);
- unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
+ RegInfo->setPhysRegUsed(PhysReg);
+ unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
ReusedOperands.markClobbered(RReg);
MI.getOperand(i).setReg(RReg);
if (!MO.isDead()) {
MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
- SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, LastStore,
- Spills, ReMatDefs, RegKills, KillOps, VRM, true);
+ SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
+ LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
+ NextMII = next(MII);
// Check to see if this is a noop copy. If so, eliminate the
// instruction before considering the dest reg to be changed.
}
}
ProcessNextInst:
- if (!Erased && !BackTracked)
+ if (!Erased && !BackTracked) {
for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
UpdateKills(*II, RegKills, KillOps);
+ }
MII = NextMII;
}
}
projects / oota-llvm.git / blobdiff