if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
&& !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
&& SchedModel.isComplete()) {
- std::string Err;
- raw_string_ostream ss(Err);
- ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
- << *DefMI;
- report_fatal_error(ss.str());
+ errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
+ << *DefMI;
+ llvm_unreachable("incomplete machine model");
}
#endif
// FIXME: Automatically giving all implicit defs defaultDefLatency is
unsigned SCIdx = TII->get(Opcode).getSchedClass();
const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx);
- unsigned Latency = 0;
if (SCDesc->isValid() && !SCDesc->isVariant())
return computeInstrLatency(*SCDesc);
- assert(Latency && "No MI sched latency");
- return 0;
+ llvm_unreachable("No MI sched latency");
}
unsigned