[MachineLICM] Fix handling of memoperands

[oota-llvm.git] / lib / CodeGen / TargetRegisterInfo.cpp

diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp
index 839d9ef31ad042c43c8a9c2443d8d904656b7b26..0a7042ac3db547c065ea40324b4e861c4a0b4a0d 100644 (file)
--- a/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/lib/CodeGen/TargetRegisterInfo.cpp
@@ -44,7 +44,7 @@ namespace llvm {
 
 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
                    unsigned SubIdx) {
-  return [Reg, TRI, SubIdx](raw_ostream &OS) {
+  return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
     if (!Reg)
       OS << "%noreg";
     else if (TargetRegisterInfo::isStackSlot(Reg))
@@ -61,11 +61,11 @@ Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
       else
         OS << ":sub(" << SubIdx << ')';
     }
-  };
+  });
 }
 
 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
-  return [Unit, TRI](raw_ostream &OS) {
+  return Printable([Unit, TRI](raw_ostream &OS) {
     // Generic printout when TRI is missing.
     if (!TRI) {
       OS << "Unit~" << Unit;
@@ -84,23 +84,23 @@ Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
     OS << TRI->getName(*Roots);
     for (++Roots; Roots.isValid(); ++Roots)
       OS << '~' << TRI->getName(*Roots);
-  };
+  });
 }
 
 Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
-  return [Unit, TRI](raw_ostream &OS) {
+  return Printable([Unit, TRI](raw_ostream &OS) {
     if (TRI && TRI->isVirtualRegister(Unit)) {
       OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
     } else {
       OS << PrintRegUnit(Unit, TRI);
     }
-  };
+  });
 }
 
 Printable PrintLaneMask(LaneBitmask LaneMask) {
-  return [LaneMask](raw_ostream &OS) {
+  return Printable([LaneMask](raw_ostream &OS) {
     OS << format("%08X", LaneMask);
-  };
+  });
 }
 
 } // End of llvm namespace