#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include <vector>
cl::desc("Suppress slot sharing during stack coloring"));
static cl::opt<bool>
-ColorWithRegs("color-ss-with-regs",
- cl::init(false), cl::Hidden,
- cl::desc("Color stack slots with free registers"));
+ColorWithRegsOpt("color-ss-with-regs",
+ cl::init(false), cl::Hidden,
+ cl::desc("Color stack slots with free registers"));
static cl::opt<int> DCELimit("ssc-dce-limit", cl::init(-1), cl::Hidden);
STATISTIC(NumEliminated, "Number of stack slots eliminated due to coloring");
STATISTIC(NumRegRepl, "Number of stack slot refs replaced with reg refs");
-STATISTIC(NumLoadElim, "Number of load eliminated");
+STATISTIC(NumLoadElim, "Number of loads eliminated");
STATISTIC(NumStoreElim, "Number of stores eliminated");
STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
namespace {
class VISIBILITY_HIDDEN StackSlotColoring : public MachineFunctionPass {
+ bool ColorWithRegs;
LiveStacks* LS;
VirtRegMap* VRM;
MachineFrameInfo *MFI;
public:
static char ID; // Pass identification
- StackSlotColoring() : MachineFunctionPass(&ID), NextColor(-1) {}
+ StackSlotColoring() :
+ MachineFunctionPass(&ID), ColorWithRegs(false), NextColor(-1) {}
+ StackSlotColoring(bool RegColor) :
+ MachineFunctionPass(&ID), ColorWithRegs(RegColor), NextColor(-1) {}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LiveStacks>();
unsigned OldReg, unsigned NewReg);
void UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
unsigned Reg, const TargetRegisterClass *RC,
+ SmallSet<unsigned, 4> &Defs,
MachineFunction &MF);
bool AllMemRefsCanBeUnfolded(int SS);
bool RemoveDeadStores(MachineBasicBlock* MBB);
static RegisterPass<StackSlotColoring>
X("stack-slot-coloring", "Stack Slot Coloring");
-FunctionPass *llvm::createStackSlotColoringPass() {
- return new StackSlotColoring();
+FunctionPass *llvm::createStackSlotColoringPass(bool RegColor) {
+ return new StackSlotColoring(RegColor);
}
namespace {
StackSlotColoring::ColorSlotsWithFreeRegs(SmallVector<int, 16> &SlotMapping,
SmallVector<SmallVector<int, 4>, 16> &RevMap,
BitVector &SlotIsReg) {
- if (!ColorWithRegs || !VRM->HasUnusedRegisters())
+ if (!(ColorWithRegs || ColorWithRegsOpt) || !VRM->HasUnusedRegisters())
return false;
bool Changed = false;
for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
LiveInterval *li = SSIntervals[i];
int SS = li->getStackSlotIndex();
- if (!UsedColors[SS])
+ if (!UsedColors[SS] || li->weight < 20)
+ // If the weight is < 20, i.e. two references in a loop with depth 1,
+ // don't bother with it.
continue;
// These slots allow to share the same registers.
return false;
// Rewrite all MO_FrameIndex operands.
+ SmallVector<SmallSet<unsigned, 4>, 4> NewDefs(MF.getNumBlockIDs());
for (unsigned SS = 0, SE = SSRefs.size(); SS != SE; ++SS) {
bool isReg = SlotIsReg[SS];
int NewFI = SlotMapping[SS];
if (NewFI == -1 || (NewFI == (int)SS && !isReg))
continue;
+ const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
for (unsigned i = 0, e = RefMIs.size(); i != e; ++i)
if (!isReg)
RewriteInstruction(RefMIs[i], SS, NewFI, MF);
else {
// Rewrite to use a register instead.
- const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
- UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, MF);
+ unsigned MBBId = RefMIs[i]->getParent()->getNumber();
+ SmallSet<unsigned, 4> &Defs = NewDefs[MBBId];
+ UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
}
}
bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
MachineBasicBlock *MBB,
unsigned OldReg, unsigned NewReg) {
+ if (MII == MBB->begin())
+ return false;
+
+ SmallVector<MachineOperand*, 4> Uses;
SmallVector<MachineOperand*, 4> Refs;
while (--MII != MBB->begin()) {
bool FoundDef = false; // Not counting 2address def.
- bool FoundUse = false;
- bool FoundKill = false;
+
+ Uses.clear();
+ const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MII->getOperand(i);
if (!MO.isReg())
if (Reg == 0)
continue;
if (Reg == OldReg) {
+ if (MO.isImplicit())
+ return false;
+ const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
+ if (RC && !RC->contains(NewReg))
+ return false;
+
if (MO.isUse()) {
- FoundUse = true;
- if (MO.isKill())
- FoundKill = true;
- Refs.push_back(&MO);
+ Uses.push_back(&MO);
} else {
Refs.push_back(&MO);
if (!MII->isRegTiedToUseOperand(i))
return false;
}
}
+
if (FoundDef) {
+ // Found non-two-address def. Stop here.
for (unsigned i = 0, e = Refs.size(); i != e; ++i)
Refs[i]->setReg(NewReg);
return true;
}
+
+ // Two-address uses must be updated as well.
+ for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+ Refs.push_back(Uses[i]);
}
return false;
}
bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
MachineBasicBlock *MBB,
unsigned OldReg, unsigned NewReg) {
+ if (MII == MBB->end())
+ return false;
+
SmallVector<MachineOperand*, 4> Uses;
while (++MII != MBB->end()) {
bool FoundUse = false;
bool FoundKill = false;
+ const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MII->getOperand(i);
if (!MO.isReg())
if (Reg == 0)
continue;
if (Reg == OldReg) {
- if (MO.isDef())
+ if (MO.isDef() || MO.isImplicit())
+ return false;
+
+ const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
+ if (RC && !RC->contains(NewReg))
return false;
FoundUse = true;
if (MO.isKill())
/// UnfoldAndRewriteInstruction - Rewrite specified instruction by unfolding
/// folded memory references and replacing those references with register
/// references instead.
-void StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
- unsigned Reg,
- const TargetRegisterClass *RC,
- MachineFunction &MF) {
+void
+StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
+ unsigned Reg,
+ const TargetRegisterClass *RC,
+ SmallSet<unsigned, 4> &Defs,
+ MachineFunction &MF) {
MachineBasicBlock *MBB = MI->getParent();
if (unsigned DstReg = TII->isLoadFromStackSlot(MI, OldFI)) {
if (PropagateForward(MI, MBB, DstReg, Reg)) {
+ DOUT << "Eliminated load: ";
+ DEBUG(MI->dump());
++NumLoadElim;
} else {
TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC);
++NumRegRepl;
}
+
+ if (!Defs.count(Reg)) {
+ // If this is the first use of Reg in this MBB and it wasn't previously
+ // defined in MBB, add it to livein.
+ MBB->addLiveIn(Reg);
+ Defs.insert(Reg);
+ }
} else if (unsigned SrcReg = TII->isStoreToStackSlot(MI, OldFI)) {
if (MI->killsRegister(SrcReg) && PropagateBackward(MI, MBB, SrcReg, Reg)) {
+ DOUT << "Eliminated store: ";
+ DEBUG(MI->dump());
++NumStoreElim;
} else {
TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC);
++NumRegRepl;
}
+
+ // Remember reg has been defined in MBB.
+ Defs.insert(Reg);
} else {
SmallVector<MachineInstr*, 4> NewMIs;
bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, false, false, NewMIs);
+ Success = Success; // Silence compiler warning.
assert(Success && "Failed to unfold!");
- MBB->insert(MI, NewMIs[0]);
+ MachineInstr *NewMI = NewMIs[0];
+ MBB->insert(MI, NewMI);
++NumRegRepl;
+
+ if (NewMI->readsRegister(Reg)) {
+ if (!Defs.count(Reg))
+ // If this is the first use of Reg in this MBB and it wasn't previously
+ // defined in MBB, add it to livein.
+ MBB->addLiveIn(Reg);
+ Defs.insert(Reg);
+ }
}
MBB->erase(MI);
}
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