#define DEBUG_TYPE "stackcoloring"
#include "VirtRegMap.h"
+#include "llvm/Function.h"
+#include "llvm/Module.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include <vector>
STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
namespace {
- class VISIBILITY_HIDDEN StackSlotColoring : public MachineFunctionPass {
+ class StackSlotColoring : public MachineFunctionPass {
bool ColorWithRegs;
LiveStacks* LS;
VirtRegMap* VRM;
public:
static char ID; // Pass identification
StackSlotColoring() :
- MachineFunctionPass(&ID), ColorWithRegs(false), NextColor(-1) {}
+ MachineFunctionPass(ID), ColorWithRegs(false), NextColor(-1) {
+ initializeStackSlotColoringPass(*PassRegistry::getPassRegistry());
+ }
StackSlotColoring(bool RegColor) :
- MachineFunctionPass(&ID), ColorWithRegs(RegColor), NextColor(-1) {}
+ MachineFunctionPass(ID), ColorWithRegs(RegColor), NextColor(-1) {
+ initializeStackSlotColoringPass(*PassRegistry::getPassRegistry());
+ }
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesCFG();
+ AU.addRequired<SlotIndexes>();
+ AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveStacks>();
AU.addRequired<VirtRegMap>();
AU.addPreserved<VirtRegMap>();
unsigned OldReg, unsigned NewReg);
void UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
unsigned Reg, const TargetRegisterClass *RC,
+ SmallSet<unsigned, 4> &Defs,
MachineFunction &MF);
bool AllMemRefsCanBeUnfolded(int SS);
bool RemoveDeadStores(MachineBasicBlock* MBB);
char StackSlotColoring::ID = 0;
-static RegisterPass<StackSlotColoring>
-X("stack-slot-coloring", "Stack Slot Coloring");
+INITIALIZE_PASS_BEGIN(StackSlotColoring, "stack-slot-coloring",
+ "Stack Slot Coloring", false, false)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(LiveStacks)
+INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
+INITIALIZE_PASS_END(StackSlotColoring, "stack-slot-coloring",
+ "Stack Slot Coloring", false, false)
FunctionPass *llvm::createStackSlotColoringPass(bool RegColor) {
return new StackSlotColoring(RegColor);
if (!LS->hasInterval(FI))
continue;
LiveInterval &li = LS->getInterval(FI);
- li.weight += LiveIntervals::getSpillWeight(false, true, loopDepth);
+ if (!MI->isDebugValue())
+ li.weight += LiveIntervals::getSpillWeight(false, true, loopDepth);
SSRefs[FI].push_back(MI);
}
}
Assignments.resize(LastFI);
// Gather all spill slots into a list.
- DOUT << "Spill slot intervals:\n";
+ DEBUG(dbgs() << "Spill slot intervals:\n");
for (LiveStacks::iterator i = LS->begin(), e = LS->end(); i != e; ++i) {
LiveInterval &li = i->second;
DEBUG(li.dump());
- int FI = li.getStackSlotIndex();
+ int FI = TargetRegisterInfo::stackSlot2Index(li.reg);
if (MFI->isDeadObjectIndex(FI))
continue;
SSIntervals.push_back(&li);
OrigSizes[FI] = MFI->getObjectSize(FI);
AllColors.set(FI);
}
- DOUT << '\n';
+ DEBUG(dbgs() << '\n');
// Sort them by weight.
std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter());
return false;
bool Changed = false;
- DOUT << "Assigning unused registers to spill slots:\n";
+ DEBUG(dbgs() << "Assigning unused registers to spill slots:\n");
for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
LiveInterval *li = SSIntervals[i];
- int SS = li->getStackSlotIndex();
+ int SS = TargetRegisterInfo::stackSlot2Index(li->reg);
if (!UsedColors[SS] || li->weight < 20)
// If the weight is < 20, i.e. two references in a loop with depth 1,
// don't bother with it.
AllColored = false;
continue;
} else {
- DOUT << "Assigning fi#" << RSS << " to " << TRI->getName(Reg) << '\n';
+ DEBUG(dbgs() << "Assigning fi#" << RSS << " to "
+ << TRI->getName(Reg) << '\n');
ColoredRegs.push_back(Reg);
SlotMapping[RSS] = Reg;
SlotIsReg.set(RSS);
++NumEliminated;
}
}
- DOUT << '\n';
+ DEBUG(dbgs() << '\n');
return Changed;
}
// Record the assignment.
Assignments[Color].push_back(li);
- int FI = li->getStackSlotIndex();
- DOUT << "Assigning fi#" << FI << " to fi#" << Color << "\n";
+ int FI = TargetRegisterInfo::stackSlot2Index(li->reg);
+ DEBUG(dbgs() << "Assigning fi#" << FI << " to fi#" << Color << "\n");
// Change size and alignment of the allocated slot. If there are multiple
// objects sharing the same slot, then make sure the size and alignment
BitVector SlotIsReg(NumObjs);
BitVector UsedColors(NumObjs);
- DOUT << "Color spill slot intervals:\n";
+ DEBUG(dbgs() << "Color spill slot intervals:\n");
bool Changed = false;
for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
LiveInterval *li = SSIntervals[i];
- int SS = li->getStackSlotIndex();
+ int SS = TargetRegisterInfo::stackSlot2Index(li->reg);
int NewSS = ColorSlot(li);
assert(NewSS >= 0 && "Stack coloring failed?");
SlotMapping[SS] = NewSS;
Changed |= (SS != NewSS);
}
- DOUT << "\nSpill slots after coloring:\n";
+ DEBUG(dbgs() << "\nSpill slots after coloring:\n");
for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
LiveInterval *li = SSIntervals[i];
- int SS = li->getStackSlotIndex();
+ int SS = TargetRegisterInfo::stackSlot2Index(li->reg);
li->weight = SlotWeights[SS];
}
// Sort them by new weight.
#ifndef NDEBUG
for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i)
DEBUG(SSIntervals[i]->dump());
- DOUT << '\n';
+ DEBUG(dbgs() << '\n');
#endif
// Can we "color" a stack slot with a unused register?
return false;
// Rewrite all MO_FrameIndex operands.
+ SmallVector<SmallSet<unsigned, 4>, 4> NewDefs(MF.getNumBlockIDs());
for (unsigned SS = 0, SE = SSRefs.size(); SS != SE; ++SS) {
bool isReg = SlotIsReg[SS];
int NewFI = SlotMapping[SS];
if (NewFI == -1 || (NewFI == (int)SS && !isReg))
continue;
+ const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
for (unsigned i = 0, e = RefMIs.size(); i != e; ++i)
if (!isReg)
RewriteInstruction(RefMIs[i], SS, NewFI, MF);
else {
// Rewrite to use a register instead.
- const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
- UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, MF);
+ unsigned MBBId = RefMIs[i]->getParent()->getNumber();
+ SmallSet<unsigned, 4> &Defs = NewDefs[MBBId];
+ UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
}
}
// Delete unused stack slots.
while (NextColor != -1) {
- DOUT << "Removing unused stack object fi#" << NextColor << "\n";
+ DEBUG(dbgs() << "Removing unused stack object fi#" << NextColor << "\n");
MFI->RemoveStackObject(NextColor);
NextColor = AllColors.find_next(NextColor);
}
/// to old frame index with new one.
void StackSlotColoring::RewriteInstruction(MachineInstr *MI, int OldFI,
int NewFI, MachineFunction &MF) {
+ // Update the operands.
for (unsigned i = 0, ee = MI->getNumOperands(); i != ee; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isFI())
MO.setIndex(NewFI);
}
- // Update the MachineMemOperand for the new memory location.
- // FIXME: We need a better method of managing these too.
- SmallVector<MachineMemOperand, 2> MMOs(MI->memoperands_begin(),
- MI->memoperands_end());
- MI->clearMemOperands(MF);
+ // Update the memory references. This changes the MachineMemOperands
+ // directly. They may be in use by multiple instructions, however all
+ // instructions using OldFI are being rewritten to use NewFI.
const Value *OldSV = PseudoSourceValue::getFixedStack(OldFI);
- for (unsigned i = 0, ee = MMOs.size(); i != ee; ++i) {
- if (MMOs[i].getValue() != OldSV)
- MI->addMemOperand(MF, MMOs[i]);
- else {
- MachineMemOperand MMO(PseudoSourceValue::getFixedStack(NewFI),
- MMOs[i].getFlags(), MMOs[i].getOffset(),
- MMOs[i].getSize(), MMOs[i].getAlignment());
- MI->addMemOperand(MF, MMO);
- }
- }
+ const Value *NewSV = PseudoSourceValue::getFixedStack(NewFI);
+ for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
+ E = MI->memoperands_end(); I != E; ++I)
+ if ((*I)->getValue() == OldSV)
+ (*I)->setValue(NewSV);
}
/// PropagateBackward - Traverse backward and look for the definition of
if (MII == MBB->begin())
return false;
+ SmallVector<MachineOperand*, 4> Uses;
SmallVector<MachineOperand*, 4> Refs;
while (--MII != MBB->begin()) {
bool FoundDef = false; // Not counting 2address def.
- bool FoundUse = false;
- bool FoundKill = false;
+
+ Uses.clear();
const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MII->getOperand(i);
if (Reg == 0)
continue;
if (Reg == OldReg) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
+ if (MO.isImplicit())
+ return false;
+
+ // Abort the use is actually a sub-register def. We don't have enough
+ // information to figure out if it is really legal.
+ if (MO.getSubReg() || MII->isSubregToReg())
+ return false;
+
+ const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
if (RC && !RC->contains(NewReg))
return false;
if (MO.isUse()) {
- FoundUse = true;
- if (MO.isKill())
- FoundKill = true;
- Refs.push_back(&MO);
+ Uses.push_back(&MO);
} else {
Refs.push_back(&MO);
if (!MII->isRegTiedToUseOperand(i))
return false;
}
}
+
if (FoundDef) {
+ // Found non-two-address def. Stop here.
for (unsigned i = 0, e = Refs.size(); i != e; ++i)
Refs[i]->setReg(NewReg);
return true;
}
+
+ // Two-address uses must be updated as well.
+ for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+ Refs.push_back(Uses[i]);
}
return false;
}
SmallVector<MachineOperand*, 4> Uses;
while (++MII != MBB->end()) {
- bool FoundUse = false;
bool FoundKill = false;
const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
if (Reg == 0)
continue;
if (Reg == OldReg) {
- if (MO.isDef())
+ if (MO.isDef() || MO.isImplicit())
+ return false;
+
+ // Abort the use is actually a sub-register use. We don't have enough
+ // information to figure out if it is really legal.
+ if (MO.getSubReg())
return false;
- const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
+ const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
if (RC && !RC->contains(NewReg))
return false;
- FoundUse = true;
if (MO.isKill())
FoundKill = true;
+
Uses.push_back(&MO);
} else if (TRI->regsOverlap(Reg, NewReg) ||
TRI->regsOverlap(Reg, OldReg))
/// UnfoldAndRewriteInstruction - Rewrite specified instruction by unfolding
/// folded memory references and replacing those references with register
/// references instead.
-void StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
- unsigned Reg,
- const TargetRegisterClass *RC,
- MachineFunction &MF) {
+void
+StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
+ unsigned Reg,
+ const TargetRegisterClass *RC,
+ SmallSet<unsigned, 4> &Defs,
+ MachineFunction &MF) {
MachineBasicBlock *MBB = MI->getParent();
if (unsigned DstReg = TII->isLoadFromStackSlot(MI, OldFI)) {
if (PropagateForward(MI, MBB, DstReg, Reg)) {
- DOUT << "Eliminated load: ";
+ DEBUG(dbgs() << "Eliminated load: ");
DEBUG(MI->dump());
++NumLoadElim;
} else {
- TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC);
+ BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
+ DstReg).addReg(Reg);
++NumRegRepl;
}
+
+ if (!Defs.count(Reg)) {
+ // If this is the first use of Reg in this MBB and it wasn't previously
+ // defined in MBB, add it to livein.
+ MBB->addLiveIn(Reg);
+ Defs.insert(Reg);
+ }
} else if (unsigned SrcReg = TII->isStoreToStackSlot(MI, OldFI)) {
if (MI->killsRegister(SrcReg) && PropagateBackward(MI, MBB, SrcReg, Reg)) {
- DOUT << "Eliminated store: ";
+ DEBUG(dbgs() << "Eliminated store: ");
DEBUG(MI->dump());
++NumStoreElim;
} else {
- TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC);
+ BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY), Reg)
+ .addReg(SrcReg);
++NumRegRepl;
}
+
+ // Remember reg has been defined in MBB.
+ Defs.insert(Reg);
} else {
SmallVector<MachineInstr*, 4> NewMIs;
bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, false, false, NewMIs);
- Success = Success; // Silence compiler warning.
+ (void)Success; // Silence compiler warning.
assert(Success && "Failed to unfold!");
- MBB->insert(MI, NewMIs[0]);
+ MachineInstr *NewMI = NewMIs[0];
+ MBB->insert(MI, NewMI);
++NumRegRepl;
+
+ if (NewMI->readsRegister(Reg)) {
+ if (!Defs.count(Reg))
+ // If this is the first use of Reg in this MBB and it wasn't previously
+ // defined in MBB, add it to livein.
+ MBB->addLiveIn(Reg);
+ Defs.insert(Reg);
+ }
}
MBB->erase(MI);
}
if (DCELimit != -1 && (int)NumDead >= DCELimit)
break;
- MachineBasicBlock::iterator NextMI = next(I);
+ MachineBasicBlock::iterator NextMI = llvm::next(I);
if (NextMI == MBB->end()) continue;
int FirstSS, SecondSS;
bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) {
- DOUT << "********** Stack Slot Coloring **********\n";
+ DEBUG({
+ dbgs() << "********** Stack Slot Coloring **********\n"
+ << "********** Function: "
+ << MF.getFunction()->getName() << '\n';
+ });
MFI = MF.getFrameInfo();
MRI = &MF.getRegInfo();
return false;
}
+ // If there are calls to setjmp or sigsetjmp, don't perform stack slot
+ // coloring. The stack could be modified before the longjmp is executed,
+ // resulting in the wrong value being used afterwards. (See
+ // <rdar://problem/8007500>.)
+ if (MF.callsSetJmp())
+ return false;
+
// Gather spill slot references
ScanForSpillSlotRefs(MF);
InitializeSlots();
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