#define DEBUG_TYPE "spiller"
#include "Spiller.h"
-#include "VirtRegMap.h"
-#include "LiveRangeEdit.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
using namespace llvm;
/// Add spill ranges for every use/def of the live interval, inserting loads
/// immediately before each use, and stores after each def. No folding or
/// remat is attempted.
- void trivialSpillEverywhere(LiveInterval *li,
- SmallVectorImpl<LiveInterval*> &newIntervals) {
+ void trivialSpillEverywhere(LiveRangeEdit& LRE) {
+ LiveInterval* li = &LRE.getParent();
+
DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
- assert(li->weight != HUGE_VALF &&
+ assert(li->weight != llvm::huge_valf &&
"Attempting to spill already spilled value.");
assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
indices.push_back(i);
}
- // Create a new vreg & interval for this instr.
- unsigned newVReg = mri->createVirtualRegister(trc);
- vrm->grow();
- vrm->assignVirt2StackSlot(newVReg, ss);
- LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
- newLI->weight = HUGE_VALF;
+ // Create a new virtual register for the load and/or store.
+ unsigned NewVReg = LRE.create();
// Update the reg operands & kill flags.
for (unsigned i = 0; i < indices.size(); ++i) {
unsigned mopIdx = indices[i];
MachineOperand &mop = mi->getOperand(mopIdx);
- mop.setReg(newVReg);
+ mop.setReg(NewVReg);
if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
mop.setIsKill(true);
}
// Insert reload if necessary.
MachineBasicBlock::iterator miItr(mi);
if (hasUse) {
- tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
+ MachineInstrSpan MIS(miItr);
+
+ tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc,
tri);
- MachineInstr *loadInstr(prior(miItr));
- SlotIndex loadIndex =
- lis->InsertMachineInstrInMaps(loadInstr).getRegSlot();
- SlotIndex endIndex = loadIndex.getNextIndex();
- VNInfo *loadVNI =
- newLI->getNextValue(loadIndex, 0, lis->getVNInfoAllocator());
- newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
+ lis->InsertMachineInstrRangeInMaps(MIS.begin(), miItr);
}
// Insert store if necessary.
if (hasDef) {
- tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
+ MachineInstrSpan MIS(miItr);
+
+ tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), NewVReg,
true, ss, trc, tri);
- MachineInstr *storeInstr(llvm::next(miItr));
- SlotIndex storeIndex =
- lis->InsertMachineInstrInMaps(storeInstr).getRegSlot();
- SlotIndex beginIndex = storeIndex.getPrevIndex();
- VNInfo *storeVNI =
- newLI->getNextValue(beginIndex, 0, lis->getVNInfoAllocator());
- newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
+ lis->InsertMachineInstrRangeInMaps(llvm::next(miItr), MIS.end());
}
-
- newIntervals.push_back(newLI);
}
}
};
void spill(LiveRangeEdit &LRE) {
// Ignore spillIs - we don't use it.
- trivialSpillEverywhere(&LRE.getParent(), *LRE.getNewVRegs());
+ trivialSpillEverywhere(LRE);
}
};
MachineFunction &mf,
VirtRegMap &vrm) {
switch (spillerOpt) {
- default: assert(0 && "unknown spiller");
case trivial: return new TrivialSpiller(pass, mf, vrm);
case inline_: return createInlineSpiller(pass, mf, vrm);
}
+ llvm_unreachable("Invalid spiller optimization");
}