//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "spiller"
-
#include "Spiller.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
using namespace llvm;
+#define DEBUG_TYPE "spiller"
+
namespace {
enum SpillerName { trivial, inline_ };
}
lis = &pass.getAnalysis<LiveIntervals>();
mfi = mf.getFrameInfo();
mri = &mf.getRegInfo();
- tii = mf.getTarget().getInstrInfo();
- tri = mf.getTarget().getRegisterInfo();
+ tii = mf.getSubtarget().getInstrInfo();
+ tri = mf.getSubtarget().getRegisterInfo();
}
/// Add spill ranges for every use/def of the live interval, inserting loads
unsigned ss = vrm->assignVirt2StackSlot(li->reg);
// Iterate over reg uses/defs.
- for (MachineRegisterInfo::reg_iterator
- regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
+ for (MachineRegisterInfo::reg_instr_iterator
+ regItr = mri->reg_instr_begin(li->reg);
+ regItr != mri->reg_instr_end();) {
// Grab the use/def instr.
MachineInstr *mi = &*regItr;
DEBUG(dbgs() << " Processing " << *mi);
// Step regItr to the next use/def instr.
- do {
- ++regItr;
- } while (regItr != mri->reg_end() && (&*regItr == mi));
+ ++regItr;
// Collect uses & defs for this instr.
SmallVector<unsigned, 2> indices;
if (hasDef) {
MachineInstrSpan MIS(miItr);
- tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), NewVReg,
+ tii->storeRegToStackSlot(*mi->getParent(), std::next(miItr), NewVReg,
true, ss, trc, tri);
- lis->InsertMachineInstrRangeInMaps(llvm::next(miItr), MIS.end());
+ lis->InsertMachineInstrRangeInMaps(std::next(miItr), MIS.end());
}
}
}
VirtRegMap &vrm)
: SpillerBase(pass, mf, vrm) {}
- void spill(LiveRangeEdit &LRE) {
+ void spill(LiveRangeEdit &LRE) override {
// Ignore spillIs - we don't use it.
trivialSpillEverywhere(LRE);
}