#include "Spiller.h"
#include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveRangeEdit.h"
+#include "llvm/CodeGen/LiveStackAnalysis.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
-
-#include <algorithm>
-#include <map>
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+namespace {
+ enum SpillerName { trivial, inline_ };
+}
+
+static cl::opt<SpillerName>
+spillerOpt("spiller",
+ cl::desc("Spiller to use: (default: standard)"),
+ cl::Prefix,
+ cl::values(clEnumVal(trivial, "trivial spiller"),
+ clEnumValN(inline_, "inline", "inline spiller"),
+ clEnumValEnd),
+ cl::init(trivial));
+
+// Spiller virtual destructor implementation.
Spiller::~Spiller() {}
namespace {
-class TrivialSpiller : public Spiller {
-public:
- TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) :
- mf(mf), lis(lis), vrm(vrm)
+/// Utility class for spillers.
+class SpillerBase : public Spiller {
+protected:
+ MachineFunctionPass *pass;
+ MachineFunction *mf;
+ VirtRegMap *vrm;
+ LiveIntervals *lis;
+ MachineFrameInfo *mfi;
+ MachineRegisterInfo *mri;
+ const TargetInstrInfo *tii;
+ const TargetRegisterInfo *tri;
+
+ /// Construct a spiller base.
+ SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
+ : pass(&pass), mf(&mf), vrm(&vrm)
{
- mfi = mf->getFrameInfo();
- mri = &mf->getRegInfo();
- tii = mf->getTarget().getInstrInfo();
+ lis = &pass.getAnalysis<LiveIntervals>();
+ mfi = mf.getFrameInfo();
+ mri = &mf.getRegInfo();
+ tii = mf.getTarget().getInstrInfo();
+ tri = mf.getTarget().getRegisterInfo();
}
- std::vector<LiveInterval*> spill(LiveInterval *li) {
+ /// Add spill ranges for every use/def of the live interval, inserting loads
+ /// immediately before each use, and stores after each def. No folding or
+ /// remat is attempted.
+ void trivialSpillEverywhere(LiveRangeEdit& LRE) {
+ LiveInterval* li = &LRE.getParent();
- DOUT << "Trivial spiller spilling " << *li << "\n";
+ DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
assert(li->weight != HUGE_VALF &&
"Attempting to spill already spilled value.");
- assert(!li->isStackSlot() &&
+ assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
"Trying to spill a stack slot.");
- std::vector<LiveInterval*> added;
-
+ DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
+
const TargetRegisterClass *trc = mri->getRegClass(li->reg);
- /*unsigned ss = mfi->CreateStackObject(trc->getSize(),
- trc->getAlignment());*/
unsigned ss = vrm->assignVirt2StackSlot(li->reg);
- MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(li->reg);
-
- while (regItr != mri->reg_end()) {
+ // Iterate over reg uses/defs.
+ for (MachineRegisterInfo::reg_iterator
+ regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
+ // Grab the use/def instr.
MachineInstr *mi = &*regItr;
+ DEBUG(dbgs() << " Processing " << *mi);
+
+ // Step regItr to the next use/def instr.
+ do {
+ ++regItr;
+ } while (regItr != mri->reg_end() && (&*regItr == mi));
+
+ // Collect uses & defs for this instr.
SmallVector<unsigned, 2> indices;
bool hasUse = false;
bool hasDef = false;
-
for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
MachineOperand &op = mi->getOperand(i);
-
if (!op.isReg() || op.getReg() != li->reg)
continue;
-
hasUse |= mi->getOperand(i).isUse();
hasDef |= mi->getOperand(i).isDef();
-
indices.push_back(i);
}
- unsigned newVReg = mri->createVirtualRegister(trc);
- LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
+ // Create a new vreg & interval for this instr.
+ LiveInterval *newLI = &LRE.create();
newLI->weight = HUGE_VALF;
- vrm->grow();
- vrm->assignVirt2StackSlot(newVReg, ss);
-
+ // Update the reg operands & kill flags.
for (unsigned i = 0; i < indices.size(); ++i) {
- mi->getOperand(indices[i]).setReg(newVReg);
-
- if (mi->getOperand(indices[i]).isUse()) {
- mi->getOperand(indices[i]).setIsKill(true);
+ unsigned mopIdx = indices[i];
+ MachineOperand &mop = mi->getOperand(mopIdx);
+ mop.setReg(newLI->reg);
+ if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
+ mop.setIsKill(true);
}
}
+ assert(hasUse || hasDef);
+ // Insert reload if necessary.
+ MachineBasicBlock::iterator miItr(mi);
if (hasUse) {
- unsigned loadInstIdx = insertLoadFor(mi, ss, newVReg, trc);
- unsigned start = lis->getDefIndex(loadInstIdx),
- end = lis->getUseIndex(lis->getInstructionIndex(mi));
-
- VNInfo *vni =
- newLI->getNextValue(loadInstIdx, 0, lis->getVNInfoAllocator());
- vni->kills.push_back(lis->getInstructionIndex(mi));
- LiveRange lr(start, end, vni);
-
- newLI->addRange(lr);
- added.push_back(newLI);
+ tii->loadRegFromStackSlot(*mi->getParent(), miItr, newLI->reg, ss, trc,
+ tri);
+ MachineInstr *loadInstr(prior(miItr));
+ SlotIndex loadIndex =
+ lis->InsertMachineInstrInMaps(loadInstr).getRegSlot();
+ SlotIndex endIndex = loadIndex.getNextIndex();
+ VNInfo *loadVNI =
+ newLI->getNextValue(loadIndex, lis->getVNInfoAllocator());
+ newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
}
+ // Insert store if necessary.
if (hasDef) {
- unsigned storeInstIdx = insertStoreFor(mi, ss, newVReg, trc);
- unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
- end = lis->getUseIndex(storeInstIdx);
-
- VNInfo *vni =
- newLI->getNextValue(storeInstIdx, 0, lis->getVNInfoAllocator());
- vni->kills.push_back(storeInstIdx);
- LiveRange lr(start, end, vni);
-
- newLI->addRange(lr);
- added.push_back(newLI);
+ tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr),newLI->reg,
+ true, ss, trc, tri);
+ MachineInstr *storeInstr(llvm::next(miItr));
+ SlotIndex storeIndex =
+ lis->InsertMachineInstrInMaps(storeInstr).getRegSlot();
+ SlotIndex beginIndex = storeIndex.getPrevIndex();
+ VNInfo *storeVNI =
+ newLI->getNextValue(beginIndex, lis->getVNInfoAllocator());
+ newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
}
-
- regItr = mri->reg_begin(li->reg);
- }
-
-
- return added;
- }
-
-
-private:
-
- MachineFunction *mf;
- LiveIntervals *lis;
- MachineFrameInfo *mfi;
- MachineRegisterInfo *mri;
- const TargetInstrInfo *tii;
- VirtRegMap *vrm;
-
-
-
- void makeRoomForInsertBefore(MachineInstr *mi) {
- if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
- lis->computeNumbering();
}
-
- assert(lis->hasGapBeforeInstr(lis->getInstructionIndex(mi)));
- }
-
- unsigned insertStoreFor(MachineInstr *mi, unsigned ss,
- unsigned newVReg,
- const TargetRegisterClass *trc) {
- MachineBasicBlock::iterator nextInstItr(mi);
- ++nextInstItr;
-
- makeRoomForInsertBefore(&*nextInstItr);
-
- unsigned miIdx = lis->getInstructionIndex(mi);
-
- tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg,
- true, ss, trc);
- MachineBasicBlock::iterator storeInstItr(mi);
- ++storeInstItr;
- MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx + LiveIntervals::InstrSlots::NUM;
-
- assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
- "Store inst index already in use.");
-
- lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
-
- return storeInstIdx;
}
+};
- unsigned insertLoadFor(MachineInstr *mi, unsigned ss,
- unsigned newVReg,
- const TargetRegisterClass *trc) {
- MachineBasicBlock::iterator useInstItr(mi);
+} // end anonymous namespace
- makeRoomForInsertBefore(mi);
-
- unsigned miIdx = lis->getInstructionIndex(mi);
-
- tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc);
- MachineBasicBlock::iterator loadInstItr(mi);
- --loadInstItr;
- MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx - LiveIntervals::InstrSlots::NUM;
+namespace {
- assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
- "Load inst index already in use.");
+/// Spills any live range using the spill-everywhere method with no attempt at
+/// folding.
+class TrivialSpiller : public SpillerBase {
+public:
- lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
+ TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
+ VirtRegMap &vrm)
+ : SpillerBase(pass, mf, vrm) {}
- return loadInstIdx;
+ void spill(LiveRangeEdit &LRE) {
+ // Ignore spillIs - we don't use it.
+ trivialSpillEverywhere(LRE);
}
-
};
-}
+} // end anonymous namespace
+void Spiller::anchor() { }
-llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
- VirtRegMap *vrm) {
- return new TrivialSpiller(mf, lis, vrm);
+llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
+ MachineFunction &mf,
+ VirtRegMap &vrm) {
+ switch (spillerOpt) {
+ case trivial: return new TrivialSpiller(pass, mf, vrm);
+ case inline_: return createInlineSpiller(pass, mf, vrm);
+ }
+ llvm_unreachable("Invalid spiller optimization");
}
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