#include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/Value.h"
+#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
cl::init(true));
static cl::opt<bool>
-NewHeuristic("new-coalescer-heuristic",
- cl::desc("Use new coalescer heuristic"),
- cl::init(false), cl::Hidden);
-
-static cl::opt<bool>
-CrossClassJoin("join-cross-class-copies",
- cl::desc("Coalesce cross register class copies"),
+DisableCrossClassJoin("disable-cross-class-join",
+ cl::desc("Avoid coalescing cross register class copies"),
cl::init(false), cl::Hidden);
static cl::opt<bool>
cl::desc("Tweak heuristics for joining phys reg with vr"),
cl::init(false), cl::Hidden);
-static RegisterPass<SimpleRegisterCoalescing>
+static RegisterPass<SimpleRegisterCoalescing>
X("simple-register-coalescing", "Simple Register Coalescing");
// Declare that we implement the RegisterCoalescer interface
const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesCFG();
+ AU.addRequired<AliasAnalysis>();
AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>();
AU.addRequired<MachineLoopInfo>();
bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
LiveInterval &IntB,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ LiveIndex CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
// BValNo is a value number in B that is defined by a copy from A. 'B3' in
// the example above.
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
assert(BLR != IntB.end() && "Live range not found!");
VNInfo *BValNo = BLR->valno;
-
+
// Get the location that B is defined at. Two options: either this value has
- // an unknown definition point or it is defined at CopyIdx. If unknown, we
+ // an unknown definition point or it is defined at CopyIdx. If unknown, we
// can't process it.
- if (!BValNo->copy) return false;
+ if (!BValNo->getCopy()) return false;
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
-
+
// AValNo is the value number in A that defines the copy, A3 in the example.
- LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
+ LiveIndex CopyUseIdx = li_->getUseIndex(CopyIdx);
+ LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
assert(ALR != IntA.end() && "Live range not found!");
VNInfo *AValNo = ALR->valno;
// If it's re-defined by an early clobber somewhere in the live range, then
// The coalescer has no idea there was a def in the middle of [174,230].
if (AValNo->hasRedefByEC())
return false;
-
- // If AValNo is defined as a copy from IntB, we can potentially process this.
+
+ // If AValNo is defined as a copy from IntB, we can potentially process this.
// Get the instruction that defines this value number.
unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
if (!SrcReg) return false; // Not defined by a copy.
-
+
// If the value number is not defined by a copy instruction, ignore it.
// If the source register comes from an interval other than IntB, we can't
// handle this.
if (SrcReg != IntB.reg) return false;
-
+
// Get the LiveRange in IntB that this value number starts with.
- LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
+ LiveInterval::iterator ValLR =
+ IntB.FindLiveRangeContaining(li_->getPrevSlot(AValNo->def));
assert(ValLR != IntB.end() && "Live range not found!");
-
+
// Make sure that the end of the live range is inside the same block as
// CopyMI.
- MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
- if (!ValLREndInst ||
+ MachineInstr *ValLREndInst =
+ li_->getInstructionFromIndex(li_->getPrevSlot(ValLR->end));
+ if (!ValLREndInst ||
ValLREndInst->getParent() != CopyMI->getParent()) return false;
// Okay, we now know that ValLR ends in the same block that the CopyMI
*tri_->getSubRegisters(IntB.reg)) {
for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
- DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
+ DEBUG({
+ errs() << "Interfere with sub-register ";
+ li_->getInterval(*SR).print(errs(), tri_);
+ });
return false;
}
}
-
- DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
-
- unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
+
+ DEBUG({
+ errs() << "\nExtending: ";
+ IntB.print(errs(), tri_);
+ });
+
+ LiveIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
// We are about to delete CopyMI, so need to remove it as the 'instruction
// that defines this value #'. Update the the valnum with the new defining
// instruction #.
BValNo->def = FillerStart;
- BValNo->copy = NULL;
-
+ BValNo->setCopy(0);
+
// Okay, we can merge them. We need to insert a new liverange:
// [ValLR.end, BLR.begin) of either value number, then we merge the
// two value numbers.
IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
// If the IntB live range is assigned to a physical register, and if that
- // physreg has sub-registers, update their live intervals as well.
+ // physreg has sub-registers, update their live intervals as well.
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
LiveInterval &SRLI = li_->getInterval(*SR);
IntB.addKills(ValLR->valno, BValNo->kills);
IntB.MergeValueNumberInto(BValNo, ValLR->valno);
}
- DOUT << " result = "; IntB.print(DOUT, tri_);
- DOUT << "\n";
+ DEBUG({
+ errs() << " result = ";
+ IntB.print(errs(), tri_);
+ errs() << "\n";
+ });
// If the source instruction was killing the source register before the
// merge, unset the isKill marker given the live range has been extended.
int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
if (UIdx != -1) {
ValLREndInst->getOperand(UIdx).setIsKill(false);
- IntB.removeKill(ValLR->valno, FillerStart);
+ ValLR->valno->removeKill(FillerStart);
}
+ // If the copy instruction was killing the destination register before the
+ // merge, find the last use and trim the live range. That will also add the
+ // isKill marker.
+ if (CopyMI->killsRegister(IntA.reg))
+ TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
+
++numExtends;
return true;
}
return false;
}
+static void
+TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
+ for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
+ i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isImplicit())
+ NewMI->addOperand(MO);
+ }
+}
+
/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
/// being the source and IntB being the dest, thus this defines a value number
/// in IntB. If the source value number (in IntA) is defined by a commutable
bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
LiveInterval &IntB,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ LiveIndex CopyIdx =
+ li_->getDefIndex(li_->getInstructionIndex(CopyMI));
// FIXME: For now, only eliminate the copy by commuting its def when the
// source register is a virtual register. We want to guard against cases
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
assert(BLR != IntB.end() && "Live range not found!");
VNInfo *BValNo = BLR->valno;
-
+
// Get the location that B is defined at. Two options: either this value has
- // an unknown definition point or it is defined at CopyIdx. If unknown, we
+ // an unknown definition point or it is defined at CopyIdx. If unknown, we
// can't process it.
- if (!BValNo->copy) return false;
+ if (!BValNo->getCopy()) return false;
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
-
+
// AValNo is the value number in A that defines the copy, A3 in the example.
- LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
+ LiveInterval::iterator ALR =
+ IntA.FindLiveRangeContaining(li_->getPrevSlot(CopyIdx));
+
assert(ALR != IntA.end() && "Live range not found!");
VNInfo *AValNo = ALR->valno;
// If other defs can reach uses of this def, then it's not safe to perform
for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
UE = mri_->use_end(); UI != UE; ++UI) {
MachineInstr *UseMI = &*UI;
- unsigned UseIdx = li_->getInstructionIndex(UseMI);
+ LiveIndex UseIdx = li_->getInstructionIndex(UseMI);
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
if (ULR == IntA.end())
continue;
bool BHasPHIKill = BValNo->hasPHIKill();
SmallVector<VNInfo*, 4> BDeadValNos;
VNInfo::KillSet BKills;
- std::map<unsigned, unsigned> BExtend;
+ std::map<LiveIndex, LiveIndex> BExtend;
// If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
// A = or A, B
++UI;
if (JoinedCopies.count(UseMI))
continue;
- unsigned UseIdx = li_->getInstructionIndex(UseMI);
+ LiveIndex UseIdx= li_->getUseIndex(li_->getInstructionIndex(UseMI));
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
if (ULR == IntA.end() || ULR->valno != AValNo)
continue;
if (Extended)
UseMO.setIsKill(false);
else
- BKills.push_back(VNInfo::KillInfo(false, li_->getUseIndex(UseIdx)+1));
+ BKills.push_back(li_->getNextSlot(UseIdx));
}
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
// This copy will become a noop. If it's defining a new val#,
// remove that val# as well. However this live range is being
// extended to the end of the existing live range defined by the copy.
- unsigned DefIdx = li_->getDefIndex(UseIdx);
+ LiveIndex DefIdx = li_->getDefIndex(UseIdx);
const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
BHasPHIKill |= DLR->valno->hasPHIKill();
assert(DLR->valno->def == DefIdx);
// We need to insert a new liverange: [ALR.start, LastUse). It may be we can
// simply extend BLR if CopyMI doesn't end the range.
- DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
+ DEBUG({
+ errs() << "\nExtending: ";
+ IntB.print(errs(), tri_);
+ });
// Remove val#'s defined by copies that will be coalesced away.
for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
// is updated. Kills are also updated.
VNInfo *ValNo = BValNo;
ValNo->def = AValNo->def;
- ValNo->copy = NULL;
+ ValNo->setCopy(0);
for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
- unsigned Kill = ValNo->kills[j].killIdx;
- if (Kill != BLR->end)
- BKills.push_back(VNInfo::KillInfo(ValNo->kills[j].isPHIKill, Kill));
+ if (ValNo->kills[j] != BLR->end)
+ BKills.push_back(ValNo->kills[j]);
}
ValNo->kills.clear();
for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
AI != AE; ++AI) {
if (AI->valno != AValNo) continue;
- unsigned End = AI->end;
- std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
+ LiveIndex End = AI->end;
+ std::map<LiveIndex, LiveIndex>::iterator
+ EI = BExtend.find(End);
if (EI != BExtend.end())
End = EI->second;
IntB.addRange(LiveRange(AI->start, End, ValNo));
// If the IntB live range is assigned to a physical register, and if that
- // physreg has sub-registers, update their live intervals as well.
+ // physreg has sub-registers, update their live intervals as well.
if (BHasSubRegs) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
LiveInterval &SRLI = li_->getInterval(*SR);
IntB.addKills(ValNo, BKills);
ValNo->setHasPHIKill(BHasPHIKill);
- DOUT << " result = "; IntB.print(DOUT, tri_);
- DOUT << "\n";
+ DEBUG({
+ errs() << " result = ";
+ IntB.print(errs(), tri_);
+ errs() << '\n';
+ errs() << "\nShortening: ";
+ IntA.print(errs(), tri_);
+ });
- DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
IntA.removeValNo(AValNo);
- DOUT << " result = "; IntA.print(DOUT, tri_);
- DOUT << "\n";
+
+ DEBUG({
+ errs() << " result = ";
+ IntA.print(errs(), tri_);
+ errs() << '\n';
+ });
++numCommutes;
return true;
/// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
/// from a physical register live interval as well as from the live intervals
/// of its sub-registers.
-static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
+static void removeRange(LiveInterval &li,
+ LiveIndex Start, LiveIndex End,
LiveIntervals *li_, const TargetRegisterInfo *tri_) {
li.removeRange(Start, End, true);
if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
if (!li_->hasInterval(*SR))
continue;
LiveInterval &sli = li_->getInterval(*SR);
- unsigned RemoveEnd = Start;
+ LiveIndex RemoveStart = Start;
+ LiveIndex RemoveEnd = Start;
while (RemoveEnd != End) {
- LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
+ LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
if (LR == sli.end())
break;
RemoveEnd = (LR->end < End) ? LR->end : End;
- sli.removeRange(Start, RemoveEnd, true);
- Start = RemoveEnd;
+ sli.removeRange(RemoveStart, RemoveEnd, true);
+ RemoveStart = RemoveEnd;
}
}
}
/// as the copy instruction, trim the live interval to the last use and return
/// true.
bool
-SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(unsigned CopyIdx,
+SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(LiveIndex CopyIdx,
MachineBasicBlock *CopyMBB,
LiveInterval &li,
const LiveRange *LR) {
- unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
- unsigned LastUseIdx;
- MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
- LastUseIdx);
+ LiveIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
+ LiveIndex LastUseIdx;
+ MachineOperand *LastUse =
+ lastRegisterUse(LR->start, li_->getPrevSlot(CopyIdx), li.reg, LastUseIdx);
if (LastUse) {
MachineInstr *LastUseMI = LastUse->getParent();
if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
// of last use.
LastUse->setIsKill();
removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
- li.addKill(LR->valno, LastUseIdx+1, false);
+ LR->valno->addKill(li_->getNextSlot(LastUseIdx));
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
DstReg == li.reg) {
// Is it livein?
if (LR->start <= MBBStart && LR->end > MBBStart) {
- if (LR->start == 0) {
+ if (LR->start == LiveIndex()) {
assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
// Live-in to the function but dead. Remove it from entry live-in set.
mf_->begin()->removeLiveIn(li.reg);
/// computation, replace the copy by rematerialize the definition.
bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
unsigned DstReg,
+ unsigned DstSubIdx,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
+ LiveIndex CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
assert(SrcLR != SrcInt.end() && "Live range not found!");
VNInfo *ValNo = SrcLR->valno;
const TargetInstrDesc &TID = DefMI->getDesc();
if (!TID.isAsCheapAsAMove())
return false;
- if (!DefMI->getDesc().isRematerializable() ||
- !tii_->isTriviallyReMaterializable(DefMI))
+ if (!tii_->isTriviallyReMaterializable(DefMI, AA))
return false;
bool SawStore = false;
- if (!DefMI->isSafeToMove(tii_, SawStore))
+ if (!DefMI->isSafeToMove(tii_, SawStore, AA))
return false;
if (TID.getNumDefs() != 1)
return false;
- // Make sure the copy destination register class fits the instruction
- // definition register class. The mismatch can happen as a result of earlier
- // extract_subreg, insert_subreg, subreg_to_reg coalescing.
- const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
- if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
- if (mri_->getRegClass(DstReg) != RC)
+ if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) {
+ // Make sure the copy destination register class fits the instruction
+ // definition register class. The mismatch can happen as a result of earlier
+ // extract_subreg, insert_subreg, subreg_to_reg coalescing.
+ const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
+ if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
+ if (mri_->getRegClass(DstReg) != RC)
+ return false;
+ } else if (!RC->contains(DstReg))
return false;
- } else if (!RC->contains(DstReg))
- return false;
+ }
- unsigned DefIdx = li_->getDefIndex(CopyIdx);
+ // If destination register has a sub-register index on it, make sure it mtches
+ // the instruction register class.
+ if (DstSubIdx) {
+ const TargetInstrDesc &TID = DefMI->getDesc();
+ if (TID.getNumDefs() != 1)
+ return false;
+ const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
+ const TargetRegisterClass *DstSubRC =
+ DstRC->getSubRegisterRegClass(DstSubIdx);
+ const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
+ if (DefRC == DstRC)
+ DstSubIdx = 0;
+ else if (DefRC != DstSubRC)
+ return false;
+ }
+
+ LiveIndex DefIdx = li_->getDefIndex(CopyIdx);
const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
- DLR->valno->copy = NULL;
+ DLR->valno->setCopy(0);
// Don't forget to update sub-register intervals.
if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
if (!li_->hasInterval(*SR))
continue;
DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
- if (DLR && DLR->valno->copy == CopyMI)
- DLR->valno->copy = NULL;
+ if (DLR && DLR->valno->getCopy() == CopyMI)
+ DLR->valno->setCopy(0);
}
}
}
MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
- tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
+ tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI);
MachineInstr *NewMI = prior(MII);
if (checkForDeadDef) {
// should mark it dead:
if (DefMI->getParent() == MBB) {
DefMI->addRegisterDead(SrcInt.reg, tri_);
- SrcLR->end = SrcLR->start + 1;
+ SrcLR->end = li_->getNextSlot(SrcLR->start);
}
}
if (MO.isDef() && li_->hasInterval(MO.getReg())) {
unsigned Reg = MO.getReg();
DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
- if (DLR && DLR->valno->copy == CopyMI)
- DLR->valno->copy = NULL;
+ if (DLR && DLR->valno->getCopy() == CopyMI)
+ DLR->valno->setCopy(0);
}
}
+ TransferImplicitOps(CopyMI, NewMI);
li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
CopyMI->eraseFromParent();
ReMatCopies.insert(CopyMI);
return true;
}
-/// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
-///
-bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
- unsigned DstReg) const {
- MachineBasicBlock *MBB = CopyMI->getParent();
- const MachineLoop *L = loopInfo->getLoopFor(MBB);
- if (!L)
- return false;
- if (MBB != L->getLoopLatch())
- return false;
-
- LiveInterval &LI = li_->getInterval(DstReg);
- unsigned DefIdx = li_->getInstructionIndex(CopyMI);
- LiveInterval::const_iterator DstLR =
- LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
- if (DstLR == LI.end())
- return false;
- if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIKill)
- return true;
- return false;
-}
-
/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
/// update the subregister number if it is not zero. If DstReg is a
/// physical register and the existing subregister number of the def / use
CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
// If the use is a copy and it won't be coalesced away, and its source
// is defined by a trivial computation, try to rematerialize it instead.
- if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
+ if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
+ CopyDstSubIdx, UseMI))
continue;
}
(TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
allocatableRegs_[CopyDstReg])) {
LiveInterval &LI = li_->getInterval(CopyDstReg);
- unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
+ LiveIndex DefIdx =
+ li_->getDefIndex(li_->getInstructionIndex(UseMI));
if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
if (DLR->valno->def == DefIdx)
- DLR->valno->copy = UseMI;
+ DLR->valno->setCopy(UseMI);
}
}
}
}
-/// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
-/// registers due to insert_subreg coalescing. e.g.
-/// r1024 = op
-/// r1025 = implicit_def
-/// r1025 = insert_subreg r1025, r1024
-/// = op r1025
-/// =>
-/// r1025 = op
-/// r1025 = implicit_def
-/// r1025 = insert_subreg r1025, r1025
-/// = op r1025
-void
-SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
- for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
- E = mri_->reg_end(); I != E; ) {
- MachineOperand &O = I.getOperand();
- MachineInstr *DefMI = &*I;
- ++I;
- if (!O.isDef())
- continue;
- if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
- continue;
- if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
- continue;
- li_->RemoveMachineInstrFromMaps(DefMI);
- DefMI->eraseFromParent();
- }
-}
-
/// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
/// due to live range lengthening as the result of coalescing.
void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
UE = mri_->use_end(); UI != UE; ++UI) {
MachineOperand &UseMO = UI.getOperand();
- if (UseMO.isKill()) {
- MachineInstr *UseMI = UseMO.getParent();
- unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
- const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
- if (!UI || !LI.isKill(UI->valno, UseIdx+1))
- UseMO.setIsKill(false);
+ if (!UseMO.isKill())
+ continue;
+ MachineInstr *UseMI = UseMO.getParent();
+ LiveIndex UseIdx =
+ li_->getUseIndex(li_->getInstructionIndex(UseMI));
+ const LiveRange *LR = LI.getLiveRangeContaining(UseIdx);
+ if (!LR ||
+ (!LR->valno->isKill(li_->getNextSlot(UseIdx)) &&
+ LR->valno->def != li_->getNextSlot(UseIdx))) {
+ // Interesting problem. After coalescing reg1027's def and kill are both
+ // at the same point: %reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
+ //
+ // bb5:
+ // 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
+ // 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
+ // 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
+ // 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
+ // 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
+ //
+ // Do not remove the kill marker on t2LDRi12.
+ UseMO.setIsKill(false);
}
}
}
/// Return true if live interval is removed.
bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
+ LiveIndex CopyIdx = li_->getInstructionIndex(CopyMI);
LiveInterval::iterator MLR =
li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
if (MLR == li.end())
return false; // Already removed by ShortenDeadCopySrcLiveRange.
- unsigned RemoveStart = MLR->start;
- unsigned RemoveEnd = MLR->end;
- unsigned DefIdx = li_->getDefIndex(CopyIdx);
+ LiveIndex RemoveStart = MLR->start;
+ LiveIndex RemoveEnd = MLR->end;
+ LiveIndex DefIdx = li_->getDefIndex(CopyIdx);
// Remove the liverange that's defined by this.
- if (RemoveStart == DefIdx && RemoveEnd == DefIdx+1) {
+ if (RemoveStart == DefIdx && RemoveEnd == li_->getNextSlot(DefIdx)) {
removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
return removeIntervalIfEmpty(li, li_, tri_);
}
/// the val# it defines. If the live interval becomes empty, remove it as well.
bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
MachineInstr *DefMI) {
- unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
+ LiveIndex DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
if (DefIdx != MLR->valno->def)
return false;
/// PropagateDeadness - Propagate the dead marker to the instruction which
/// defines the val#.
static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
- unsigned &LRStart, LiveIntervals *li_,
+ LiveIndex &LRStart, LiveIntervals *li_,
const TargetRegisterInfo* tri_) {
MachineInstr *DefMI =
li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
if (DefMI && DefMI != CopyMI) {
- int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
- if (DeadIdx != -1) {
+ int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false);
+ if (DeadIdx != -1)
DefMI->getOperand(DeadIdx).setIsDead();
- // A dead def should have a single cycle interval.
- ++LRStart;
- }
+ else
+ DefMI->addOperand(MachineOperand::CreateReg(li.reg,
+ true, true, false, true));
+ LRStart = li_->getNextSlot(LRStart);
}
}
bool
SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
MachineInstr *CopyMI) {
- unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
- if (CopyIdx == 0) {
+ LiveIndex CopyIdx = li_->getInstructionIndex(CopyMI);
+ if (CopyIdx == LiveIndex()) {
// FIXME: special case: function live in. It can be a general case if the
// first instruction index starts at > 0 value.
assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
return removeIntervalIfEmpty(li, li_, tri_);
}
- LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
+ LiveInterval::iterator LR =
+ li.FindLiveRangeContaining(li_->getPrevSlot(CopyIdx));
if (LR == li.end())
// Livein but defined by a phi.
return false;
- unsigned RemoveStart = LR->start;
- unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
+ LiveIndex RemoveStart = LR->start;
+ LiveIndex RemoveEnd = li_->getNextSlot(li_->getDefIndex(CopyIdx));
if (LR->end > RemoveEnd)
// More uses past this copy? Nothing to do.
return false;
// If the live range starts in another mbb and the copy mbb is not a fall
// through mbb, then we can only cut the range from the beginning of the
// copy mbb.
- RemoveStart = li_->getMBBStartIdx(CopyMBB) + 1;
+ RemoveStart = li_->getNextSlot(li_->getMBBStartIdx(CopyMBB));
if (LR->valno->def == RemoveStart) {
// If the def MI defines the val# and this copy is the only kill of the
// val#, then propagate the dead marker.
- if (li.isOnlyLROfValNo(LR)) {
- PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
- ++numDeadValNo;
- }
- if (li.isKill(LR->valno, RemoveEnd))
- li.removeKill(LR->valno, RemoveEnd);
+ PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
+ ++numDeadValNo;
+
+ if (LR->valno->isKill(RemoveEnd))
+ LR->valno->removeKill(RemoveEnd);
}
removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
LiveInterval &ImpLi) const{
if (!CopyMI->killsRegister(ImpLi.reg))
return false;
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
- LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
- if (LR == li.end())
- return false;
- if (LR->valno->hasPHIKill())
- return false;
- if (LR->valno->def != CopyIdx)
- return false;
- // Make sure all of val# uses are copies.
- for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
+ // Make sure this is the only use.
+ for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
UE = mri_->use_end(); UI != UE;) {
MachineInstr *UseMI = &*UI;
++UI;
- if (JoinedCopies.count(UseMI))
+ if (CopyMI == UseMI || JoinedCopies.count(UseMI))
continue;
- unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
- LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
- if (ULR == li.end() || ULR->valno != LR->valno)
- continue;
- // If the use is not a use, then it's not safe to coalesce the move.
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
- if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
- UseMI->getOperand(1).getReg() == li.reg)
- continue;
- return false;
- }
+ return false;
}
return true;
}
-/// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
-/// implicit_def and it is being removed. Turn all copies from this value#
-/// into implicit_defs.
-void SimpleRegisterCoalescing::TurnCopiesFromValNoToImpDefs(LiveInterval &li,
- VNInfo *VNI) {
- SmallVector<MachineInstr*, 4> ImpDefs;
- MachineOperand *LastUse = NULL;
- unsigned LastUseIdx = li_->getUseIndex(VNI->def);
- for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
- RE = mri_->reg_end(); RI != RE;) {
- MachineOperand *MO = &RI.getOperand();
- MachineInstr *MI = &*RI;
- ++RI;
- if (MO->isDef()) {
- if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
- ImpDefs.push_back(MI);
- continue;
- }
- if (JoinedCopies.count(MI))
- continue;
- unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
- LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
- if (ULR == li.end() || ULR->valno != VNI)
- continue;
- // If the use is a copy, turn it into an identity copy.
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- SrcReg == li.reg) {
- // Change it to an implicit_def.
- MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
- for (int i = MI->getNumOperands() - 1, e = 0; i > e; --i)
- MI->RemoveOperand(i);
- // It's no longer a copy, update the valno it defines.
- unsigned DefIdx = li_->getDefIndex(UseIdx);
- LiveInterval &DstInt = li_->getInterval(DstReg);
- LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(DefIdx);
- assert(DLR != DstInt.end() && "Live range not found!");
- assert(DLR->valno->copy == MI);
- DLR->valno->copy = NULL;
- ReMatCopies.insert(MI);
- } else if (UseIdx > LastUseIdx) {
- LastUseIdx = UseIdx;
- LastUse = MO;
- }
- }
- if (LastUse) {
- LastUse->setIsKill();
- li.addKill(VNI, LastUseIdx+1, false);
- } else {
- // Remove dead implicit_def's.
- while (!ImpDefs.empty()) {
- MachineInstr *ImpDef = ImpDefs.back();
- ImpDefs.pop_back();
- li_->RemoveMachineInstrFromMaps(ImpDef);
- ImpDef->eraseFromParent();
- }
- }
-}
-
/// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
/// a virtual destination register with physical source register.
bool
// If the virtual register live interval extends into a loop, turn down
// aggressiveness.
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ LiveIndex CopyIdx =
+ li_->getDefIndex(li_->getInstructionIndex(CopyMI));
const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
if (!L) {
// Let's see if the virtual register live interval extends into the loop.
LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
assert(DLR != DstInt.end() && "Live range not found!");
- DLR = DstInt.FindLiveRangeContaining(DLR->end+1);
+ DLR = DstInt.FindLiveRangeContaining(li_->getNextSlot(DLR->end));
if (DLR != DstInt.end()) {
CopyMBB = li_->getMBBFromIndex(DLR->start);
L = loopInfo->getLoopFor(CopyMBB);
if (!L || Length <= Threshold)
return true;
- unsigned UseIdx = li_->getUseIndex(CopyIdx);
+ LiveIndex UseIdx = li_->getUseIndex(CopyIdx);
LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
if (loopInfo->getLoopFor(SMBB) != L) {
if (SuccMBB == CopyMBB)
continue;
if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
- li_->getMBBEndIdx(SuccMBB)+1))
+ li_->getNextSlot(li_->getMBBEndIdx(SuccMBB))))
return false;
}
}
// If the virtual register live interval is defined or cross a loop, turn
// down aggressiveness.
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
- unsigned UseIdx = li_->getUseIndex(CopyIdx);
+ LiveIndex CopyIdx =
+ li_->getDefIndex(li_->getInstructionIndex(CopyMI));
+ LiveIndex UseIdx = li_->getUseIndex(CopyIdx);
LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
assert(SLR != SrcInt.end() && "Live range not found!");
- SLR = SrcInt.FindLiveRangeContaining(SLR->start-1);
+ SLR = SrcInt.FindLiveRangeContaining(li_->getPrevSlot(SLR->start));
if (SLR == SrcInt.end())
return true;
MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
if (PredMBB == SMBB)
continue;
if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
- li_->getMBBEndIdx(PredMBB)+1))
+ li_->getNextSlot(li_->getMBBEndIdx(PredMBB))))
return false;
}
}
LiveInterval &RHS = li_->getInterval(SrcReg);
if (li_->hasInterval(RealDstReg) &&
RHS.overlaps(li_->getInterval(RealDstReg))) {
- DOUT << "Interfere with register ";
- DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_));
+ DEBUG({
+ errs() << "Interfere with register ";
+ li_->getInterval(RealDstReg).print(errs(), tri_);
+ });
return false; // Not coalescable
}
for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
- DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
+ DEBUG({
+ errs() << "Interfere with sub-register ";
+ li_->getInterval(*SR).print(errs(), tri_);
+ });
return false; // Not coalescable
}
return true;
LiveInterval &RHS = li_->getInterval(DstReg);
if (li_->hasInterval(RealSrcReg) &&
RHS.overlaps(li_->getInterval(RealSrcReg))) {
- DOUT << "Interfere with register ";
- DEBUG(li_->getInterval(RealSrcReg).print(DOUT, tri_));
+ DEBUG({
+ errs() << "Interfere with register ";
+ li_->getInterval(RealSrcReg).print(errs(), tri_);
+ });
return false; // Not coalescable
}
for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
- DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
+ DEBUG({
+ errs() << "Interfere with sub-register ";
+ li_->getInterval(*SR).print(errs(), tri_);
+ });
return false; // Not coalescable
}
return true;
if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
return false; // Already done.
- DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
+ DEBUG(errs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
SrcReg = CopyMI->getOperand(1).getReg();
SrcSubIdx = CopyMI->getOperand(2).getImm();
} else if (isInsSubReg || isSubRegToReg) {
- if (CopyMI->getOperand(2).getSubReg()) {
- DOUT << "\tSource of insert_subreg is already coalesced "
- << "to another register.\n";
- return false; // Not coalescable.
- }
DstReg = CopyMI->getOperand(0).getReg();
DstSubIdx = CopyMI->getOperand(3).getImm();
SrcReg = CopyMI->getOperand(2).getReg();
+ SrcSubIdx = CopyMI->getOperand(2).getSubReg();
+ if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
+ // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
+ // coalesced to a larger register so the subreg indices cancel out.
+ DEBUG(errs() << "\tSource of insert_subreg or subreg_to_reg is already "
+ "coalesced to another register.\n");
+ return false; // Not coalescable.
+ }
} else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
llvm_unreachable("Unrecognized copy instruction!");
}
// If they are already joined we continue.
if (SrcReg == DstReg) {
- DOUT << "\tCopy already coalesced.\n";
+ DEBUG(errs() << "\tCopy already coalesced.\n");
return false; // Not coalescable.
}
-
+
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
// If they are both physical registers, we cannot join them.
if (SrcIsPhys && DstIsPhys) {
- DOUT << "\tCan not coalesce physregs.\n";
+ DEBUG(errs() << "\tCan not coalesce physregs.\n");
return false; // Not coalescable.
}
-
+
// We only join virtual registers with allocatable physical registers.
if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
- DOUT << "\tSrc reg is unallocatable physreg.\n";
+ DEBUG(errs() << "\tSrc reg is unallocatable physreg.\n");
return false; // Not coalescable.
}
if (DstIsPhys && !allocatableRegs_[DstReg]) {
- DOUT << "\tDst reg is unallocatable physreg.\n";
+ DEBUG(errs() << "\tDst reg is unallocatable physreg.\n");
return false; // Not coalescable.
}
DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
assert(DstSubRC && "Illegal subregister index");
if (!DstSubRC->contains(SrcSubReg)) {
- DOUT << "\tIncompatible destination regclass: "
- << tri_->getName(SrcSubReg) << " not in " << DstSubRC->getName()
- << ".\n";
+ DEBUG(errs() << "\tIncompatible destination regclass: "
+ << tri_->getName(SrcSubReg) << " not in "
+ << DstSubRC->getName() << ".\n");
return false; // Not coalescable.
}
}
SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
assert(SrcSubRC && "Illegal subregister index");
if (!SrcSubRC->contains(DstReg)) {
- DOUT << "\tIncompatible source regclass: "
- << tri_->getName(DstSubReg) << " not in " << SrcSubRC->getName()
- << ".\n";
+ DEBUG(errs() << "\tIncompatible source regclass: "
+ << tri_->getName(DstSubReg) << " not in "
+ << SrcSubRC->getName() << ".\n");
+ (void)DstSubReg;
return false; // Not coalescable.
}
}
// Should be non-null only when coalescing to a sub-register class.
bool CrossRC = false;
+ const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
+ const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
const TargetRegisterClass *NewRC = NULL;
MachineBasicBlock *CopyMBB = CopyMI->getParent();
unsigned RealDstReg = 0;
// r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
// coalesced to a larger register so the subreg indices cancel out.
if (DstSubIdx != SubIdx) {
- DOUT << "\t Sub-register indices mismatch.\n";
+ DEBUG(errs() << "\t Sub-register indices mismatch.\n");
return false; // Not coalescable.
}
} else
// EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
// coalesced to a larger register so the subreg indices cancel out.
if (SrcSubIdx != SubIdx) {
- DOUT << "\t Sub-register indices mismatch.\n";
+ DEBUG(errs() << "\t Sub-register indices mismatch.\n");
return false; // Not coalescable.
}
} else
} else if ((DstIsPhys && isExtSubReg) ||
(SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
- DOUT << "\tSrc of extract_subreg already coalesced with reg"
- << " of a super-class.\n";
+ DEBUG(errs() << "\tSrc of extract_subreg already coalesced with reg"
+ << " of a super-class.\n");
return false; // Not coalescable.
}
// class as the would be resulting register.
SubIdx = 0;
else {
- DOUT << "\t Sub-register indices mismatch.\n";
+ DEBUG(errs() << "\t Sub-register indices mismatch.\n");
return false; // Not coalescable.
}
}
if (SubIdx) {
+ if (!DstIsPhys && !SrcIsPhys) {
+ if (isInsSubReg || isSubRegToReg) {
+ NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
+ } else // extract_subreg {
+ NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
+ }
+ if (!NewRC) {
+ DEBUG(errs() << "\t Conflicting sub-register indices.\n");
+ return false; // Not coalescable
+ }
+
unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();
}
}
} else if (differingRegisterClasses(SrcReg, DstReg)) {
- if (!CrossClassJoin)
+ if (DisableCrossClassJoin)
return false;
CrossRC = true;
}
}
- const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
- const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
unsigned LargeReg = SrcReg;
unsigned SmallReg = DstReg;
- unsigned Limit = 0;
// Now determine the register class of the joined register.
if (isExtSubReg) {
Again = true;
return false;
}
- Limit = allocatableRCRegs_[DstRC].count();
+ if (!DstIsPhys && !SrcIsPhys)
+ NewRC = SrcRC;
} else if (!SrcIsPhys && !DstIsPhys) {
NewRC = getCommonSubClass(SrcRC, DstRC);
if (!NewRC) {
- DOUT << "\tDisjoint regclasses: "
- << SrcRC->getName() << ", "
- << DstRC->getName() << ".\n";
+ DEBUG(errs() << "\tDisjoint regclasses: "
+ << SrcRC->getName() << ", "
+ << DstRC->getName() << ".\n");
return false; // Not coalescable.
}
if (DstRC->getSize() > SrcRC->getSize())
(isExtSubReg || DstRC->isASubClass()) &&
!isWinToJoinCrossClass(LargeReg, SmallReg,
allocatableRCRegs_[NewRC].count())) {
- DOUT << "\tSrc/Dest are different register classes.\n";
+ DEBUG(errs() << "\tSrc/Dest are different register classes.\n");
// Allow the coalescer to try again in case either side gets coalesced to
// a physical register that's compatible with the other side. e.g.
// r1024 = MOV32to32_ r1025
return false;
if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
return false;
-
+
LiveInterval &SrcInt = li_->getInterval(SrcReg);
LiveInterval &DstInt = li_->getInterval(DstReg);
assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
"Register mapping is horribly broken!");
- DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
- DOUT << " and "; DstInt.print(DOUT, tri_);
- DOUT << ": ";
+ DEBUG({
+ errs() << "\t\tInspecting "; SrcInt.print(errs(), tri_);
+ errs() << " and "; DstInt.print(errs(), tri_);
+ errs() << ": ";
+ });
// Save a copy of the virtual register live interval. We'll manually
// merge this into the "real" physical register live interval this is
if (!isWinToJoinVRWithSrcPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
mri_->setRegAllocationHint(DstInt.reg, 0, SrcReg);
++numAborts;
- DOUT << "\tMay tie down a physical register, abort!\n";
+ DEBUG(errs() << "\tMay tie down a physical register, abort!\n");
Again = true; // May be possible to coalesce later.
return false;
}
if (!isWinToJoinVRWithDstPhysReg(CopyMI, CopyMBB, DstInt, SrcInt)) {
mri_->setRegAllocationHint(SrcInt.reg, 0, DstReg);
++numAborts;
- DOUT << "\tMay tie down a physical register, abort!\n";
+ DEBUG(errs() << "\tMay tie down a physical register, abort!\n");
Again = true; // May be possible to coalesce later.
return false;
}
unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
- if (TheCopy.isBackEdge)
- Threshold *= 2; // Favors back edge copies.
-
unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
float Ratio = 1.0 / Threshold;
if (Length > Threshold &&
mri_->use_end()) / Length) < Ratio)) {
mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
++numAborts;
- DOUT << "\tMay tie down a physical register, abort!\n";
+ DEBUG(errs() << "\tMay tie down a physical register, abort!\n");
Again = true; // May be possible to coalesce later.
return false;
}
// Only coalesce an empty interval (defined by implicit_def) with
// another interval which has a valno defined by the CopyMI and the CopyMI
// is a kill of the implicit def.
- DOUT << "Not profitable!\n";
+ DEBUG(errs() << "Not profitable!\n");
return false;
}
// If definition of source is defined by trivial computation, try
// rematerializing it.
if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
- ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
+ ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
return true;
-
+
// If we can eliminate the copy without merging the live ranges, do so now.
if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
(AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
JoinedCopies.insert(CopyMI);
return true;
}
-
+
// Otherwise, we are unable to join the intervals.
- DOUT << "Interference!\n";
+ DEBUG(errs() << "Interference!\n");
Again = true; // May be possible to coalesce later.
return false;
}
}
assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"LiveInterval::join didn't work right!");
-
+
// If we're about to merge live ranges into a physical register live interval,
// we have to update any aliased register's live ranges to indicate that they
// have clobbered values for this range.
for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
E = SavedLI->vni_end(); I != E; ++I) {
const VNInfo *ValNo = *I;
- VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->copy,
+ VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(),
false, // updated at *
li_->getVNInfoAllocator());
NewValNo->setFlags(ValNo->getFlags()); // * updated here.
RealInt.addKills(NewValNo, ValNo->kills);
RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
}
- RealInt.weight += SavedLI->weight;
+ RealInt.weight += SavedLI->weight;
DstReg = RealDstReg ? RealDstReg : RealSrcReg;
}
// Coalescing to a virtual register that is of a sub-register class of the
// other. Make sure the resulting register is set to the right register class.
- if (CrossRC) {
- ++numCrossRCs;
- if (NewRC)
- mri_->setRegClass(DstReg, NewRC);
- }
-
- if (NewHeuristic) {
- // Add all copies that define val# in the source interval into the queue.
- for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
- e = ResSrcInt->vni_end(); i != e; ++i) {
- const VNInfo *vni = *i;
- // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
- if (!vni->def || vni->isUnused() || vni->isPHIDef() || !vni->isDefAccurate())
- continue;
- MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
- unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
- if (CopyMI &&
- JoinedCopies.count(CopyMI) == 0 &&
- tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
- NewSrcSubIdx, NewDstSubIdx)) {
- unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
- JoinQueue->push(CopyRec(CopyMI, LoopDepth,
- isBackEdgeCopy(CopyMI, DstReg)));
- }
- }
- }
+ if (CrossRC)
+ ++numCrossRCs;
+
+ // This may happen even if it's cross-rc coalescing. e.g.
+ // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
+ // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
+ // be allocate a register from GR64_ABCD.
+ if (NewRC)
+ mri_->setRegClass(DstReg, NewRC);
// Remember to delete the copy instruction.
JoinedCopies.insert(CopyMI);
if (TargetRegisterInfo::isVirtualRegister(DstReg))
RemoveUnnecessaryKills(DstReg, *ResDstInt);
- if (isInsSubReg)
- // Avoid:
- // r1024 = op
- // r1024 = implicit_def
- // ...
- // = r1024
- RemoveDeadImpDef(DstReg, *ResDstInt);
UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
// SrcReg is guarateed to be the register whose live interval that is
delete SavedLI;
}
- if (isEmpty) {
- // Now the copy is being coalesced away, the val# previously defined
- // by the copy is being defined by an IMPLICIT_DEF which defines a zero
- // length interval. Remove the val#.
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
- const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
- VNInfo *ImpVal = LR->valno;
- assert(ImpVal->def == CopyIdx);
- unsigned NextDef = LR->end;
- TurnCopiesFromValNoToImpDefs(*ResDstInt, ImpVal);
- ResDstInt->removeValNo(ImpVal);
- LR = ResDstInt->FindLiveRangeContaining(NextDef);
- if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
- // Special case: vr1024 = implicit_def
- // vr1024 = insert_subreg vr1024, vr1025, c
- // The insert_subreg becomes a "copy" that defines a val# which can itself
- // be coalesced away.
- MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
- if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
- LR->valno->copy = DefMI;
- }
- }
-
// If resulting interval has a preference that no longer fits because of subreg
// coalescing, just clear the preference.
unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
}
- DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
- DOUT << "\n";
+ DEBUG({
+ errs() << "\n\t\tJoined. Result = ";
+ ResDstInt->print(errs(), tri_);
+ errs() << "\n";
+ });
++numJoins;
return true;
// been computed, return it.
if (OtherValNoAssignments[OtherValNo->id] >= 0)
return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
-
+
// Mark this value number as currently being computed, then ask what the
// ultimate value # of the other value is.
ThisValNoAssignments[VN] = -2;
DstReg == li.reg && SrcReg == Reg) {
// Cache computed info.
LR->valno->def = LR->start;
- LR->valno->copy = DefMI;
+ LR->valno->setCopy(DefMI);
return true;
}
}
/// joins them and returns true.
bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
assert(RHS.containsOneValue());
-
+
// Some number (potentially more than one) value numbers in the current
// interval may be defined as copies from the RHS. Scan the overlapping
// portions of the LHS and RHS, keeping track of this and looking for
// overlapping live ranges that are NOT defined as copies. If these exist, we
// cannot coalesce.
-
+
LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
-
+
if (LHSIt->start < RHSIt->start) {
LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
if (LHSIt != LHS.begin()) --LHSIt;
RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
if (RHSIt != RHS.begin()) --RHSIt;
}
-
+
SmallVector<VNInfo*, 8> EliminatedLHSVals;
-
+
while (1) {
// Determine if these live intervals overlap.
bool Overlaps = false;
Overlaps = LHSIt->end > RHSIt->start;
else
Overlaps = RHSIt->end > LHSIt->start;
-
+
// If the live intervals overlap, there are two interesting cases: if the
// LHS interval is defined by a copy from the RHS, it's ok and we record
// that the LHS value # is the same as the RHS. If it's not, then we cannot
// vr1025 = copy vr1024
// ..
// BB2:
- // vr1024 = op
+ // vr1024 = op
// = vr1025
// Even though vr1025 is copied from vr1024, it's not safe to
// coalesce them since the live range of vr1025 intersects the
return false;
EliminatedLHSVals.push_back(LHSIt->valno);
}
-
+
// We know this entire LHS live range is okay, so skip it now.
if (++LHSIt == LHSEnd) break;
continue;
}
-
+
if (LHSIt->end < RHSIt->end) {
if (++LHSIt == LHSEnd) break;
} else {
// vr1025 = copy vr1024
// ..
// BB2:
- // vr1024 = op
+ // vr1024 = op
// = vr1025
// Even though vr1025 is copied from vr1024, it's not safe to
// coalesced them since live range of vr1025 intersects the
}
}
}
-
+
if (++RHSIt == RHSEnd) break;
}
}
-
+
// If we got here, we know that the coalescing will be successful and that
// the value numbers in EliminatedLHSVals will all be merged together. Since
// the most common case is that EliminatedLHSVals has a single number, we
} else {
LHSValNo = EliminatedLHSVals[0];
}
-
+
// Okay, now that there is a single LHS value number that we're merging the
// RHS into, update the value number info for the LHS to indicate that the
// value number is defined where the RHS value number was.
const VNInfo *VNI = RHS.getValNumInfo(0);
LHSValNo->def = VNI->def;
- LHSValNo->copy = VNI->copy;
-
+ LHSValNo->setCopy(VNI->getCopy());
+
// Okay, the final step is to loop over the RHS live intervals, adding them to
// the LHS.
if (VNI->hasPHIKill())
LHSValNo->setHasPHIKill(true);
LHS.addKills(LHSValNo, VNI->kills);
LHS.MergeRangesInAsValue(RHS, LHSValNo);
- LHS.weight += RHS.weight;
+
+ LHS.ComputeJoinedWeight(RHS);
// Update regalloc hint if both are virtual registers.
- if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
+ if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
} else {
for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
- DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
+ DEBUG({
+ errs() << "Interfere with sub-register ";
+ li_->getInterval(*SR).print(errs(), tri_);
+ });
return false;
}
}
} else {
for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
- DOUT << "Interfere with sub-register ";
- DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
+ DEBUG({
+ errs() << "Interfere with sub-register ";
+ li_->getInterval(*SR).print(errs(), tri_);
+ });
return false;
}
}
}
-
+
// Compute ultimate value numbers for the LHS and RHS values.
if (RHS.containsOneValue()) {
// Copies from a liveinterval with a single value are simple to handle and
// very common, handle the special case here. This is important, because
// often RHS is small and LHS is large (e.g. a physreg).
-
+
// Find out if the RHS is defined as a copy from some value in the LHS.
int RHSVal0DefinedFromLHS = -1;
int RHSValID = -1;
}
} else {
// It was defined as a copy from the LHS, find out what value # it is.
- RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
+ RHSValNoInfo =
+ LHS.getLiveRangeContaining(li_->getPrevSlot(RHSValNoInfo0->def))->valno;
RHSValID = RHSValNoInfo->id;
RHSVal0DefinedFromLHS = RHSValID;
}
-
+
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
NewVNInfo.resize(LHS.getNumValNums(), NULL);
-
+
// Okay, *all* of the values in LHS that are defined as a copy from RHS
// should now get updated.
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
LHSValNoAssignments[VN] = VN;
}
}
-
+
assert(RHSValID != -1 && "Didn't find value #?");
RHSValNoAssignments[0] = RHSValID;
if (RHSVal0DefinedFromLHS != -1) {
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
i != e; ++i) {
VNInfo *VNI = *i;
- if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
+ if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
continue;
-
+
// DstReg is known to be a register in the LHS interval. If the src is
// from the RHS interval, we can use its value #.
if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
continue;
-
+
// Figure out the value # from the RHS.
- LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
+ LHSValsDefinedFromRHS[VNI]=
+ RHS.getLiveRangeContaining(li_->getPrevSlot(VNI->def))->valno;
}
-
+
// Loop over the value numbers of the RHS, seeing if any are defined from
// the LHS.
for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
i != e; ++i) {
VNInfo *VNI = *i;
- if (VNI->isUnused() || VNI->copy == 0) // Src not defined by a copy?
+ if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
continue;
-
+
// DstReg is known to be a register in the RHS interval. If the src is
// from the LHS interval, we can use its value #.
if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
continue;
-
+
// Figure out the value # from the LHS.
- RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
+ RHSValsDefinedFromLHS[VNI]=
+ LHS.getLiveRangeContaining(li_->getPrevSlot(VNI->def))->valno;
}
-
+
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
-
+
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
i != e; ++i) {
VNInfo *VNI = *i;
unsigned VN = VNI->id;
- if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
+ if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
continue;
ComputeUltimateVN(VNI, NewVNInfo,
LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
RHSValNoAssignments[VN] = NewVNInfo.size()-1;
continue;
}
-
+
ComputeUltimateVN(VNI, NewVNInfo,
RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
RHSValNoAssignments, LHSValNoAssignments);
}
}
-
+
// Armed with the mappings of LHS/RHS values to ultimate values, walk the
// interval lists to see if these intervals are coalescable.
LiveInterval::const_iterator I = LHS.begin();
LiveInterval::const_iterator IE = LHS.end();
LiveInterval::const_iterator J = RHS.begin();
LiveInterval::const_iterator JE = RHS.end();
-
+
// Skip ahead until the first place of potential sharing.
if (I->start < J->start) {
I = std::upper_bound(I, IE, J->start);
J = std::upper_bound(J, JE, I->start);
if (J != RHS.begin()) --J;
}
-
+
while (1) {
// Determine if these two live ranges overlap.
bool Overlaps;
RHSValNoAssignments[J->valno->id])
return false;
}
-
+
if (I->end < J->end) {
++I;
if (I == IE) break;
E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
VNInfo *VNI = I->first;
unsigned LHSValID = LHSValNoAssignments[VNI->id];
- LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
+ NewVNInfo[LHSValID]->removeKill(VNI->def);
if (VNI->hasPHIKill())
NewVNInfo[LHSValID]->setHasPHIKill(true);
RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
VNInfo *VNI = I->first;
unsigned RHSValID = RHSValNoAssignments[VNI->id];
- LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
+ NewVNInfo[RHSValID]->removeKill(VNI->def);
if (VNI->hasPHIKill())
NewVNInfo[RHSValID]->setHasPHIKill(true);
LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
};
}
-/// getRepIntervalSize - Returns the size of the interval that represents the
-/// specified register.
-template<class SF>
-unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
- return Rc->getRepIntervalSize(Reg);
-}
-
-/// CopyRecSort::operator - Join priority queue sorting function.
-///
-bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
- // Inner loops first.
- if (left.LoopDepth > right.LoopDepth)
- return false;
- else if (left.LoopDepth == right.LoopDepth)
- if (left.isBackEdge && !right.isBackEdge)
- return false;
- return true;
-}
-
void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
std::vector<CopyRec> &TryAgain) {
- DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
+ DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
std::vector<CopyRec> VirtCopies;
std::vector<CopyRec> PhysCopies;
std::vector<CopyRec> ImpDefCopies;
- unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
MII != E;) {
MachineInstr *Inst = MII++;
-
+
// If this isn't a copy nor a extract_subreg, we can't join intervals.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
- if (NewHeuristic) {
- JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
- } else {
- if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
- ImpDefCopies.push_back(CopyRec(Inst, 0, false));
- else if (SrcIsPhys || DstIsPhys)
- PhysCopies.push_back(CopyRec(Inst, 0, false));
- else
- VirtCopies.push_back(CopyRec(Inst, 0, false));
- }
+ if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
+ ImpDefCopies.push_back(CopyRec(Inst, 0));
+ else if (SrcIsPhys || DstIsPhys)
+ PhysCopies.push_back(CopyRec(Inst, 0));
+ else
+ VirtCopies.push_back(CopyRec(Inst, 0));
}
- if (NewHeuristic)
- return;
-
// Try coalescing implicit copies first, followed by copies to / from
// physical registers, then finally copies from virtual registers to
// virtual registers.
}
void SimpleRegisterCoalescing::joinIntervals() {
- DOUT << "********** JOINING INTERVALS ***********\n";
-
- if (NewHeuristic)
- JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
+ DEBUG(errs() << "********** JOINING INTERVALS ***********\n");
std::vector<CopyRec> TryAgainList;
if (loopInfo->empty()) {
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
}
-
+
// Joining intervals can allow other intervals to be joined. Iteratively join
// until we make no progress.
- if (NewHeuristic) {
- SmallVector<CopyRec, 16> TryAgain;
- bool ProgressMade = true;
- while (ProgressMade) {
- ProgressMade = false;
- while (!JoinQueue->empty()) {
- CopyRec R = JoinQueue->pop();
- bool Again = false;
- bool Success = JoinCopy(R, Again);
- if (Success)
- ProgressMade = true;
- else if (Again)
- TryAgain.push_back(R);
- }
+ bool ProgressMade = true;
+ while (ProgressMade) {
+ ProgressMade = false;
- if (ProgressMade) {
- while (!TryAgain.empty()) {
- JoinQueue->push(TryAgain.back());
- TryAgain.pop_back();
- }
- }
- }
- } else {
- bool ProgressMade = true;
- while (ProgressMade) {
- ProgressMade = false;
-
- for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
- CopyRec &TheCopy = TryAgainList[i];
- if (TheCopy.MI) {
- bool Again = false;
- bool Success = JoinCopy(TheCopy, Again);
- if (Success || !Again) {
- TheCopy.MI = 0; // Mark this one as done.
- ProgressMade = true;
- }
- }
+ for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
+ CopyRec &TheCopy = TryAgainList[i];
+ if (!TheCopy.MI)
+ continue;
+
+ bool Again = false;
+ bool Success = JoinCopy(TheCopy, Again);
+ if (Success || !Again) {
+ TheCopy.MI = 0; // Mark this one as done.
+ ProgressMade = true;
}
}
}
-
- if (NewHeuristic)
- delete JoinQueue;
}
/// Return true if the two specified registers belong to different register
/// lastRegisterUse - Returns the last use of the specific register between
/// cycles Start and End or NULL if there are no uses.
MachineOperand *
-SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
- unsigned Reg, unsigned &UseIdx) const{
- UseIdx = 0;
+SimpleRegisterCoalescing::lastRegisterUse(LiveIndex Start,
+ LiveIndex End,
+ unsigned Reg,
+ LiveIndex &UseIdx) const{
+ UseIdx = LiveIndex();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
MachineOperand *LastUse = NULL;
for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
SrcReg == DstReg)
// Ignore identity copies.
continue;
- unsigned Idx = li_->getInstructionIndex(UseMI);
+ LiveIndex Idx = li_->getInstructionIndex(UseMI);
if (Idx >= Start && Idx < End && Idx >= UseIdx) {
LastUse = &Use;
UseIdx = li_->getUseIndex(Idx);
return LastUse;
}
- int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
- int s = Start;
+ LiveIndex s = Start;
+ LiveIndex e = li_->getBaseIndex(li_->getPrevSlot(End));
while (e >= s) {
// Skip deleted instructions
MachineInstr *MI = li_->getInstructionFromIndex(e);
- while ((e - InstrSlots::NUM) >= s && !MI) {
- e -= InstrSlots::NUM;
+ while (e != LiveIndex() && li_->getPrevIndex(e) >= s && !MI) {
+ e = li_->getPrevIndex(e);
MI = li_->getInstructionFromIndex(e);
}
if (e < s || MI == NULL)
}
}
- e -= InstrSlots::NUM;
+ e = li_->getPrevIndex(e);
}
return NULL;
void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
if (TargetRegisterInfo::isPhysicalRegister(reg))
- cerr << tri_->getName(reg);
+ errs() << tri_->getName(reg);
else
- cerr << "%reg" << reg;
+ errs() << "%reg" << reg;
}
void SimpleRegisterCoalescing::releaseMemory() {
ReMatDefs.clear();
}
-static bool isZeroLengthInterval(LiveInterval *li) {
+/// Returns true if the given live interval is zero length.
+static bool isZeroLengthInterval(LiveInterval *li, LiveIntervals *li_) {
for (LiveInterval::Ranges::const_iterator
i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
- if (i->end - i->start > LiveInterval::InstrSlots::NUM)
+ if (li_->getPrevIndex(i->end) > i->start)
return false;
return true;
}
-/// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
-/// turn the copy into an implicit def.
-bool
-SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
- MachineBasicBlock *MBB,
- unsigned DstReg, unsigned SrcReg) {
- MachineInstr *CopyMI = &*I;
- unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
- if (!li_->hasInterval(SrcReg))
- return false;
- LiveInterval &SrcInt = li_->getInterval(SrcReg);
- if (!SrcInt.empty())
- return false;
- if (!li_->hasInterval(DstReg))
- return false;
- LiveInterval &DstInt = li_->getInterval(DstReg);
- const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
- // If the valno extends beyond this basic block, then it's not safe to delete
- // the val# or else livein information won't be correct.
- MachineBasicBlock *EndMBB = li_->getMBBFromIndex(DstLR->end);
- if (EndMBB != MBB)
- return false;
- DstInt.removeValNo(DstLR->valno);
- CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
- for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
- CopyMI->RemoveOperand(i);
- CopyMI->getOperand(0).setIsUndef();
- bool NoUse = mri_->use_empty(SrcReg);
- if (NoUse) {
- for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
- RE = mri_->reg_end(); RI != RE; ) {
- assert(RI.getOperand().isDef());
- MachineInstr *DefMI = &*RI;
- ++RI;
- // The implicit_def source has no other uses, delete it.
- assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
- li_->RemoveMachineInstrFromMaps(DefMI);
- DefMI->eraseFromParent();
+
+void SimpleRegisterCoalescing::CalculateSpillWeights() {
+ SmallSet<unsigned, 4> Processed;
+ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
+ mbbi != mbbe; ++mbbi) {
+ MachineBasicBlock* MBB = mbbi;
+ LiveIndex MBBEnd = li_->getMBBEndIdx(MBB);
+ MachineLoop* loop = loopInfo->getLoopFor(MBB);
+ unsigned loopDepth = loop ? loop->getLoopDepth() : 0;
+ bool isExit = loop ? loop->isLoopExit(MBB) : false;
+
+ for (MachineBasicBlock::const_iterator mii = MBB->begin(), mie = MBB->end();
+ mii != mie; ++mii) {
+ const MachineInstr *MI = mii;
+ if (tii_->isIdentityCopy(*MI))
+ continue;
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &mopi = MI->getOperand(i);
+ if (!mopi.isReg() || mopi.getReg() == 0)
+ continue;
+ unsigned Reg = mopi.getReg();
+ if (!TargetRegisterInfo::isVirtualRegister(mopi.getReg()))
+ continue;
+ // Multiple uses of reg by the same instruction. It should not
+ // contribute to spill weight again.
+ if (!Processed.insert(Reg))
+ continue;
+
+ bool HasDef = mopi.isDef();
+ bool HasUse = !HasDef;
+ for (unsigned j = i+1; j != e; ++j) {
+ const MachineOperand &mopj = MI->getOperand(j);
+ if (!mopj.isReg() || mopj.getReg() != Reg)
+ continue;
+ HasDef |= mopj.isDef();
+ HasUse |= mopj.isUse();
+ if (HasDef && HasUse)
+ break;
+ }
+
+ LiveInterval &RegInt = li_->getInterval(Reg);
+ float Weight = li_->getSpillWeight(HasDef, HasUse, loopDepth);
+ if (HasDef && isExit) {
+ // Looks like this is a loop count variable update.
+ LiveIndex DefIdx =
+ li_->getDefIndex(li_->getInstructionIndex(MI));
+ const LiveRange *DLR =
+ li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
+ if (DLR->end > MBBEnd)
+ Weight *= 3.0F;
+ }
+ RegInt.weight += Weight;
+ }
+ Processed.clear();
}
}
- // Mark uses of implicit_def isUndef.
- for (MachineRegisterInfo::use_iterator RI = mri_->use_begin(DstReg),
- RE = mri_->use_end(); RI != RE; ++RI) {
- assert((*RI).getParent() == MBB);
- RI.getOperand().setIsUndef();
- }
+ for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
+ LiveInterval &LI = *I->second;
+ if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
+ // If the live interval length is essentially zero, i.e. in every live
+ // range the use follows def immediately, it doesn't make sense to spill
+ // it and hope it will be easier to allocate for this li.
+ if (isZeroLengthInterval(&LI, li_)) {
+ LI.weight = HUGE_VALF;
+ continue;
+ }
- ++I;
- return true;
+ bool isLoad = false;
+ SmallVector<LiveInterval*, 4> SpillIs;
+ if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
+ // If all of the definitions of the interval are re-materializable,
+ // it is a preferred candidate for spilling. If non of the defs are
+ // loads, then it's potentially very cheap to re-materialize.
+ // FIXME: this gets much more complicated once we support non-trivial
+ // re-materialization.
+ if (isLoad)
+ LI.weight *= 0.9F;
+ else
+ LI.weight *= 0.5F;
+ }
+
+ // Slightly prefer live interval that has been assigned a preferred reg.
+ std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
+ if (Hint.first || Hint.second)
+ LI.weight *= 1.01F;
+
+ // Divide the weight of the interval by its size. This encourages
+ // spilling of intervals that are large and have few uses, and
+ // discourages spilling of small intervals with many uses.
+ LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
+ }
+ }
}
tri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
li_ = &getAnalysis<LiveIntervals>();
+ AA = &getAnalysis<AliasAnalysis>();
loopInfo = &getAnalysis<MachineLoopInfo>();
- DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
- << "********** Function: "
- << ((Value*)mf_->getFunction())->getName() << '\n';
+ DEBUG(errs() << "********** SIMPLE REGISTER COALESCING **********\n"
+ << "********** Function: "
+ << ((Value*)mf_->getFunction())->getName() << '\n');
allocatableRegs_ = tri_->getAllocatableSet(fn);
for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
if (EnableJoining) {
joinIntervals();
DEBUG({
- DOUT << "********** INTERVALS POST JOINING **********\n";
+ errs() << "********** INTERVALS POST JOINING **********\n";
for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
- I->second->print(DOUT, tri_);
- DOUT << "\n";
+ I->second->print(errs(), tri_);
+ errs() << "\n";
}
});
}
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) {
MachineBasicBlock* mbb = mbbi;
- unsigned loopDepth = loopInfo->getLoopDepth(mbb);
-
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
mii != mie; ) {
MachineInstr *MI = mii;
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (JoinedCopies.count(MI)) {
// Delete all coalesced copies.
+ bool DoDelete = true;
if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
"Unrecognized copy instruction");
DstReg = MI->getOperand(0).getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg))
+ // Do not delete extract_subreg, insert_subreg of physical
+ // registers unless the definition is dead. e.g.
+ // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
+ // or else the scavenger may complain. LowerSubregs will
+ // change this to an IMPLICIT_DEF later.
+ DoDelete = false;
}
if (MI->registerDefIsDead(DstReg)) {
LiveInterval &li = li_->getInterval(DstReg);
if (!ShortenDeadCopySrcLiveRange(li, MI))
ShortenDeadCopyLiveRange(li, MI);
+ DoDelete = true;
+ }
+ if (!DoDelete)
+ mii = next(mii);
+ else {
+ li_->RemoveMachineInstrFromMaps(MI);
+ mii = mbbi->erase(mii);
+ ++numPeep;
}
- li_->RemoveMachineInstrFromMaps(MI);
- mii = mbbi->erase(mii);
- ++numPeep;
continue;
}
li_->RemoveMachineInstrFromMaps(MI);
mii = mbbi->erase(mii);
++numPeep;
- } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
- SmallSet<unsigned, 4> UniqueUses;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &mop = MI->getOperand(i);
- if (mop.isReg() && mop.getReg() &&
- TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
- unsigned reg = mop.getReg();
- // Multiple uses of reg by the same instruction. It should not
- // contribute to spill weight again.
- if (UniqueUses.count(reg) != 0)
- continue;
- LiveInterval &RegInt = li_->getInterval(reg);
- RegInt.weight +=
- li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
- UniqueUses.insert(reg);
- }
- }
+ } else {
++mii;
}
}
}
- for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
- LiveInterval &LI = *I->second;
- if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
- // If the live interval length is essentially zero, i.e. in every live
- // range the use follows def immediately, it doesn't make sense to spill
- // it and hope it will be easier to allocate for this li.
- if (isZeroLengthInterval(&LI))
- LI.weight = HUGE_VALF;
- else {
- bool isLoad = false;
- SmallVector<LiveInterval*, 4> SpillIs;
- if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
- // If all of the definitions of the interval are re-materializable,
- // it is a preferred candidate for spilling. If non of the defs are
- // loads, then it's potentially very cheap to re-materialize.
- // FIXME: this gets much more complicated once we support non-trivial
- // re-materialization.
- if (isLoad)
- LI.weight *= 0.9F;
- else
- LI.weight *= 0.5F;
- }
- }
-
- // Slightly prefer live interval that has been assigned a preferred reg.
- std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(LI.reg);
- if (Hint.first || Hint.second)
- LI.weight *= 1.01F;
-
- // Divide the weight of the interval by its size. This encourages
- // spilling of intervals that are large and have few uses, and
- // discourages spilling of small intervals with many uses.
- LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
- }
- }
+ CalculateSpillWeights();
DEBUG(dump());
return true;
}
/// print - Implement the dump method.
-void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
+void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
li_->print(O, m);
}
projects / oota-llvm.git / blobdiff