/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
/// PHI nodes or outside of the basic block that defines it, or used by a
-/// switch instruction, which may expand to multiple basic blocks.
+/// switch or atomic instruction, which may expand to multiple basic blocks.
static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
if (isa<PHINode>(I)) return true;
BasicBlock *BB = I->getParent();
void visitMemIntrinsic(CallInst &I, unsigned Op);
+ void visitGetResult(GetResultInst &I) {
+ assert (0 && "getresult unimplemented");
+ }
+
void visitUserOp1(Instruction &I) {
assert(0 && "UserOp1 should not exist at instruction selection time!");
abort();
MVT::ValueType ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE,
bool TruncExact = false) {
- if (!MVT::isVector(ValueVT) || NumParts == 1) {
- SDOperand Val = Parts[0];
-
- // If the value was expanded, copy from the top part.
- if (NumParts > 1) {
- assert(NumParts == 2 &&
- "Cannot expand to more than 2 elts yet!");
- SDOperand Hi = Parts[1];
- if (!DAG.getTargetLoweringInfo().isLittleEndian())
- std::swap(Val, Hi);
- return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
- }
-
- // Otherwise, if the value was promoted or extended, truncate it to the
- // appropriate type.
- if (PartVT == ValueVT)
- return Val;
-
- if (MVT::isVector(PartVT)) {
- assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
- return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
- }
-
- if (MVT::isVector(ValueVT)) {
- assert(NumParts == 1 &&
- MVT::getVectorElementType(ValueVT) == PartVT &&
- MVT::getVectorNumElements(ValueVT) == 1 &&
- "Only trivial scalar-to-vector conversions should get here!");
- return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
- }
-
- if (MVT::isInteger(PartVT) &&
- MVT::isInteger(ValueVT)) {
- if (ValueVT < PartVT) {
- // For a truncate, see if we have any information to
- // indicate whether the truncated bits will always be
- // zero or sign-extension.
- if (AssertOp != ISD::DELETED_NODE)
- Val = DAG.getNode(AssertOp, PartVT, Val,
- DAG.getValueType(ValueVT));
- return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+ assert(NumParts > 0 && "No parts to assemble!");
+ TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ SDOperand Val = Parts[0];
+
+ if (NumParts > 1) {
+ // Assemble the value from multiple parts.
+ if (!MVT::isVector(ValueVT)) {
+ unsigned PartBits = MVT::getSizeInBits(PartVT);
+ unsigned ValueBits = MVT::getSizeInBits(ValueVT);
+
+ // Assemble the power of 2 part.
+ unsigned RoundParts = NumParts & (NumParts - 1) ?
+ 1 << Log2_32(NumParts) : NumParts;
+ unsigned RoundBits = PartBits * RoundParts;
+ MVT::ValueType RoundVT = RoundBits == ValueBits ?
+ ValueVT : MVT::getIntegerType(RoundBits);
+ SDOperand Lo, Hi;
+
+ if (RoundParts > 2) {
+ MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
+ Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
+ Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
+ PartVT, HalfVT);
} else {
- return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
+ Lo = Parts[0];
+ Hi = Parts[1];
+ }
+ if (TLI.isBigEndian())
+ std::swap(Lo, Hi);
+ Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
+
+ if (RoundParts < NumParts) {
+ // Assemble the trailing non-power-of-2 part.
+ unsigned OddParts = NumParts - RoundParts;
+ MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
+ Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
+
+ // Combine the round and odd parts.
+ Lo = Val;
+ if (TLI.isBigEndian())
+ std::swap(Lo, Hi);
+ MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
+ Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
+ Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
+ DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
+ TLI.getShiftAmountTy()));
+ Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
+ Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
}
+ } else {
+ // Handle a multi-element vector.
+ MVT::ValueType IntermediateVT, RegisterVT;
+ unsigned NumIntermediates;
+ unsigned NumRegs =
+ TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
+ RegisterVT);
+
+ assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
+ assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
+ assert(RegisterVT == Parts[0].getValueType() &&
+ "Part type doesn't match part!");
+
+ // Assemble the parts into intermediate operands.
+ SmallVector<SDOperand, 8> Ops(NumIntermediates);
+ if (NumIntermediates == NumParts) {
+ // If the register was not expanded, truncate or copy the value,
+ // as appropriate.
+ for (unsigned i = 0; i != NumParts; ++i)
+ Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
+ PartVT, IntermediateVT);
+ } else if (NumParts > 0) {
+ // If the intermediate type was expanded, build the intermediate operands
+ // from the parts.
+ assert(NumParts % NumIntermediates == 0 &&
+ "Must expand into a divisible number of parts!");
+ unsigned Factor = NumParts / NumIntermediates;
+ for (unsigned i = 0; i != NumIntermediates; ++i)
+ Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
+ PartVT, IntermediateVT);
+ }
+
+ // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
+ // operands.
+ Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
+ ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
+ ValueVT, &Ops[0], NumIntermediates);
}
-
- if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
- return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
- DAG.getIntPtrConstant(TruncExact));
+ }
- if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
- return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
+ // There is now one part, held in Val. Correct it to match ValueVT.
+ PartVT = Val.getValueType();
- assert(0 && "Unknown mismatch!");
- }
+ if (PartVT == ValueVT)
+ return Val;
- // Handle a multi-element vector.
- MVT::ValueType IntermediateVT, RegisterVT;
- unsigned NumIntermediates;
- unsigned NumRegs =
- DAG.getTargetLoweringInfo()
- .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
- RegisterVT);
+ if (MVT::isVector(PartVT)) {
+ assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
+ return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
+ }
- assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
- assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
- assert(RegisterVT == Parts[0].getValueType() &&
- "Part type doesn't match part!");
+ if (MVT::isVector(ValueVT)) {
+ assert(MVT::getVectorElementType(ValueVT) == PartVT &&
+ MVT::getVectorNumElements(ValueVT) == 1 &&
+ "Only trivial scalar-to-vector conversions should get here!");
+ return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
+ }
- // Assemble the parts into intermediate operands.
- SmallVector<SDOperand, 8> Ops(NumIntermediates);
- if (NumIntermediates == NumParts) {
- // If the register was not expanded, truncate or copy the value,
- // as appropriate.
- for (unsigned i = 0; i != NumParts; ++i)
- Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
- PartVT, IntermediateVT);
- } else if (NumParts > 0) {
- // If the intermediate type was expanded, build the intermediate operands
- // from the parts.
- assert(NumParts % NumIntermediates == 0 &&
- "Must expand into a divisible number of parts!");
- unsigned Factor = NumParts / NumIntermediates;
- for (unsigned i = 0; i != NumIntermediates; ++i)
- Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
- PartVT, IntermediateVT);
+ if (MVT::isInteger(PartVT) &&
+ MVT::isInteger(ValueVT)) {
+ if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
+ // For a truncate, see if we have any information to
+ // indicate whether the truncated bits will always be
+ // zero or sign-extension.
+ if (AssertOp != ISD::DELETED_NODE)
+ Val = DAG.getNode(AssertOp, PartVT, Val,
+ DAG.getValueType(ValueVT));
+ return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+ } else {
+ return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
+ }
}
-
- // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
- // operands.
- return DAG.getNode(MVT::isVector(IntermediateVT) ?
- ISD::CONCAT_VECTORS :
- ISD::BUILD_VECTOR,
- ValueVT, &Ops[0], NumIntermediates);
+
+ if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
+ return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
+ DAG.getIntPtrConstant(TruncExact));
+
+ if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
+ return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
+
+ assert(0 && "Unknown mismatch!");
}
/// getCopyToParts - Create a series of nodes that contain the specified value
TargetLowering &TLI = DAG.getTargetLoweringInfo();
MVT::ValueType PtrVT = TLI.getPointerTy();
MVT::ValueType ValueVT = Val.getValueType();
+ unsigned PartBits = MVT::getSizeInBits(PartVT);
+ assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
+
+ if (!NumParts)
+ return;
- if (!MVT::isVector(ValueVT) || NumParts == 1) {
- // If the value was expanded, copy from the parts.
- if (NumParts > 1) {
- for (unsigned i = 0; i != NumParts; ++i)
- Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
- DAG.getConstant(i, PtrVT));
- if (!DAG.getTargetLoweringInfo().isLittleEndian())
- std::reverse(Parts, Parts + NumParts);
+ if (!MVT::isVector(ValueVT)) {
+ if (PartVT == ValueVT) {
+ assert(NumParts == 1 && "No-op copy with multiple parts!");
+ Parts[0] = Val;
return;
}
- // If there is a single part and the types differ, this must be
- // a promotion.
+ if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
+ // If the parts cover more bits than the value has, promote the value.
+ if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
+ assert(NumParts == 1 && "Do not know what to promote to!");
+ Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
+ } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
+ ValueVT = MVT::getIntegerType(NumParts * PartBits);
+ Val = DAG.getNode(ExtendKind, ValueVT, Val);
+ } else {
+ assert(0 && "Unknown mismatch!");
+ }
+ } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
+ // Different types of the same size.
+ assert(NumParts == 1 && PartVT != ValueVT);
+ Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
+ } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
+ // If the parts cover less bits than value has, truncate the value.
+ if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
+ ValueVT = MVT::getIntegerType(NumParts * PartBits);
+ Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+ } else {
+ assert(0 && "Unknown mismatch!");
+ }
+ }
+
+ // The value may have changed - recompute ValueVT.
+ ValueVT = Val.getValueType();
+ assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
+ "Failed to tile the value with PartVT!");
+
+ if (NumParts == 1) {
+ assert(PartVT == ValueVT && "Type conversion failed!");
+ Parts[0] = Val;
+ return;
+ }
+
+ // Expand the value into multiple parts.
+ if (NumParts & (NumParts - 1)) {
+ // The number of parts is not a power of 2. Split off and copy the tail.
+ assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
+ "Do not know what to expand to!");
+ unsigned RoundParts = 1 << Log2_32(NumParts);
+ unsigned RoundBits = RoundParts * PartBits;
+ unsigned OddParts = NumParts - RoundParts;
+ SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
+ DAG.getConstant(RoundBits,
+ TLI.getShiftAmountTy()));
+ getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
+ if (TLI.isBigEndian())
+ // The odd parts were reversed by getCopyToParts - unreverse them.
+ std::reverse(Parts + RoundParts, Parts + NumParts);
+ NumParts = RoundParts;
+ ValueVT = MVT::getIntegerType(NumParts * PartBits);
+ Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+ }
+
+ // The number of parts is a power of 2. Repeatedly bisect the value using
+ // EXTRACT_ELEMENT.
+ Parts[0] = Val;
+ for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
+ for (unsigned i = 0; i < NumParts; i += StepSize) {
+ unsigned ThisBits = StepSize * PartBits / 2;
+ MVT::ValueType ThisVT =
+ ThisBits == PartBits ? PartVT : MVT::getIntegerType (ThisBits);
+
+ Parts[i+StepSize/2] =
+ DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
+ DAG.getConstant(1, PtrVT));
+ Parts[i] =
+ DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
+ DAG.getConstant(0, PtrVT));
+ }
+ }
+
+ if (TLI.isBigEndian())
+ std::reverse(Parts, Parts + NumParts);
+
+ return;
+ }
+
+ // Vector ValueVT.
+ if (NumParts == 1) {
if (PartVT != ValueVT) {
if (MVT::isVector(PartVT)) {
- assert(MVT::isVector(ValueVT) &&
- "Not a vector-vector cast?");
Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
- } else if (MVT::isVector(ValueVT)) {
- assert(NumParts == 1 &&
- MVT::getVectorElementType(ValueVT) == PartVT &&
+ } else {
+ assert(MVT::getVectorElementType(ValueVT) == PartVT &&
MVT::getVectorNumElements(ValueVT) == 1 &&
"Only trivial vector-to-scalar conversions should get here!");
Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
DAG.getConstant(0, PtrVT));
- } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
- if (PartVT < ValueVT)
- Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
- else
- Val = DAG.getNode(ExtendKind, PartVT, Val);
- } else if (MVT::isFloatingPoint(PartVT) &&
- MVT::isFloatingPoint(ValueVT)) {
- Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
- } else if (MVT::getSizeInBits(PartVT) ==
- MVT::getSizeInBits(ValueVT)) {
- Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
- } else {
- assert(0 && "Unknown mismatch!");
}
}
+
Parts[0] = Val;
return;
}
static GlobalVariable *ExtractTypeInfo (Value *V) {
V = IntrinsicInst::StripPointerCasts(V);
GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
- assert (GV || isa<ConstantPointerNull>(V) &&
+ assert ((GV || isa<ConstantPointerNull>(V)) &&
"TypeInfo must be a global variable or NULL");
return GV;
}
DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
return 0;
}
+ case Intrinsic::memory_barrier: {
+ SDOperand Ops[6];
+ Ops[0] = getRoot();
+ for (int x = 1; x < 6; ++x)
+ Ops[x] = getValue(I.getOperand(x));
+
+ DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
+ return 0;
+ }
+ case Intrinsic::atomic_lcs: {
+ SDOperand Root = getRoot();
+ SDOperand O3 = getValue(I.getOperand(3));
+ SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
+ getValue(I.getOperand(1)),
+ getValue(I.getOperand(2)),
+ O3, O3.getValueType());
+ setValue(&I, L);
+ DAG.setRoot(L.getValue(1));
+ return 0;
+ }
+ case Intrinsic::atomic_las: {
+ SDOperand Root = getRoot();
+ SDOperand O2 = getValue(I.getOperand(2));
+ SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root,
+ getValue(I.getOperand(1)),
+ O2, O2.getValueType());
+ setValue(&I, L);
+ DAG.setRoot(L.getValue(1));
+ return 0;
+ }
+ case Intrinsic::atomic_swap: {
+ SDOperand Root = getRoot();
+ SDOperand O2 = getValue(I.getOperand(2));
+ SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root,
+ getValue(I.getOperand(1)),
+ O2, O2.getValueType());
+ setValue(&I, L);
+ DAG.setRoot(L.getValue(1));
+ return 0;
+ }
+
}
}
std::pair<SDOperand,SDOperand> Result =
TLI.LowerCallTo(getRoot(), CS.getType(),
CS.paramHasAttr(0, ParamAttr::SExt),
+ CS.paramHasAttr(0, ParamAttr::ZExt),
FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
Callee, Args, DAG);
if (CS.getType() != Type::VoidTy)
/// busy in OutputRegs/InputRegs.
void MarkAllocatedRegs(bool isOutReg, bool isInReg,
std::set<unsigned> &OutputRegs,
- std::set<unsigned> &InputRegs) const {
- if (isOutReg)
- OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
- if (isInReg)
- InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
- }
+ std::set<unsigned> &InputRegs,
+ const TargetRegisterInfo &TRI) const {
+ if (isOutReg) {
+ for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
+ MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
+ }
+ if (isInReg) {
+ for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
+ MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
+ }
+ }
+
+private:
+ /// MarkRegAndAliases - Mark the specified register and all aliases in the
+ /// specified set.
+ static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
+ const TargetRegisterInfo &TRI) {
+ assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
+ Regs.insert(Reg);
+ if (const unsigned *Aliases = TRI.getAliasSet(Reg))
+ for (; *Aliases; ++Aliases)
+ Regs.insert(*Aliases);
+ }
};
} // end anon namespace.
}
}
OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
- OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
+ const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
+ OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
return;
}
Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
- OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
return;
}
OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
OpInfo.ConstraintVT);
- OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
+ OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
return;
}
}
break;
} else {
assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
- assert(0 && "matching constraints for memory operands unimp");
+ assert((NumOps >> 3) == 1 && "Unexpected number of operands");
+ // Add information to the INLINEASM node to know about this input.
+ unsigned ResOpType = 4/*MEM*/ | (1 << 3);
+ AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
+ TLI.getPointerTy()));
+ AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
+ break;
}
}
Args.push_back(Entry);
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
- DAG.getExternalSymbol("malloc", IntPtr),
- Args, DAG);
+ TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
+ true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
setValue(&I, Result.first); // Pointers always fit in registers
DAG.setRoot(Result.second);
}
Args.push_back(Entry);
MVT::ValueType IntPtr = TLI.getPointerTy();
std::pair<SDOperand,SDOperand> Result =
- TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
+ TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
+ CallingConv::C, true,
DAG.getExternalSymbol("free", IntPtr), Args, DAG);
DAG.setRoot(Result.second);
}
// Create the node.
SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
- DAG.getNodeValueTypes(RetVals), RetVals.size(),
+ DAG.getVTList(&RetVals[0], RetVals.size()),
&Ops[0], Ops.size()).Val;
+
+ // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
+ // allows exposing the loads that may be part of the argument access to the
+ // first DAGCombiner pass.
+ SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
+
+ // The number of results should match up, except that the lowered one may have
+ // an extra flag result.
+ assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
+ (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
+ TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
+ && "Lowering produced unexpected number of results!");
+ Result = TmpRes.Val;
+
unsigned NumArgRegs = Result->getNumValues() - 1;
DAG.setRoot(SDOperand(Result, NumArgRegs));
/// lowered by the target to something concrete. FIXME: When all targets are
/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
std::pair<SDOperand, SDOperand>
-TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
- bool RetTyIsSigned, bool isVarArg,
- unsigned CallingConv, bool isTailCall,
+TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
+ bool RetSExt, bool RetZExt, bool isVarArg,
+ unsigned CallingConv, bool isTailCall,
SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG) {
SmallVector<SDOperand, 32> Ops;
// Gather up the call result into a single value.
if (RetTy != Type::VoidTy) {
- ISD::NodeType AssertOp = ISD::AssertSext;
- if (!RetTyIsSigned)
+ ISD::NodeType AssertOp = ISD::DELETED_NODE;
+
+ if (RetSExt)
+ AssertOp = ISD::AssertSext;
+ else if (RetZExt)
AssertOp = ISD::AssertZext;
+
SmallVector<SDOperand, 4> Results(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i)
Results[i] = Res.getValue(i);
- Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
+ Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
+ AssertOp, true);
}
return std::make_pair(Res, Chain);