//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "isel"
+#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CallingConv.h"
#include "llvm/Instructions.h"
#include "llvm/Intrinsics.h"
#include "llvm/IntrinsicInst.h"
-#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineDebugInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
-#include "llvm/Support/CommandLine.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Debug.h"
-#include <map>
-#include <set>
-#include <iostream>
+#include "llvm/Support/Compiler.h"
#include <algorithm>
using namespace llvm;
static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
#endif
-// Scheduling heuristics
-enum SchedHeuristics {
- defaultScheduling, // Let the target specify its preference.
- noScheduling, // No scheduling, emit breadth first sequence.
- simpleScheduling, // Two pass, min. critical path, max. utilization.
- simpleNoItinScheduling, // Same as above exact using generic latency.
- listSchedulingBURR, // Bottom up reg reduction list scheduling.
- listSchedulingTD // Top-down list scheduler.
-};
+//===---------------------------------------------------------------------===//
+///
+/// RegisterScheduler class - Track the registration of instruction schedulers.
+///
+//===---------------------------------------------------------------------===//
+MachinePassRegistry RegisterScheduler::Registry;
+
+//===---------------------------------------------------------------------===//
+///
+/// ISHeuristic command line option for instruction schedulers.
+///
+//===---------------------------------------------------------------------===//
namespace {
- cl::opt<SchedHeuristics>
- ISHeuristic(
- "sched",
- cl::desc("Choose scheduling style"),
- cl::init(defaultScheduling),
- cl::values(
- clEnumValN(defaultScheduling, "default",
- "Target preferred scheduling style"),
- clEnumValN(noScheduling, "none",
- "No scheduling: breadth first sequencing"),
- clEnumValN(simpleScheduling, "simple",
- "Simple two pass scheduling: minimize critical path "
- "and maximize processor utilization"),
- clEnumValN(simpleNoItinScheduling, "simple-noitin",
- "Simple two pass scheduling: Same as simple "
- "except using generic latency"),
- clEnumValN(listSchedulingBURR, "list-burr",
- "Bottom up register reduction list scheduling"),
- clEnumValN(listSchedulingTD, "list-td",
- "Top-down list scheduler"),
- clEnumValEnd));
+ cl::opt<RegisterScheduler::FunctionPassCtor, false,
+ RegisterPassParser<RegisterScheduler> >
+ ISHeuristic("sched",
+ cl::init(&createDefaultScheduler),
+ cl::desc("Instruction schedulers available:"));
+
+ static RegisterScheduler
+ defaultListDAGScheduler("default", " Best scheduler for the target",
+ createDefaultScheduler);
} // namespace
namespace {
/// particular value is assigned and the type information about the value.
/// This is needed because values can be promoted into larger registers and
/// expanded into multiple smaller registers than the value.
- struct RegsForValue {
+ struct VISIBILITY_HIDDEN RegsForValue {
/// Regs - This list hold the register (for legal and promoted values)
/// or register set (for expanded values) that the value should be assigned
/// to.
/// specified value into the registers specified by this object. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
- SDOperand &Chain, SDOperand &Flag) const;
+ SDOperand &Chain, SDOperand &Flag,
+ MVT::ValueType PtrVT) const;
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
/// operand list. This adds the code marker and includes the number of
}
namespace llvm {
+ //===--------------------------------------------------------------------===//
+ /// createDefaultScheduler - This creates an instruction scheduler appropriate
+ /// for the target.
+ ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
+ MachineBasicBlock *BB) {
+ TargetLowering &TLI = IS->getTargetLowering();
+
+ if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
+ return createTDListDAGScheduler(IS, DAG, BB);
+ } else {
+ assert(TLI.getSchedulingPreference() ==
+ TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
+ return createBURRListDAGScheduler(IS, DAG, BB);
+ }
+ }
+
+
//===--------------------------------------------------------------------===//
/// FunctionLoweringInfo - This contains information that is global to a
/// function that is used when lowering a region of the function.
unsigned MakeReg(MVT::ValueType VT) {
return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
}
+
+ /// isExportedInst - Return true if the specified value is an instruction
+ /// exported from its block.
+ bool isExportedInst(const Value *V) {
+ return ValueMap.count(V);
+ }
unsigned CreateRegForValue(const Value *V);
BasicBlock *BB = I->getParent();
for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
+ // FIXME: Remove switchinst special case.
isa<SwitchInst>(*UI))
return true;
return false;
Function::iterator BB = Fn.begin(), EB = Fn.end();
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
- if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
+ if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
const Type *Ty = AI->getAllocatedType();
uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
unsigned Align =
std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
AI->getAlignment());
- // If the alignment of the value is smaller than the size of the value,
- // and if the size of the value is particularly small (<= 8 bytes),
- // round up to the size of the value for potentially better performance.
+ // If the alignment of the value is smaller than the size of the
+ // value, and if the size of the value is particularly small
+ // (<= 8 bytes), round up to the size of the value for potentially
+ // better performance.
//
// FIXME: This could be made better with a preferred alignment hook in
// TargetData. It serves primarily to 8-byte align doubles for X86.
if (Align < TySize && TySize <= 8) Align = TySize;
- TySize *= CUI->getValue(); // Get total allocated size.
+ TySize *= CUI->getZExtValue(); // Get total allocated size.
if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
StaticAllocaMap[AI] =
MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
// appropriate.
PHINode *PN;
- for (BasicBlock::iterator I = BB->begin();
- (PN = dyn_cast<PHINode>(I)); ++I)
- if (!PN->use_empty()) {
- MVT::ValueType VT = TLI.getValueType(PN->getType());
- unsigned NumElements;
- if (VT != MVT::Vector)
- NumElements = TLI.getNumElements(VT);
- else {
- MVT::ValueType VT1,VT2;
- NumElements =
- TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
- VT1, VT2);
- }
- unsigned PHIReg = ValueMap[PN];
- assert(PHIReg &&"PHI node does not have an assigned virtual register!");
- for (unsigned i = 0; i != NumElements; ++i)
- BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
+ for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
+ if (PN->use_empty()) continue;
+
+ MVT::ValueType VT = TLI.getValueType(PN->getType());
+ unsigned NumElements;
+ if (VT != MVT::Vector)
+ NumElements = TLI.getNumElements(VT);
+ else {
+ MVT::ValueType VT1,VT2;
+ NumElements =
+ TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
+ VT1, VT2);
}
+ unsigned PHIReg = ValueMap[PN];
+ assert(PHIReg && "PHI node does not have an assigned virtual register!");
+ const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
+ for (unsigned i = 0; i != NumElements; ++i)
+ BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
+ }
}
}
// If this value is represented with multiple target registers, make sure
// to create enough consecutive registers of the right (smaller) type.
- unsigned NT = VT-1; // Find the type to use.
- while (TLI.getNumElements((MVT::ValueType)NT) != 1)
- --NT;
-
- unsigned R = MakeReg((MVT::ValueType)NT);
+ VT = TLI.getTypeToExpandTo(VT);
+ unsigned R = MakeReg(VT);
for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
- MakeReg((MVT::ValueType)NT);
+ MakeReg(VT);
return R;
}
/// The comparison function for sorting Case values.
struct CaseCmp {
bool operator () (const Case& C1, const Case& C2) {
- if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
- return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
+ if (const ConstantInt* I1 = dyn_cast<const ConstantInt>(C1.first))
+ if (I1->getType()->isUnsigned())
+ return I1->getZExtValue() <
+ cast<const ConstantInt>(C2.first)->getZExtValue();
- const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
- return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
+ return cast<const ConstantInt>(C1.first)->getSExtValue() <
+ cast<const ConstantInt>(C2.first)->getSExtValue();
}
};
}
// Otherwise, we have to make a token factor node.
- SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
+ SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
return Root;
}
+ SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
+
void visit(Instruction &I) { visit(I.getOpcode(), I); }
void visit(unsigned Opcode, User &I) {
+ // Note: this doesn't use InstVisitor, because it has to work with
+ // ConstantExpr's in addition to instructions.
switch (Opcode) {
default: assert(0 && "Unknown instruction type encountered!");
abort();
void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
- SDOperand SrcValue, SDOperand Root,
+ const Value *SV, SDOperand Root,
bool isVolatile);
SDOperand getIntPtrConstant(uint64_t Val) {
std::set<unsigned> &OutputRegs,
std::set<unsigned> &InputRegs);
+ void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
+ unsigned Opc);
+ bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
+ void ExportFromCurrentBlock(Value *V);
+
// Terminator instructions.
void visitRet(ReturnInst &I);
void visitBr(BranchInst &I);
void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
- void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
+ void visitIntBinary(User &I, unsigned IntOp, unsigned VecOp);
+ void visitFPBinary(User &I, unsigned FPOp, unsigned VecOp);
void visitShift(User &I, unsigned Opcode);
void visitAdd(User &I) {
- visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
+ if (I.getType()->isFloatingPoint())
+ visitFPBinary(I, ISD::FADD, ISD::VADD);
+ else
+ visitIntBinary(I, ISD::ADD, ISD::VADD);
}
void visitSub(User &I);
- void visitMul(User &I) {
- visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
- }
- void visitDiv(User &I) {
- const Type *Ty = I.getType();
- visitBinary(I,
- Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
- Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
- }
- void visitRem(User &I) {
- const Type *Ty = I.getType();
- visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
- }
- void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
- void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
- void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
- void visitShl(User &I) { visitShift(I, ISD::SHL); }
- void visitShr(User &I) {
- visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
+ void visitMul(User &I) {
+ if (I.getType()->isFloatingPoint())
+ visitFPBinary(I, ISD::FMUL, ISD::VMUL);
+ else
+ visitIntBinary(I, ISD::MUL, ISD::VMUL);
}
-
- void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
- void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
- void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
- void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
- void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
- void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
- void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
+ void visitURem(User &I) { visitIntBinary(I, ISD::UREM, 0); }
+ void visitSRem(User &I) { visitIntBinary(I, ISD::SREM, 0); }
+ void visitFRem(User &I) { visitFPBinary (I, ISD::FREM, 0); }
+ void visitUDiv(User &I) { visitIntBinary(I, ISD::UDIV, ISD::VUDIV); }
+ void visitSDiv(User &I) { visitIntBinary(I, ISD::SDIV, ISD::VSDIV); }
+ void visitFDiv(User &I) { visitFPBinary (I, ISD::FDIV, ISD::VSDIV); }
+ void visitAnd(User &I) { visitIntBinary(I, ISD::AND, ISD::VAND); }
+ void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); }
+ void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); }
+ void visitShl(User &I) { visitShift(I, ISD::SHL); }
+ void visitLShr(User &I) { visitShift(I, ISD::SRL); }
+ void visitAShr(User &I) { visitShift(I, ISD::SRA); }
+ void visitICmp(User &I);
+ void visitFCmp(User &I);
+ void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
+ ISD::CondCode FPOpc);
+ void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
+ ISD::SETOEQ); }
+ void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
+ ISD::SETUNE); }
+ void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
+ ISD::SETOLE); }
+ void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
+ ISD::SETOGE); }
+ void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
+ ISD::SETOLT); }
+ void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
+ ISD::SETOGT); }
+ // Visit the conversion instructions
+ void visitTrunc(User &I);
+ void visitZExt(User &I);
+ void visitSExt(User &I);
+ void visitFPTrunc(User &I);
+ void visitFPExt(User &I);
+ void visitFPToUI(User &I);
+ void visitFPToSI(User &I);
+ void visitUIToFP(User &I);
+ void visitSIToFP(User &I);
+ void visitPtrToInt(User &I);
+ void visitIntToPtr(User &I);
+ void visitBitCast(User &I);
void visitExtractElement(User &I);
void visitInsertElement(User &I);
void visitShuffleVector(User &I);
void visitGetElementPtr(User &I);
- void visitCast(User &I);
void visitSelect(User &I);
void visitMalloc(MallocInst &I);
unsigned NumElements = PTy->getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
// Create a VConstant node with generic Vector type.
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
Ops.push_back(DAG.getValueType(PVT));
- return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+ &Ops[0], Ops.size());
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
return N = DAG.getConstantFP(CFP->getValue(), VT);
} else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
// Now that we know the number and type of the elements, push a
// Constant or ConstantFP node onto the ops list for each element of
// the packed constant.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
for (unsigned i = 0; i != NumElements; ++i)
Ops.push_back(getValue(CP->getOperand(i)));
// Create a VBUILD_VECTOR node with generic Vector type.
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
Ops.push_back(DAG.getValueType(PVT));
- return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
} else {
// Canonicalize all constant ints to be unsigned.
- return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
+ return N = DAG.getConstant(cast<ConstantIntegral>(C)->getZExtValue(),VT);
}
}
// If this type is not legal, make it so now.
if (VT != MVT::Vector) {
- MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
-
- N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
- if (DestVT < VT) {
+ if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
// Source must be expanded. This input value is actually coming from the
// register pair VMI->second and VMI->second+1.
- N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
- DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
- } else if (DestVT > VT) { // Promotion case
- if (MVT::isFloatingPoint(VT))
- N = DAG.getNode(ISD::FP_ROUND, VT, N);
- else
- N = DAG.getNode(ISD::TRUNCATE, VT, N);
+ MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
+ unsigned NumVals = TLI.getNumElements(VT);
+ N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+ if (NumVals == 1)
+ N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
+ else {
+ assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
+ N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
+ DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
+ }
+ } else {
+ MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
+ N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
+ if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
+ N = MVT::isFloatingPoint(VT)
+ ? DAG.getNode(ISD::FP_ROUND, VT, N)
+ : DAG.getNode(ISD::TRUNCATE, VT, N);
}
} else {
// Otherwise, if this is a vector, make it available as a generic vector
PTyLegalElementVT);
// Build a VBUILD_VECTOR with the input registers.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
if (PTyElementVT == PTyLegalElementVT) {
// If the value types are legal, just VBUILD the CopyFromReg nodes.
for (unsigned i = 0; i != NE; ++i)
Ops.push_back(DAG.getConstant(NE, MVT::i32));
Ops.push_back(DAG.getValueType(PTyLegalElementVT));
- N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
// Finally, use a VBIT_CONVERT to make this available as the appropriate
// vector type.
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
return;
}
- std::vector<SDOperand> NewValues;
+ SmallVector<SDOperand, 8> NewValues;
NewValues.push_back(getRoot());
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
SDOperand RetOp = getValue(I.getOperand(i));
+ bool isSigned = I.getOperand(i)->getType()->isSigned();
// If this is an integer return value, we need to promote it ourselves to
// the full width of a register, since LegalizeOp will use ANY_EXTEND rather
// than sign/zero.
+ // FIXME: C calling convention requires the return type to be promoted to
+ // at least 32-bit. But this is not necessary for non-C calling conventions.
if (MVT::isInteger(RetOp.getValueType()) &&
RetOp.getValueType() < MVT::i64) {
MVT::ValueType TmpVT;
else
TmpVT = MVT::i32;
- if (I.getOperand(i)->getType()->isSigned())
+ if (isSigned)
RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
else
RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
}
NewValues.push_back(RetOp);
+ NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
+ }
+ DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
+ &NewValues[0], NewValues.size()));
+}
+
+/// ExportFromCurrentBlock - If this condition isn't known to be exported from
+/// the current basic block, add it to ValueMap now so that we'll get a
+/// CopyTo/FromReg.
+void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
+ // No need to export constants.
+ if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
+
+ // Already exported?
+ if (FuncInfo.isExportedInst(V)) return;
+
+ unsigned Reg = FuncInfo.InitializeRegForValue(V);
+ PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
+}
+
+bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
+ const BasicBlock *FromBB) {
+ // The operands of the setcc have to be in this block. We don't know
+ // how to export them from some other block.
+ if (Instruction *VI = dyn_cast<Instruction>(V)) {
+ // Can export from current BB.
+ if (VI->getParent() == FromBB)
+ return true;
+
+ // Is already exported, noop.
+ return FuncInfo.isExportedInst(V);
+ }
+
+ // If this is an argument, we can export it if the BB is the entry block or
+ // if it is already exported.
+ if (isa<Argument>(V)) {
+ if (FromBB == &FromBB->getParent()->getEntryBlock())
+ return true;
+
+ // Otherwise, can only export this if it is already exported.
+ return FuncInfo.isExportedInst(V);
+ }
+
+ // Otherwise, constants can always be exported.
+ return true;
+}
+
+static bool InBlock(const Value *V, const BasicBlock *BB) {
+ if (const Instruction *I = dyn_cast<Instruction>(V))
+ return I->getParent() == BB;
+ return true;
+}
+
+/// FindMergedConditions - If Cond is an expression like
+void SelectionDAGLowering::FindMergedConditions(Value *Cond,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
+ MachineBasicBlock *CurBB,
+ unsigned Opc) {
+ // If this node is not part of the or/and tree, emit it as a branch.
+ BinaryOperator *BOp = dyn_cast<BinaryOperator>(Cond);
+
+ if (!BOp || (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
+ BOp->getParent() != CurBB->getBasicBlock() ||
+ !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
+ !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
+ const BasicBlock *BB = CurBB->getBasicBlock();
+
+ if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Cond))
+ if ((II->getIntrinsicID() == Intrinsic::isunordered_f32 ||
+ II->getIntrinsicID() == Intrinsic::isunordered_f64) &&
+ // The operands of the setcc have to be in this block. We don't know
+ // how to export them from some other block. If this is the first
+ // block of the sequence, no exporting is needed.
+ (CurBB == CurMBB ||
+ (isExportableFromCurrentBlock(II->getOperand(1), BB) &&
+ isExportableFromCurrentBlock(II->getOperand(2), BB)))) {
+ SelectionDAGISel::CaseBlock CB(ISD::SETUO, II->getOperand(1),
+ II->getOperand(2), TBB, FBB, CurBB);
+ SwitchCases.push_back(CB);
+ return;
+ }
+
+
+ // If the leaf of the tree is a setcond inst, merge the condition into the
+ // caseblock.
+ if (BOp && isa<SetCondInst>(BOp) &&
+ // The operands of the setcc have to be in this block. We don't know
+ // how to export them from some other block. If this is the first block
+ // of the sequence, no exporting is needed.
+ (CurBB == CurMBB ||
+ (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
+ isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
+ ISD::CondCode SignCond, UnsCond, FPCond, Condition;
+ switch (BOp->getOpcode()) {
+ default: assert(0 && "Unknown setcc opcode!");
+ case Instruction::SetEQ:
+ SignCond = ISD::SETEQ;
+ UnsCond = ISD::SETEQ;
+ FPCond = ISD::SETOEQ;
+ break;
+ case Instruction::SetNE:
+ SignCond = ISD::SETNE;
+ UnsCond = ISD::SETNE;
+ FPCond = ISD::SETUNE;
+ break;
+ case Instruction::SetLE:
+ SignCond = ISD::SETLE;
+ UnsCond = ISD::SETULE;
+ FPCond = ISD::SETOLE;
+ break;
+ case Instruction::SetGE:
+ SignCond = ISD::SETGE;
+ UnsCond = ISD::SETUGE;
+ FPCond = ISD::SETOGE;
+ break;
+ case Instruction::SetLT:
+ SignCond = ISD::SETLT;
+ UnsCond = ISD::SETULT;
+ FPCond = ISD::SETOLT;
+ break;
+ case Instruction::SetGT:
+ SignCond = ISD::SETGT;
+ UnsCond = ISD::SETUGT;
+ FPCond = ISD::SETOGT;
+ break;
+ }
+
+ const Type *OpType = BOp->getOperand(0)->getType();
+ if (const PackedType *PTy = dyn_cast<PackedType>(OpType))
+ OpType = PTy->getElementType();
+
+ if (!FiniteOnlyFPMath() && OpType->isFloatingPoint())
+ Condition = FPCond;
+ else if (OpType->isUnsigned())
+ Condition = UnsCond;
+ else
+ Condition = SignCond;
+
+ SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
+ BOp->getOperand(1), TBB, FBB, CurBB);
+ SwitchCases.push_back(CB);
+ return;
+ }
+
+ // Create a CaseBlock record representing this branch.
+ SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantBool::getTrue(),
+ TBB, FBB, CurBB);
+ SwitchCases.push_back(CB);
+ return;
+ }
+
+
+ // Create TmpBB after CurBB.
+ MachineFunction::iterator BBI = CurBB;
+ MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
+ CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
+
+ if (Opc == Instruction::Or) {
+ // Codegen X | Y as:
+ // jmp_if_X TBB
+ // jmp TmpBB
+ // TmpBB:
+ // jmp_if_Y TBB
+ // jmp FBB
+ //
+
+ // Emit the LHS condition.
+ FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
+
+ // Emit the RHS condition into TmpBB.
+ FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
+ } else {
+ assert(Opc == Instruction::And && "Unknown merge op!");
+ // Codegen X & Y as:
+ // jmp_if_X TmpBB
+ // jmp FBB
+ // TmpBB:
+ // jmp_if_Y TBB
+ // jmp FBB
+ //
+ // This requires creation of TmpBB after CurBB.
+
+ // Emit the LHS condition.
+ FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
+
+ // Emit the RHS condition into TmpBB.
+ FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
+ }
+}
+
+/// If the set of cases should be emitted as a series of branches, return true.
+/// If we should emit this as a bunch of and/or'd together conditions, return
+/// false.
+static bool
+ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
+ if (Cases.size() != 2) return true;
+
+ // If this is two comparisons of the same values or'd or and'd together, they
+ // will get folded into a single comparison, so don't emit two blocks.
+ if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
+ Cases[0].CmpRHS == Cases[1].CmpRHS) ||
+ (Cases[0].CmpRHS == Cases[1].CmpLHS &&
+ Cases[0].CmpLHS == Cases[1].CmpRHS)) {
+ return false;
}
- DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
+
+ return true;
}
void SelectionDAGLowering::visitBr(BranchInst &I) {
// Update machine-CFG edges.
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
- CurMBB->addSuccessor(Succ0MBB);
// Figure out which block is immediately after the current one.
MachineBasicBlock *NextBlock = 0;
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
DAG.getBasicBlock(Succ0MBB)));
- } else {
- MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
- CurMBB->addSuccessor(Succ1MBB);
-
- SDOperand Cond = getValue(I.getCondition());
- if (Succ1MBB == NextBlock) {
- // If the condition is false, fall through. This means we should branch
- // if the condition is true to Succ #0.
- DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
- Cond, DAG.getBasicBlock(Succ0MBB)));
- } else if (Succ0MBB == NextBlock) {
- // If the condition is true, fall through. This means we should branch if
- // the condition is false to Succ #1. Invert the condition first.
- SDOperand True = DAG.getConstant(1, Cond.getValueType());
- Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
- DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
- Cond, DAG.getBasicBlock(Succ1MBB)));
- } else {
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- // If the false case is the current basic block, then this is a self
- // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
- // adds an extra instruction in the loop. Instead, invert the
- // condition and emit "Loop: ... br!cond Loop; br Out.
- if (CurMBB == Succ1MBB) {
- std::swap(Succ0MBB, Succ1MBB);
- SDOperand True = DAG.getConstant(1, Cond.getValueType());
- Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
+
+ // Update machine-CFG edges.
+ CurMBB->addSuccessor(Succ0MBB);
+
+ return;
+ }
+
+ // If this condition is one of the special cases we handle, do special stuff
+ // now.
+ Value *CondVal = I.getCondition();
+ MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
+
+ // If this is a series of conditions that are or'd or and'd together, emit
+ // this as a sequence of branches instead of setcc's with and/or operations.
+ // For example, instead of something like:
+ // cmp A, B
+ // C = seteq
+ // cmp D, E
+ // F = setle
+ // or C, F
+ // jnz foo
+ // Emit:
+ // cmp A, B
+ // je foo
+ // cmp D, E
+ // jle foo
+ //
+ if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
+ if (BOp->hasOneUse() &&
+ (BOp->getOpcode() == Instruction::And ||
+ BOp->getOpcode() == Instruction::Or)) {
+ FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
+ // If the compares in later blocks need to use values not currently
+ // exported from this block, export them now. This block should always
+ // be the first entry.
+ assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
+
+ // Allow some cases to be rejected.
+ if (ShouldEmitAsBranches(SwitchCases)) {
+ for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
+ ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
+ ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
+ }
+
+ // Emit the branch for this block.
+ visitSwitchCase(SwitchCases[0]);
+ SwitchCases.erase(SwitchCases.begin());
+ return;
}
- SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
- DAG.getBasicBlock(Succ0MBB));
- DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
- DAG.getBasicBlock(Succ1MBB)));
+
+ // Okay, we decided not to do this, remove any inserted MBB's and clear
+ // SwitchCases.
+ for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
+ CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
+
+ SwitchCases.clear();
}
}
+
+ // Create a CaseBlock record representing this branch.
+ SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantBool::getTrue(),
+ Succ0MBB, Succ1MBB, CurMBB);
+ // Use visitSwitchCase to actually insert the fast branch sequence for this
+ // cond branch.
+ visitSwitchCase(CB);
}
/// visitSwitchCase - Emits the necessary code to represent a single node in
/// the binary search tree resulting from lowering a switch instruction.
void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
- SDOperand SwitchOp = getValue(CB.SwitchV);
- SDOperand CaseOp = getValue(CB.CaseC);
- SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
+ SDOperand Cond;
+ SDOperand CondLHS = getValue(CB.CmpLHS);
+
+ // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
+ // handle common cases produced by branch lowering.
+ if (CB.CmpRHS == ConstantBool::getTrue() && CB.CC == ISD::SETEQ)
+ Cond = CondLHS;
+ else if (CB.CmpRHS == ConstantBool::getFalse() && CB.CC == ISD::SETEQ) {
+ SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
+ Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
+ } else
+ Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
// Set NextBlock to be the MBB immediately after the current one, if any.
// This is used to avoid emitting unnecessary branches to the next block.
// If the lhs block is the next block, invert the condition so that we can
// fall through to the lhs instead of the rhs block.
- if (CB.LHSBB == NextBlock) {
- std::swap(CB.LHSBB, CB.RHSBB);
+ if (CB.TrueBB == NextBlock) {
+ std::swap(CB.TrueBB, CB.FalseBB);
SDOperand True = DAG.getConstant(1, Cond.getValueType());
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
}
SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
- DAG.getBasicBlock(CB.LHSBB));
- if (CB.RHSBB == NextBlock)
+ DAG.getBasicBlock(CB.TrueBB));
+ if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
else
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
- DAG.getBasicBlock(CB.RHSBB)));
+ DAG.getBasicBlock(CB.FalseBB)));
// Update successor info
- CurMBB->addSuccessor(CB.LHSBB);
- CurMBB->addSuccessor(CB.RHSBB);
+ CurMBB->addSuccessor(CB.TrueBB);
+ CurMBB->addSuccessor(CB.FalseBB);
}
-/// visitSwitchCase - Emits the necessary code to represent a single node in
-/// the binary search tree resulting from lowering a switch instruction.
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
- // FIXME: Need to emit different code for PIC vs. Non-PIC, specifically,
- // we need to add the address of the jump table to the value loaded, since
- // the entries in the jump table will be differences rather than absolute
- // addresses.
-
// Emit the code for the jump table
MVT::ValueType PTy = TLI.getPointerTy();
- unsigned PTyBytes = MVT::getSizeInBits(PTy)/8;
- SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
- SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
- DAG.getConstant(PTyBytes, PTy));
- SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy));
- SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0));
- DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
+ SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
+ SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
+ DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
+ Table, Index));
+ return;
}
void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
// Figure out which block is immediately after the current one.
MachineBasicBlock *NextBlock = 0;
MachineFunction::iterator BBI = CurMBB;
+
if (++BBI != CurMBB->getParent()->end())
NextBlock = BBI;
+ MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
+
// If there is only the default destination, branch to it if it is not the
// next basic block. Otherwise, just fall through.
if (I.getNumOperands() == 2) {
// Update machine-CFG edges.
- MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
+
// If this is not a fall-through branch, emit the branch.
- if (DefaultMBB != NextBlock)
+ if (Default != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
- DAG.getBasicBlock(DefaultMBB)));
+ DAG.getBasicBlock(Default)));
+
+ CurMBB->addSuccessor(Default);
return;
}
// representing each one, and sort the vector so that we can efficiently
// create a binary search tree from them.
std::vector<Case> Cases;
+
for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
}
+
std::sort(Cases.begin(), Cases.end(), CaseCmp());
// Get the Value to be switched on and default basic blocks, which will be
// inserted into CaseBlock records, representing basic blocks in the binary
// search tree.
Value *SV = I.getOperand(0);
- MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
// Get the MachineFunction which holds the current MBB. This is used during
// emission of jump tables, and when inserting any additional MBBs necessary
// to represent the switch.
MachineFunction *CurMF = CurMBB->getParent();
const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
- Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel();
-
- // If the switch has more than 5 blocks, and at least 75% dense, then emit a
- // jump table rather than lowering the switch to a binary tree of conditional
- // branches.
- // FIXME: Make this work with PIC code
- if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
- (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) &&
+
+ // If the switch has few cases (two or less) emit a series of specific
+ // tests.
+ if (Cases.size() < 3) {
+ // TODO: If any two of the cases has the same destination, and if one value
+ // is the same as the other, but has one bit unset that the other has set,
+ // use bit manipulation to do two compares at once. For example:
+ // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
+
+ // Rearrange the case blocks so that the last one falls through if possible.
+ if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) {
+ // The last case block won't fall through into 'NextBlock' if we emit the
+ // branches in this order. See if rearranging a case value would help.
+ for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) {
+ if (Cases[i].second == NextBlock) {
+ std::swap(Cases[i], Cases.back());
+ break;
+ }
+ }
+ }
+
+ // Create a CaseBlock record representing a conditional branch to
+ // the Case's target mbb if the value being switched on SV is equal
+ // to C.
+ MachineBasicBlock *CurBlock = CurMBB;
+ for (unsigned i = 0, e = Cases.size(); i != e; ++i) {
+ MachineBasicBlock *FallThrough;
+ if (i != e-1) {
+ FallThrough = new MachineBasicBlock(CurMBB->getBasicBlock());
+ CurMF->getBasicBlockList().insert(BBI, FallThrough);
+ } else {
+ // If the last case doesn't match, go to the default block.
+ FallThrough = Default;
+ }
+
+ SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, Cases[i].first,
+ Cases[i].second, FallThrough, CurBlock);
+
+ // If emitting the first comparison, just call visitSwitchCase to emit the
+ // code into the current block. Otherwise, push the CaseBlock onto the
+ // vector to be later processed by SDISel, and insert the node's MBB
+ // before the next MBB.
+ if (CurBlock == CurMBB)
+ visitSwitchCase(CB);
+ else
+ SwitchCases.push_back(CB);
+
+ CurBlock = FallThrough;
+ }
+ return;
+ }
+
+ // If the switch has more than 5 blocks, and at least 31.25% dense, and the
+ // target supports indirect branches, then emit a jump table rather than
+ // lowering the switch to a binary tree of conditional branches.
+ if ((TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
+ TLI.isOperationLegal(ISD::BRIND, MVT::Other)) &&
Cases.size() > 5) {
- uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
- uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
+ uint64_t First =cast<ConstantIntegral>(Cases.front().first)->getZExtValue();
+ uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getZExtValue();
double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
- if (Density >= 0.75) {
+ if (Density >= 0.3125) {
// Create a new basic block to hold the code for loading the address
// of the jump table, and jumping to it. Update successor information;
// we will either branch to the default case for the switch, or the jump
SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
else
SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
+
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
// of the jump table. If the value of the jump table slot corresponds to
// a case statement, push the case's BB onto the vector, otherwise, push
// the default BB.
- std::set<MachineBasicBlock*> UniqueBBs;
std::vector<MachineBasicBlock*> DestBBs;
uint64_t TEI = First;
- for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
- if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
+ for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI)
+ if (cast<ConstantIntegral>(ii->first)->getZExtValue() == TEI) {
DestBBs.push_back(ii->second);
- UniqueBBs.insert(ii->second);
++ii;
} else {
DestBBs.push_back(Default);
- UniqueBBs.insert(Default);
}
- }
- // Update successor info
- for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(),
- ee = UniqueBBs.end(); ii != ee; ++ii)
- JumpTableBB->addSuccessor(*ii);
+ // Update successor info. Add one edge to each unique successor.
+ // Vector bool would be better, but vector<bool> is really slow.
+ std::vector<unsigned char> SuccsHandled;
+ SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs());
+
+ for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
+ E = DestBBs.end(); I != E; ++I) {
+ if (!SuccsHandled[(*I)->getNumber()]) {
+ SuccsHandled[(*I)->getNumber()] = true;
+ JumpTableBB->addSuccessor(*I);
+ }
+ }
// Create a jump table index for this jump table, or return an existing
// one.
MachineBasicBlock *Target = CR.Range.first->second;
SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
CR.CaseBB);
+
// If the MBB representing the leaf node is the current MBB, then just
// call visitSwitchCase to emit the code into the current block.
// Otherwise, push the CaseBlock onto the vector to be later processed
// by SDISel, and insert the node's MBB before the next MBB.
if (CR.CaseBB == CurMBB)
visitSwitchCase(CB);
- else {
+ else
SwitchCases.push_back(CB);
- CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
- }
} else {
// split case range at pivot
CaseItr Pivot = CR.Range.first + (Size / 2);
CaseRange LHSR(CR.Range.first, Pivot);
CaseRange RHSR(Pivot, CR.Range.second);
Constant *C = Pivot->first;
- MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
+ MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
+
// We know that we branch to the LHS if the Value being switched on is
// less than the Pivot value, C. We use this to optimize our binary
// tree a bit, by recognizing that if SV is greater than or equal to the
// rather than creating a leaf node for it.
if ((LHSR.second - LHSR.first) == 1 &&
LHSR.first->first == CR.GE &&
- cast<ConstantIntegral>(C)->getRawValue() ==
- (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
- LHSBB = LHSR.first->second;
+ cast<ConstantIntegral>(C)->getZExtValue() ==
+ (cast<ConstantIntegral>(CR.GE)->getZExtValue() + 1ULL)) {
+ TrueBB = LHSR.first->second;
} else {
- LHSBB = new MachineBasicBlock(LLVMBB);
- CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
+ TrueBB = new MachineBasicBlock(LLVMBB);
+ CurMF->getBasicBlockList().insert(BBI, TrueBB);
+ CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
}
+
// Similar to the optimization above, if the Value being switched on is
// known to be less than the Constant CR.LT, and the current Case Value
// is CR.LT - 1, then we can branch directly to the target block for
// the current Case Value, rather than emitting a RHS leaf node for it.
if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
- cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
- (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
- RHSBB = RHSR.first->second;
+ cast<ConstantIntegral>(RHSR.first->first)->getZExtValue() ==
+ (cast<ConstantIntegral>(CR.LT)->getZExtValue() - 1ULL)) {
+ FalseBB = RHSR.first->second;
} else {
- RHSBB = new MachineBasicBlock(LLVMBB);
- CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
+ FalseBB = new MachineBasicBlock(LLVMBB);
+ CurMF->getBasicBlockList().insert(BBI, FalseBB);
+ CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
}
+
// Create a CaseBlock record representing a conditional branch to
// the LHS node if the value being switched on SV is less than C.
// Otherwise, branch to LHS.
ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
- SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
+ SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
+
if (CR.CaseBB == CurMBB)
visitSwitchCase(CB);
- else {
+ else
SwitchCases.push_back(CB);
- CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
- }
}
}
}
setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
return;
}
- }
- visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
+ visitFPBinary(I, ISD::FSUB, ISD::VSUB);
+ } else
+ visitIntBinary(I, ISD::SUB, ISD::VSUB);
}
-void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
- unsigned VecOp) {
+void
+SelectionDAGLowering::visitIntBinary(User &I, unsigned IntOp, unsigned VecOp) {
const Type *Ty = I.getType();
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
- if (Ty->isIntegral()) {
- setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
- } else if (Ty->isFloatingPoint()) {
- setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
+ if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
+ SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
+ SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
+ setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
} else {
- const PackedType *PTy = cast<PackedType>(Ty);
+ setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
+ }
+}
+
+void
+SelectionDAGLowering::visitFPBinary(User &I, unsigned FPOp, unsigned VecOp) {
+ const Type *Ty = I.getType();
+ SDOperand Op1 = getValue(I.getOperand(0));
+ SDOperand Op2 = getValue(I.getOperand(1));
+
+ if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
+ } else {
+ setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
}
}
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
}
+void SelectionDAGLowering::visitICmp(User &I) {
+ ICmpInst *IC = cast<ICmpInst>(&I);
+ SDOperand Op1 = getValue(IC->getOperand(0));
+ SDOperand Op2 = getValue(IC->getOperand(1));
+ ISD::CondCode Opcode;
+ switch (IC->getPredicate()) {
+ case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
+ case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
+ case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
+ case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
+ case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
+ case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
+ case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
+ case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
+ case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
+ case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
+ default:
+ assert(!"Invalid ICmp predicate value");
+ Opcode = ISD::SETEQ;
+ break;
+ }
+ setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
+}
+
+void SelectionDAGLowering::visitFCmp(User &I) {
+ FCmpInst *FC = cast<FCmpInst>(&I);
+ SDOperand Op1 = getValue(FC->getOperand(0));
+ SDOperand Op2 = getValue(FC->getOperand(1));
+ ISD::CondCode Opcode;
+ switch (FC->getPredicate()) {
+ case FCmpInst::FCMP_FALSE : Opcode = ISD::SETFALSE;
+ case FCmpInst::FCMP_OEQ : Opcode = ISD::SETOEQ;
+ case FCmpInst::FCMP_OGT : Opcode = ISD::SETOGT;
+ case FCmpInst::FCMP_OGE : Opcode = ISD::SETOGE;
+ case FCmpInst::FCMP_OLT : Opcode = ISD::SETOLT;
+ case FCmpInst::FCMP_OLE : Opcode = ISD::SETOLE;
+ case FCmpInst::FCMP_ONE : Opcode = ISD::SETONE;
+ case FCmpInst::FCMP_ORD : Opcode = ISD::SETO;
+ case FCmpInst::FCMP_UNO : Opcode = ISD::SETUO;
+ case FCmpInst::FCMP_UEQ : Opcode = ISD::SETUEQ;
+ case FCmpInst::FCMP_UGT : Opcode = ISD::SETUGT;
+ case FCmpInst::FCMP_UGE : Opcode = ISD::SETUGE;
+ case FCmpInst::FCMP_ULT : Opcode = ISD::SETULT;
+ case FCmpInst::FCMP_ULE : Opcode = ISD::SETULE;
+ case FCmpInst::FCMP_UNE : Opcode = ISD::SETUNE;
+ case FCmpInst::FCMP_TRUE : Opcode = ISD::SETTRUE;
+ default:
+ assert(!"Invalid FCmp predicate value");
+ Opcode = ISD::SETFALSE;
+ break;
+ }
+ setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
+}
+
void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
- ISD::CondCode UnsignedOpcode) {
+ ISD::CondCode UnsignedOpcode,
+ ISD::CondCode FPOpcode) {
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = SignedOpcode;
- if (I.getOperand(0)->getType()->isUnsigned())
+ if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
+ Opcode = FPOpcode;
+ else if (I.getOperand(0)->getType()->isUnsigned())
Opcode = UnsignedOpcode;
setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
}
}
}
-void SelectionDAGLowering::visitCast(User &I) {
+
+void SelectionDAGLowering::visitTrunc(User &I) {
+ // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
+}
+
+void SelectionDAGLowering::visitZExt(User &I) {
+ // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
+ // ZExt also can't be a cast to bool for same reason. So, nothing much to do
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
+}
+
+void SelectionDAGLowering::visitSExt(User &I) {
+ // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
+ // SExt also can't be a cast to bool for same reason. So, nothing much to do
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
+}
+
+void SelectionDAGLowering::visitFPTrunc(User &I) {
+ // FPTrunc is never a no-op cast, no need to check
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
+}
+
+void SelectionDAGLowering::visitFPExt(User &I){
+ // FPTrunc is never a no-op cast, no need to check
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
+}
+
+void SelectionDAGLowering::visitFPToUI(User &I) {
+ // FPToUI is never a no-op cast, no need to check
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
+}
+
+void SelectionDAGLowering::visitFPToSI(User &I) {
+ // FPToSI is never a no-op cast, no need to check
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
+}
+
+void SelectionDAGLowering::visitUIToFP(User &I) {
+ // UIToFP is never a no-op cast, no need to check
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
+}
+
+void SelectionDAGLowering::visitSIToFP(User &I){
+ // UIToFP is never a no-op cast, no need to check
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
+}
+
+void SelectionDAGLowering::visitPtrToInt(User &I) {
+ // What to do depends on the size of the integer and the size of the pointer.
+ // We can either truncate, zero extend, or no-op, accordingly.
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType SrcVT = N.getValueType();
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ SDOperand Result;
+ if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
+ Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
+ else
+ // Note: ZERO_EXTEND can handle cases where the sizes are equal too
+ Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
+ setValue(&I, Result);
+}
+
+void SelectionDAGLowering::visitIntToPtr(User &I) {
+ // What to do depends on the size of the integer and the size of the pointer.
+ // We can either truncate, zero extend, or no-op, accordingly.
SDOperand N = getValue(I.getOperand(0));
MVT::ValueType SrcVT = N.getValueType();
MVT::ValueType DestVT = TLI.getValueType(I.getType());
+ if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
+ setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
+ else
+ // Note: ZERO_EXTEND can handle cases where the sizes are equal too
+ setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
+}
+void SelectionDAGLowering::visitBitCast(User &I) {
+ SDOperand N = getValue(I.getOperand(0));
+ MVT::ValueType DestVT = TLI.getValueType(I.getType());
if (DestVT == MVT::Vector) {
- // This is a cast to a vector from something else. This is always a bit
- // convert. Get information about the input vector.
+ // This is a cast to a vector from something else.
+ // Get information about the output vector.
const PackedType *DestTy = cast<PackedType>(I.getType());
MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
DAG.getConstant(DestTy->getNumElements(),MVT::i32),
DAG.getValueType(EltVT)));
- } else if (SrcVT == DestVT) {
- setValue(&I, N); // noop cast.
- } else if (DestVT == MVT::i1) {
- // Cast to bool is a comparison against zero, not truncation to zero.
- SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
- DAG.getConstantFP(0.0, N.getValueType());
- setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
- } else if (isInteger(SrcVT)) {
- if (isInteger(DestVT)) { // Int -> Int cast
- if (DestVT < SrcVT) // Truncating cast?
- setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
- else if (I.getOperand(0)->getType()->isSigned())
- setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
- else
- setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
- } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
- if (I.getOperand(0)->getType()->isSigned())
- setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
- else
- setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
- } else {
- assert(0 && "Unknown cast!");
- }
- } else if (isFloatingPoint(SrcVT)) {
- if (isFloatingPoint(DestVT)) { // FP -> FP cast
- if (DestVT < SrcVT) // Rounding cast?
- setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
- else
- setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
- } else if (isInteger(DestVT)) { // FP -> Int cast.
- if (I.getType()->isSigned())
- setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
- else
- setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
- } else {
- assert(0 && "Unknown cast!");
- }
- } else {
- assert(SrcVT == MVT::Vector && "Unknown cast!");
- assert(DestVT != MVT::Vector && "Casts to vector already handled!");
- // This is a cast from a vector to something else. This is always a bit
- // convert. Get information about the input vector.
+ return;
+ }
+ MVT::ValueType SrcVT = N.getValueType();
+ if (SrcVT == MVT::Vector) {
+ // This is a cast from a vctor to something else.
+ // Get information about the input vector.
setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
+ return;
}
+
+ // BitCast assures us that source and destination are the same size so this
+ // is either a BIT_CONVERT or a no-op.
+ if (DestVT != N.getValueType())
+ setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
+ else
+ setValue(&I, N); // noop cast.
}
void SelectionDAGLowering::visitInsertElement(User &I) {
void SelectionDAGLowering::visitGetElementPtr(User &I) {
SDOperand N = getValue(I.getOperand(0));
const Type *Ty = I.getOperand(0)->getType();
- const Type *UIntPtrTy = TD->getIntPtrType();
for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
OI != E; ++OI) {
Value *Idx = *OI;
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
- unsigned Field = cast<ConstantUInt>(Idx)->getValue();
+ unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
if (Field) {
// N = N + Offset
uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
// If this is a constant subscript, handle it quickly.
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
- if (CI->getRawValue() == 0) continue;
-
+ if (CI->getZExtValue() == 0) continue;
uint64_t Offs;
- if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
- Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
+ if (CI->getType()->isSigned())
+ Offs = (int64_t)
+ TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
else
- Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
+ Offs =
+ TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getZExtValue();
N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
continue;
}
getIntPtrConstant(~(uint64_t)(StackAlign-1)));
}
- std::vector<MVT::ValueType> VTs;
- VTs.push_back(AllocSize.getValueType());
- VTs.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- Ops.push_back(AllocSize);
- Ops.push_back(getIntPtrConstant(Align));
- SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
+ SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
+ const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
+ MVT::Other);
+ SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
DAG.setRoot(setValue(&I, DSA).getValue(1));
// Inform the Frame Information that we have just allocated a variable-sized
Root = DAG.getRoot();
}
- setValue(&I, getLoadFrom(I.getType(), Ptr, DAG.getSrcValue(I.getOperand(0)),
+ setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
Root, I.isVolatile()));
}
SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
- SDOperand SrcValue, SDOperand Root,
+ const Value *SV, SDOperand Root,
bool isVolatile) {
SDOperand L;
if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
- L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr, SrcValue);
+ L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
+ DAG.getSrcValue(SV));
} else {
- L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SrcValue);
+ L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, isVolatile);
}
if (isVolatile)
Value *SrcV = I.getOperand(0);
SDOperand Src = getValue(SrcV);
SDOperand Ptr = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
- DAG.getSrcValue(I.getOperand(1))));
+ DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
+ I.isVolatile()));
}
/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
// Build the operand list.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
if (HasChain) { // If this intrinsic has side-effects, chainify it.
if (OnlyLoad) {
// We don't need to serialize loads against other loads.
if (HasChain)
VTs.push_back(MVT::Other);
+ const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
+
// Create the node.
SDOperand Result;
if (!HasChain)
- Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
+ Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
+ &Ops[0], Ops.size());
else if (I.getType() != Type::VoidTy)
- Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
+ Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
+ &Ops[0], Ops.size());
else
- Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
+ Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
+ &Ops[0], Ops.size());
if (HasChain) {
SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
case Intrinsic::setjmp:
- return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
+ return "_setjmp"+!TLI.usesUnderscoreSetJmp();
break;
case Intrinsic::longjmp:
- return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
+ return "_longjmp"+!TLI.usesUnderscoreLongJmp();
break;
case Intrinsic::memcpy_i32:
case Intrinsic::memcpy_i64:
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
- std::vector<SDOperand> Ops;
+ SDOperand Ops[5];
- Ops.push_back(getRoot());
- Ops.push_back(getValue(SPI.getLineValue()));
- Ops.push_back(getValue(SPI.getColumnValue()));
+ Ops[0] = getRoot();
+ Ops[1] = getValue(SPI.getLineValue());
+ Ops[2] = getValue(SPI.getColumnValue());
DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
assert(DD && "Not a debug information descriptor");
CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
- Ops.push_back(DAG.getString(CompileUnit->getFileName()));
- Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
+ Ops[3] = DAG.getString(CompileUnit->getFileName());
+ Ops[4] = DAG.getString(CompileUnit->getDirectory());
- DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
}
return 0;
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
- std::vector<SDOperand> Ops;
-
unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
-
- Ops.push_back(getRoot());
- Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
+ DAG.getConstant(LabelID, MVT::i32)));
}
return 0;
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
- std::vector<SDOperand> Ops;
-
unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
-
- Ops.push_back(getRoot());
- Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+ getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
return 0;
DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
if (DebugInfo && FSI.getSubprogram() &&
DebugInfo->Verify(FSI.getSubprogram())) {
- std::vector<SDOperand> Ops;
-
unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
-
- Ops.push_back(getRoot());
- Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+ getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
return 0;
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
- std::vector<SDOperand> Ops;
-
SDOperand AddressOp = getValue(DI.getAddress());
- if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
+ if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
- }
}
return 0;
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
+ case Intrinsic::powi_f32:
+ case Intrinsic::powi_f64:
+ setValue(&I, DAG.getNode(ISD::FPOWI,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1)),
+ getValue(I.getOperand(2))));
+ return 0;
case Intrinsic::pcmarker: {
SDOperand Tmp = getValue(I.getOperand(1));
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
- std::vector<MVT::ValueType> VTs;
- VTs.push_back(MVT::i64);
- VTs.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
+ SDOperand Op = getRoot();
+ SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
+ DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
+ &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
getValue(I.getOperand(1))));
return 0;
case Intrinsic::stacksave: {
- std::vector<MVT::ValueType> VTs;
- VTs.push_back(TLI.getPointerTy());
- VTs.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
+ SDOperand Op = getRoot();
+ SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
+ DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
assert(Regs.size() == 2 &&
"Cannot expand to more than 2 elts yet!");
SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
- Chain = Val.getValue(1);
- Flag = Val.getValue(2);
+ Chain = Hi.getValue(1);
+ Flag = Hi.getValue(2);
if (DAG.getTargetLoweringInfo().isLittleEndian())
return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
else
return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
}
- // Otherwise, if the return value was promoted, truncate it to the
+ // Otherwise, if the return value was promoted or extended, truncate it to the
// appropriate type.
if (RegVT == ValueVT)
return Val;
- if (MVT::isInteger(RegVT))
- return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
- else
+ if (MVT::isInteger(RegVT)) {
+ if (ValueVT < RegVT)
+ return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
+ else
+ return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
+ } else {
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
+ }
}
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
/// specified value into the registers specified by this object. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag.
void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
- SDOperand &Chain, SDOperand &Flag) const {
+ SDOperand &Chain, SDOperand &Flag,
+ MVT::ValueType PtrVT) const {
if (Regs.size() == 1) {
// If there is a single register and the types differ, this must be
// a promotion.
if (RegVT != ValueVT) {
- if (MVT::isInteger(RegVT))
- Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
- else
+ if (MVT::isInteger(RegVT)) {
+ if (RegVT < ValueVT)
+ Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
+ else
+ Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
+ } else
Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
}
Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
for (unsigned i = 0, e = R.size(); i != e; ++i) {
SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
- DAG.getConstant(i, MVT::i32));
+ DAG.getConstant(i, PtrVT));
Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
Flag = Chain.getValue(1);
}
MVT::ValueType RegVT;
MVT::ValueType ValueVT = VT;
+ // If this is a constraint for a specific physical register, like {r17},
+ // assign it now.
if (PhysReg.first) {
if (VT == MVT::Other)
ValueVT = *PhysReg.second->vt_begin();
- RegVT = VT;
+
+ // Get the actual register value type. This is important, because the user
+ // may have asked for (e.g.) the AX register in i32 type. We need to
+ // remember that AX is actually i16 to get the right extension.
+ RegVT = *PhysReg.second->vt_begin();
// This is a explicit reference to a physical register.
Regs.push_back(PhysReg.first);
// If this is an expanded reference, add the rest of the regs to Regs.
if (NumRegs != 1) {
- RegVT = *PhysReg.second->vt_begin();
TargetRegisterClass::iterator I = PhysReg.second->begin();
TargetRegisterClass::iterator E = PhysReg.second->end();
for (; *I != PhysReg.first; ++I)
return RegsForValue(Regs, RegVT, ValueVT);
}
- // This is a reference to a register class. Allocate NumRegs consecutive,
- // available, registers from the class.
- std::vector<unsigned> RegClassRegs =
- TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
+ // Otherwise, if this was a reference to an LLVM register class, create vregs
+ // for this reference.
+ std::vector<unsigned> RegClassRegs;
+ if (PhysReg.second) {
+ // If this is an early clobber or tied register, our regalloc doesn't know
+ // how to maintain the constraint. If it isn't, go ahead and create vreg
+ // and let the regalloc do the right thing.
+ if (!isOutReg || !isInReg) {
+ if (VT == MVT::Other)
+ ValueVT = *PhysReg.second->vt_begin();
+ RegVT = *PhysReg.second->vt_begin();
+
+ // Create the appropriate number of virtual registers.
+ SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
+ for (; NumRegs; --NumRegs)
+ Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
+
+ return RegsForValue(Regs, RegVT, ValueVT);
+ }
+
+ // Otherwise, we can't allocate it. Let the code below figure out how to
+ // maintain these constraints.
+ RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
+
+ } else {
+ // This is a reference to a register class that doesn't directly correspond
+ // to an LLVM register class. Allocate NumRegs consecutive, available,
+ // registers from the class.
+ RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
+ }
const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
MachineFunction &MF = *CurMBB->getParent();
SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
MVT::Other);
- // Note, we treat inline asms both with and without side-effects as the same.
- // If an inline asm doesn't have side effects and doesn't access memory, we
- // could not choose to not chain it.
- bool hasSideEffects = IA->hasSideEffects();
-
std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
std::vector<MVT::ValueType> ConstraintVTs;
GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
true, UsesInputRegister,
OutputRegs, InputRegs);
- assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
+ if (Regs.Regs.empty()) {
+ cerr << "Couldn't allocate output reg for contraint '"
+ << ConstraintCode << "'!\n";
+ exit(1);
+ }
if (!Constraints[i].isIndirectOutput) {
assert(RetValRegs.Regs.empty() &&
// Advance to the next operand.
unsigned NumOps =
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
- assert((NumOps & 7) == 2 /*REGDEF*/ &&
+ assert(((NumOps & 7) == 2 /*REGDEF*/ ||
+ (NumOps & 7) == 4 /*MEM*/) &&
"Skipped past definitions?");
CurOp += (NumOps>>3)+1;
}
}
// Use the produced MatchedRegs object to
- MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
+ MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
+ TLI.getPointerTy());
MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
break;
}
CTy = TLI.getConstraintType(ConstraintCode[0]);
if (CTy == TargetLowering::C_Other) {
- if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
- assert(0 && "MATCH FAIL!");
+ InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
+ ConstraintCode[0], DAG);
+ if (!InOperandVal.Val) {
+ cerr << "Invalid operand for inline asm constraint '"
+ << ConstraintCode << "'!\n";
+ exit(1);
+ }
// Add information to the INLINEASM node to know about this input.
unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
// FIXME: should be match fail.
assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
- InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag);
+ InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
break;
AsmNodeOperands[0] = Chain;
if (Flag.Val) AsmNodeOperands.push_back(Flag);
- std::vector<MVT::ValueType> VTs;
- VTs.push_back(MVT::Other);
- VTs.push_back(MVT::Flag);
- Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
+ Chain = DAG.getNode(ISD::INLINEASM,
+ DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
+ &AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
// If this asm returns a register value, copy the result from that register
}
// Emit the non-flagged stores from the physregs.
- std::vector<SDOperand> OutChains;
+ SmallVector<SDOperand, 8> OutChains;
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
- OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- StoresToEmit[i].first,
+ OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
getValue(StoresToEmit[i].second),
- DAG.getSrcValue(StoresToEmit[i].second)));
+ StoresToEmit[i].second, 0));
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
// basic blocks, and the scheduler passes ownership of it to this method.
MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB) {
- std::cerr << "If a target marks an instruction with "
- "'usesCustomDAGSchedInserter', it must implement "
- "TargetLowering::InsertAtEndOfBasicBlock!\n";
+ cerr << "If a target marks an instruction with "
+ << "'usesCustomDAGSchedInserter', it must implement "
+ << "TargetLowering::InsertAtEndOfBasicBlock!\n";
abort();
return 0;
}
DAG.getSrcValue(I.getOperand(2))));
}
+/// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either
+/// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate.
+static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg,
+ unsigned &i, SelectionDAG &DAG,
+ TargetLowering &TLI) {
+ if (TLI.getTypeAction(VT) != TargetLowering::Expand)
+ return SDOperand(Arg, i++);
+
+ MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
+ unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
+ if (NumVals == 1) {
+ return DAG.getNode(ISD::BIT_CONVERT, VT,
+ ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI));
+ } else if (NumVals == 2) {
+ SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
+ SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
+ if (!TLI.isLittleEndian())
+ std::swap(Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
+ } else {
+ // Value scalarized into many values. Unimp for now.
+ assert(0 && "Cannot expand i64 -> i16 yet!");
+ }
+ return SDOperand();
+}
+
/// TargetLowering::LowerArguments - This is the default LowerArguments
/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
-/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be removed.
+/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
+/// integrated into SDISel.
std::vector<SDOperand>
TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
std::vector<SDOperand> Ops;
+ Ops.push_back(DAG.getRoot());
Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
// If this is a large integer, it needs to be broken up into small
// integers. Figure out what the destination type is and how many small
// integers it turns into.
- MVT::ValueType NVT = getTypeToTransformTo(VT);
- unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
+ MVT::ValueType NVT = getTypeToExpandTo(VT);
+ unsigned NumVals = getNumElements(VT);
for (unsigned i = 0; i != NumVals; ++i)
RetVals.push_back(NVT);
} else {
}
}
- if (RetVals.size() == 0)
- RetVals.push_back(MVT::isVoid);
+ RetVals.push_back(MVT::Other);
// Create the node.
- SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
+ SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
+ DAG.getNodeValueTypes(RetVals), RetVals.size(),
+ &Ops[0], Ops.size()).Val;
+
+ DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
// Set up the return result vector.
Ops.clear();
}
case Expand:
if (VT != MVT::Vector) {
- // If this is a large integer, it needs to be reassembled from small
- // integers. Figure out what the source elt type is and how many small
- // integers it is.
- MVT::ValueType NVT = getTypeToTransformTo(VT);
- unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
- if (NumVals == 2) {
- SDOperand Lo = SDOperand(Result, i++);
- SDOperand Hi = SDOperand(Result, i++);
-
- if (!isLittleEndian())
- std::swap(Lo, Hi);
-
- Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
- } else {
- // Value scalarized into many values. Unimp for now.
- assert(0 && "Cannot expand i64 -> i16 yet!");
- }
+ // If this is a large integer or a floating point node that needs to be
+ // expanded, it needs to be reassembled from small integers. Figure out
+ // what the source elt type is and how many small integers it is.
+ Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this));
} else {
// Otherwise, this is a vector type. We only support legal vectors
// right now.
if (TVT != MVT::Other && isTypeLegal(TVT)) {
SDOperand N = SDOperand(Result, i++);
// Handle copies from generic vectors to registers.
- MVT::ValueType PTyElementVT, PTyLegalElementVT;
- unsigned NE = getPackedTypeBreakdown(PTy, PTyElementVT,
- PTyLegalElementVT);
- // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
- // "N x PTyElementVT" MVT::Vector type.
N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
- DAG.getConstant(NE, MVT::i32),
- DAG.getValueType(PTyElementVT));
+ DAG.getConstant(NumElems, MVT::i32),
+ DAG.getValueType(getValueType(EltTy)));
Ops.push_back(N);
} else {
assert(0 && "Don't support illegal by-val vector arguments yet!");
+ abort();
}
}
break;
return Ops;
}
+
+/// ExpandScalarCallArgs - Recursively expand call argument node by
+/// bit_converting it or extract a pair of elements from the larger node.
+static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg,
+ bool isSigned,
+ SmallVector<SDOperand, 32> &Ops,
+ SelectionDAG &DAG,
+ TargetLowering &TLI) {
+ if (TLI.getTypeAction(VT) != TargetLowering::Expand) {
+ Ops.push_back(Arg);
+ Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
+ return;
+ }
+
+ MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
+ unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
+ if (NumVals == 1) {
+ Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg);
+ ExpandScalarCallArgs(EVT, Arg, isSigned, Ops, DAG, TLI);
+ } else if (NumVals == 2) {
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
+ DAG.getConstant(0, TLI.getPointerTy()));
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
+ DAG.getConstant(1, TLI.getPointerTy()));
+ if (!TLI.isLittleEndian())
+ std::swap(Lo, Hi);
+ ExpandScalarCallArgs(EVT, Lo, isSigned, Ops, DAG, TLI);
+ ExpandScalarCallArgs(EVT, Hi, isSigned, Ops, DAG, TLI);
+ } else {
+ // Value scalarized into many values. Unimp for now.
+ assert(0 && "Cannot expand i64 -> i16 yet!");
+ }
+}
+
+/// TargetLowering::LowerCallTo - This is the default LowerCallTo
+/// implementation, which just inserts an ISD::CALL node, which is later custom
+/// lowered by the target to something concrete. FIXME: When all targets are
+/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
+std::pair<SDOperand, SDOperand>
+TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
+ unsigned CallingConv, bool isTailCall,
+ SDOperand Callee,
+ ArgListTy &Args, SelectionDAG &DAG) {
+ SmallVector<SDOperand, 32> Ops;
+ Ops.push_back(Chain); // Op#0 - Chain
+ Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
+ Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
+ Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
+ Ops.push_back(Callee);
+
+ // Handle all of the outgoing arguments.
+ for (unsigned i = 0, e = Args.size(); i != e; ++i) {
+ MVT::ValueType VT = getValueType(Args[i].second);
+ SDOperand Op = Args[i].first;
+ bool isSigned = Args[i].second->isSigned();
+ switch (getTypeAction(VT)) {
+ default: assert(0 && "Unknown type action!");
+ case Legal:
+ Ops.push_back(Op);
+ Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
+ break;
+ case Promote:
+ if (MVT::isInteger(VT)) {
+ unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
+ Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
+ } else {
+ assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
+ Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
+ }
+ Ops.push_back(Op);
+ Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
+ break;
+ case Expand:
+ if (VT != MVT::Vector) {
+ // If this is a large integer, it needs to be broken down into small
+ // integers. Figure out what the source elt type is and how many small
+ // integers it is.
+ ExpandScalarCallArgs(VT, Op, isSigned, Ops, DAG, *this);
+ } else {
+ // Otherwise, this is a vector type. We only support legal vectors
+ // right now.
+ const PackedType *PTy = cast<PackedType>(Args[i].second);
+ unsigned NumElems = PTy->getNumElements();
+ const Type *EltTy = PTy->getElementType();
+
+ // Figure out if there is a Packed type corresponding to this Vector
+ // type. If so, convert to the packed type.
+ MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
+ if (TVT != MVT::Other && isTypeLegal(TVT)) {
+ // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
+ Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
+ Ops.push_back(Op);
+ Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
+ } else {
+ assert(0 && "Don't support illegal by-val vector call args yet!");
+ abort();
+ }
+ }
+ break;
+ }
+ }
+
+ // Figure out the result value types.
+ SmallVector<MVT::ValueType, 4> RetTys;
+
+ if (RetTy != Type::VoidTy) {
+ MVT::ValueType VT = getValueType(RetTy);
+ switch (getTypeAction(VT)) {
+ default: assert(0 && "Unknown type action!");
+ case Legal:
+ RetTys.push_back(VT);
+ break;
+ case Promote:
+ RetTys.push_back(getTypeToTransformTo(VT));
+ break;
+ case Expand:
+ if (VT != MVT::Vector) {
+ // If this is a large integer, it needs to be reassembled from small
+ // integers. Figure out what the source elt type is and how many small
+ // integers it is.
+ MVT::ValueType NVT = getTypeToExpandTo(VT);
+ unsigned NumVals = getNumElements(VT);
+ for (unsigned i = 0; i != NumVals; ++i)
+ RetTys.push_back(NVT);
+ } else {
+ // Otherwise, this is a vector type. We only support legal vectors
+ // right now.
+ const PackedType *PTy = cast<PackedType>(RetTy);
+ unsigned NumElems = PTy->getNumElements();
+ const Type *EltTy = PTy->getElementType();
+
+ // Figure out if there is a Packed type corresponding to this Vector
+ // type. If so, convert to the packed type.
+ MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
+ if (TVT != MVT::Other && isTypeLegal(TVT)) {
+ RetTys.push_back(TVT);
+ } else {
+ assert(0 && "Don't support illegal by-val vector call results yet!");
+ abort();
+ }
+ }
+ }
+ }
+
+ RetTys.push_back(MVT::Other); // Always has a chain.
+
+ // Finally, create the CALL node.
+ SDOperand Res = DAG.getNode(ISD::CALL,
+ DAG.getVTList(&RetTys[0], RetTys.size()),
+ &Ops[0], Ops.size());
+
+ // This returns a pair of operands. The first element is the
+ // return value for the function (if RetTy is not VoidTy). The second
+ // element is the outgoing token chain.
+ SDOperand ResVal;
+ if (RetTys.size() != 1) {
+ MVT::ValueType VT = getValueType(RetTy);
+ if (RetTys.size() == 2) {
+ ResVal = Res;
+
+ // If this value was promoted, truncate it down.
+ if (ResVal.getValueType() != VT) {
+ if (VT == MVT::Vector) {
+ // Insert a VBITCONVERT to convert from the packed result type to the
+ // MVT::Vector type.
+ unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
+ const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
+
+ // Figure out if there is a Packed type corresponding to this Vector
+ // type. If so, convert to the packed type.
+ MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
+ if (TVT != MVT::Other && isTypeLegal(TVT)) {
+ // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
+ // "N x PTyElementVT" MVT::Vector type.
+ ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
+ DAG.getConstant(NumElems, MVT::i32),
+ DAG.getValueType(getValueType(EltTy)));
+ } else {
+ abort();
+ }
+ } else if (MVT::isInteger(VT)) {
+ unsigned AssertOp = RetTy->isSigned() ?
+ ISD::AssertSext : ISD::AssertZext;
+ ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
+ DAG.getValueType(VT));
+ ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
+ } else {
+ assert(MVT::isFloatingPoint(VT));
+ if (getTypeAction(VT) == Expand)
+ ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
+ else
+ ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
+ }
+ }
+ } else if (RetTys.size() == 3) {
+ ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
+ Res.getValue(0), Res.getValue(1));
+
+ } else {
+ assert(0 && "Case not handled yet!");
+ }
+ }
+
+ return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
+}
+
+
+
// It is always conservatively correct for llvm.returnaddress and
// llvm.frameaddress to return 0.
+//
+// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
+// expanded to 0 if the target wants.
std::pair<SDOperand, SDOperand>
TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
unsigned Depth, SelectionDAG &DAG) {
}
void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
- unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
+ unsigned Depth = (unsigned)cast<ConstantInt>(I.getOperand(1))->getZExtValue();
std::pair<SDOperand,SDOperand> Result =
TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
setValue(&I, Result.first);
static SDOperand getMemsetStringVal(MVT::ValueType VT,
SelectionDAG &DAG, TargetLowering &TLI,
std::string &Str, unsigned Offset) {
- MVT::ValueType CurVT = VT;
uint64_t Val = 0;
unsigned MSB = getSizeInBits(VT) / 8;
if (TLI.isLittleEndian())
Offset = Offset + MSB - 1;
for (unsigned i = 0; i != MSB; ++i) {
- Val = (Val << 8) | Str[Offset];
+ Val = (Val << 8) | (unsigned char)Str[Offset];
Offset += TLI.isLittleEndian() ? -1 : 1;
}
return DAG.getConstant(Val, VT);
// Expand memset / memcpy to a series of load / store ops
// if the size operand falls below a certain threshold.
- std::vector<SDOperand> OutChains;
+ SmallVector<SDOperand, 8> OutChains;
switch (Op) {
default: break; // Do nothing for now.
case ISD::MEMSET: {
MVT::ValueType VT = MemOps[i];
unsigned VTSize = getSizeInBits(VT) / 8;
SDOperand Value = getMemsetValue(Op2, VT, DAG);
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
- Value,
+ SDOperand Store = DAG.getStore(getRoot(), Value,
getMemBasePlusOffset(Op1, Offset, DAG, TLI),
- DAG.getSrcValue(I.getOperand(1), Offset));
+ I.getOperand(1), Offset);
OutChains.push_back(Store);
Offset += VTSize;
}
}
if (G) {
GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
- if (GV) {
+ if (GV && GV->isConstant()) {
Str = GV->getStringValue(false);
if (!Str.empty()) {
CopyFromStr = true;
Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
Chain = getRoot();
Store =
- DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
- getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
- DAG.getSrcValue(I.getOperand(1), DstOff));
+ DAG.getStore(Chain, Value,
+ getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
+ I.getOperand(1), DstOff);
} else {
Value = DAG.getLoad(VT, getRoot(),
getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
- DAG.getSrcValue(I.getOperand(2), SrcOff));
+ I.getOperand(2), SrcOff);
Chain = Value.getValue(1);
Store =
- DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
- getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
- DAG.getSrcValue(I.getOperand(1), DstOff));
+ DAG.getStore(Chain, Value,
+ getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
+ I.getOperand(1), DstOff);
}
OutChains.push_back(Store);
SrcOff += VTSize;
}
if (!OutChains.empty()) {
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &OutChains[0], OutChains.size()));
return;
}
}
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
}
//===----------------------------------------------------------------------===//
void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
// FIXME: we only modify the CFG to split critical edges. This
// updates dom and loop info.
+ AU.addRequired<AliasAnalysis>();
}
-/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
-/// casting to the type of GEPI.
-static Value *InsertGEPComputeCode(Value *&V, BasicBlock *BB, Instruction *GEPI,
- Value *Ptr, Value *PtrOffset) {
- if (V) return V; // Already computed.
-
- BasicBlock::iterator InsertPt;
- if (BB == GEPI->getParent()) {
- // If insert into the GEP's block, insert right after the GEP.
- InsertPt = GEPI;
- ++InsertPt;
- } else {
- // Otherwise, insert at the top of BB, after any PHI nodes
- InsertPt = BB->begin();
- while (isa<PHINode>(InsertPt)) ++InsertPt;
- }
-
- // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
- // BB so that there is only one value live across basic blocks (the cast
- // operand).
- if (CastInst *CI = dyn_cast<CastInst>(Ptr))
- if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
- Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
-
- // Add the offset, cast it to the right type.
- Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
- Ptr = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
- return V = Ptr;
-}
-
/// OptimizeNoopCopyExpression - We have determined that the specified cast
/// instruction is a noop copy (e.g. it's casting from one pointer type to
/// another, int->uint, or int->sbyte on PPC.
-static void OptimizeNoopCopyExpression(CastInst *CI) {
+///
+/// Return true if any changes are made.
+static bool OptimizeNoopCopyExpression(CastInst *CI) {
BasicBlock *DefBB = CI->getParent();
/// InsertedCasts - Only insert a cast in each block once.
std::map<BasicBlock*, CastInst*> InsertedCasts;
+ bool MadeChange = false;
for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
UI != E; ) {
Use &TheUse = UI.getUse();
while (isa<PHINode>(InsertPt)) ++InsertPt;
InsertedCast =
- new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
+ CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
+ InsertPt);
+ MadeChange = true;
}
// Replace a use of the cast with a use of the new casat.
TheUse = InsertedCast;
}
+
+ // If we removed all uses, nuke the cast.
+ if (CI->use_empty())
+ CI->eraseFromParent();
+
+ return MadeChange;
}
+/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
+/// casting to the type of GEPI.
+static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
+ Instruction *GEPI, Value *Ptr,
+ Value *PtrOffset) {
+ if (V) return V; // Already computed.
+
+ // Figure out the insertion point
+ BasicBlock::iterator InsertPt;
+ if (BB == GEPI->getParent()) {
+ // If GEP is already inserted into BB, insert right after the GEP.
+ InsertPt = GEPI;
+ ++InsertPt;
+ } else {
+ // Otherwise, insert at the top of BB, after any PHI nodes
+ InsertPt = BB->begin();
+ while (isa<PHINode>(InsertPt)) ++InsertPt;
+ }
+
+ // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
+ // BB so that there is only one value live across basic blocks (the cast
+ // operand).
+ if (CastInst *CI = dyn_cast<CastInst>(Ptr))
+ if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
+ Ptr = CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(),
+ "", InsertPt);
+
+ // Add the offset, cast it to the right type.
+ Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
+ // Ptr is an integer type, GEPI is pointer type ==> IntToPtr
+ return V = CastInst::create(Instruction::IntToPtr, Ptr, GEPI->getType(),
+ "", InsertPt);
+}
+
+/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
+/// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
+/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
+/// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
+/// sink PtrOffset into user blocks where doing so will likely allow us to fold
+/// the constant add into a load or store instruction. Additionally, if a user
+/// is a pointer-pointer cast, we look through it to find its users.
+static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
+ Constant *PtrOffset, BasicBlock *DefBB,
+ GetElementPtrInst *GEPI,
+ std::map<BasicBlock*,Instruction*> &InsertedExprs) {
+ while (!RepPtr->use_empty()) {
+ Instruction *User = cast<Instruction>(RepPtr->use_back());
+
+ // If the user is a Pointer-Pointer cast, recurse. Only BitCast can be
+ // used for a Pointer-Pointer cast.
+ if (isa<BitCastInst>(User)) {
+ ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
+
+ // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
+ // could invalidate an iterator.
+ User->setOperand(0, UndefValue::get(RepPtr->getType()));
+ continue;
+ }
+
+ // If this is a load of the pointer, or a store through the pointer, emit
+ // the increment into the load/store block.
+ Instruction *NewVal;
+ if (isa<LoadInst>(User) ||
+ (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
+ NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
+ User->getParent(), GEPI,
+ Ptr, PtrOffset);
+ } else {
+ // If this use is not foldable into the addressing mode, use a version
+ // emitted in the GEP block.
+ NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
+ Ptr, PtrOffset);
+ }
+
+ if (GEPI->getType() != RepPtr->getType()) {
+ BasicBlock::iterator IP = NewVal;
+ ++IP;
+ // NewVal must be a GEP which must be pointer type, so BitCast
+ NewVal = new BitCastInst(NewVal, RepPtr->getType(), "", IP);
+ }
+ User->replaceUsesOfWith(RepPtr, NewVal);
+ }
+}
+
+
/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
/// selection, we want to be a bit careful about some things. In particular, if
/// we have a GEP instruction that is used in a different block than it is
/// defined, the addressing expression of the GEP cannot be folded into loads or
/// stores that use it. In this case, decompose the GEP and move constant
/// indices into blocks that use it.
-static void OptimizeGEPExpression(GetElementPtrInst *GEPI,
+static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
const TargetData *TD) {
// If this GEP is only used inside the block it is defined in, there is no
// need to rewrite it.
break;
}
}
- if (!isUsedOutsideDefBB) return;
+ if (!isUsedOutsideDefBB) return false;
// If this GEP has no non-zero constant indices, there is nothing we can do,
// ignore it.
bool hasConstantIndex = false;
+ bool hasVariableIndex = false;
for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
E = GEPI->op_end(); OI != E; ++OI) {
- if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI))
- if (CI->getRawValue()) {
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
+ if (CI->getZExtValue()) {
hasConstantIndex = true;
break;
}
+ } else {
+ hasVariableIndex = true;
+ }
+ }
+
+ // If this is a "GEP X, 0, 0, 0", turn this into a cast.
+ if (!hasConstantIndex && !hasVariableIndex) {
+ /// The GEP operand must be a pointer, so must its result -> BitCast
+ Value *NC = new BitCastInst(GEPI->getOperand(0), GEPI->getType(),
+ GEPI->getName(), GEPI);
+ GEPI->replaceAllUsesWith(NC);
+ GEPI->eraseFromParent();
+ return true;
}
+
// If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
- if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0))) return;
+ if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
+ return false;
// Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
// constant offset (which we now know is non-zero) and deal with it later.
uint64_t ConstantOffset = 0;
const Type *UIntPtrTy = TD->getIntPtrType();
- Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
+ Value *Ptr = new PtrToIntInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
const Type *Ty = GEPI->getOperand(0)->getType();
for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
E = GEPI->op_end(); OI != E; ++OI) {
Value *Idx = *OI;
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
- unsigned Field = cast<ConstantUInt>(Idx)->getValue();
+ unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
if (Field)
ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
Ty = StTy->getElementType(Field);
// Handle constant subscripts.
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
- if (CI->getRawValue() == 0) continue;
-
- if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
- ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
+ if (CI->getZExtValue() == 0) continue;
+ if (CI->getType()->isSigned())
+ ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CI->getSExtValue();
else
- ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
+ ConstantOffset += TD->getTypeSize(Ty)*CI->getZExtValue();
continue;
}
// Ptr = Ptr + Idx * ElementSize;
// Cast Idx to UIntPtrTy if needed.
- Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
+ Idx = CastInst::createIntegerCast(Idx, UIntPtrTy, true/*SExt*/, "", GEPI);
uint64_t ElementSize = TD->getTypeSize(Ty);
// Mask off bits that should not be set.
ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
- Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
+ Constant *SizeCst = ConstantInt::get(UIntPtrTy, ElementSize);
// Multiply by the element size and add to the base.
Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
// Make sure that the offset fits in uintptr_t.
ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
- Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
+ Constant *PtrOffset = ConstantInt::get(UIntPtrTy, ConstantOffset);
// Okay, we have now emitted all of the variable index parts to the BB that
// the GEP is defined in. Loop over all of the using instructions, inserting
// block, otherwise we use a canonical version right next to the gep (these
// won't be foldable as addresses, so we might as well share the computation).
- std::map<BasicBlock*,Value*> InsertedExprs;
- while (!GEPI->use_empty()) {
- Instruction *User = cast<Instruction>(GEPI->use_back());
+ std::map<BasicBlock*,Instruction*> InsertedExprs;
+ ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
+
+ // Finally, the GEP is dead, remove it.
+ GEPI->eraseFromParent();
+
+ return true;
+}
- // If this use is not foldable into the addressing mode, use a version
- // emitted in the GEP block.
- Value *NewVal;
- if (!isa<LoadInst>(User) &&
- (!isa<StoreInst>(User) || User->getOperand(0) == GEPI)) {
- NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
- Ptr, PtrOffset);
- } else {
- // Otherwise, insert the code in the User's block so it can be folded into
- // any users in that block.
- NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
- User->getParent(), GEPI,
- Ptr, PtrOffset);
+
+/// SplitEdgeNicely - Split the critical edge from TI to it's specified
+/// successor if it will improve codegen. We only do this if the successor has
+/// phi nodes (otherwise critical edges are ok). If there is already another
+/// predecessor of the succ that is empty (and thus has no phi nodes), use it
+/// instead of introducing a new block.
+static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
+ BasicBlock *TIBB = TI->getParent();
+ BasicBlock *Dest = TI->getSuccessor(SuccNum);
+ assert(isa<PHINode>(Dest->begin()) &&
+ "This should only be called if Dest has a PHI!");
+
+ /// TIPHIValues - This array is lazily computed to determine the values of
+ /// PHIs in Dest that TI would provide.
+ std::vector<Value*> TIPHIValues;
+
+ // Check to see if Dest has any blocks that can be used as a split edge for
+ // this terminator.
+ for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; ++PI) {
+ BasicBlock *Pred = *PI;
+ // To be usable, the pred has to end with an uncond branch to the dest.
+ BranchInst *PredBr = dyn_cast<BranchInst>(Pred->getTerminator());
+ if (!PredBr || !PredBr->isUnconditional() ||
+ // Must be empty other than the branch.
+ &Pred->front() != PredBr)
+ continue;
+
+ // Finally, since we know that Dest has phi nodes in it, we have to make
+ // sure that jumping to Pred will have the same affect as going to Dest in
+ // terms of PHI values.
+ PHINode *PN;
+ unsigned PHINo = 0;
+ bool FoundMatch = true;
+ for (BasicBlock::iterator I = Dest->begin();
+ (PN = dyn_cast<PHINode>(I)); ++I, ++PHINo) {
+ if (PHINo == TIPHIValues.size())
+ TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB));
+
+ // If the PHI entry doesn't work, we can't use this pred.
+ if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) {
+ FoundMatch = false;
+ break;
+ }
+ }
+
+ // If we found a workable predecessor, change TI to branch to Succ.
+ if (FoundMatch) {
+ Dest->removePredecessor(TIBB);
+ TI->setSuccessor(SuccNum, Pred);
+ return;
}
- User->replaceUsesOfWith(GEPI, NewVal);
}
- // Finally, the GEP is dead, remove it.
- GEPI->eraseFromParent();
+ SplitCriticalEdge(TI, SuccNum, P, true);
}
+
bool SelectionDAGISel::runOnFunction(Function &Fn) {
MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
RegMap = MF.getSSARegMap();
- DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
+ DOUT << "\n\n\n=== " << Fn.getName() << "\n";
- // First, split all critical edges for PHI nodes with incoming values that are
- // constants, this way the load of the constant into a vreg will not be placed
- // into MBBs that are used some other way.
+ // First, split all critical edges.
//
// In this pass we also look for GEP and cast instructions that are used
// across basic blocks and rewrite them to improve basic-block-at-a-time
// selection.
//
- //
+ bool MadeChange = true;
+ while (MadeChange) {
+ MadeChange = false;
for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
- PHINode *PN;
- BasicBlock::iterator BBI;
- for (BBI = BB->begin(); (PN = dyn_cast<PHINode>(BBI)); ++BBI)
- for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
- if (isa<Constant>(PN->getIncomingValue(i)))
- SplitCriticalEdge(PN->getIncomingBlock(i), BB);
+ // Split all critical edges where the dest block has a PHI.
+ TerminatorInst *BBTI = BB->getTerminator();
+ if (BBTI->getNumSuccessors() > 1) {
+ for (unsigned i = 0, e = BBTI->getNumSuccessors(); i != e; ++i)
+ if (isa<PHINode>(BBTI->getSuccessor(i)->begin()) &&
+ isCriticalEdge(BBTI, i, true))
+ SplitEdgeNicely(BBTI, i, this);
+ }
+
- for (BasicBlock::iterator E = BB->end(); BBI != E; ) {
+ for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
Instruction *I = BBI++;
- if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
- OptimizeGEPExpression(GEPI, TLI.getTargetData());
+
+ if (CallInst *CI = dyn_cast<CallInst>(I)) {
+ // If we found an inline asm expession, and if the target knows how to
+ // lower it to normal LLVM code, do so now.
+ if (isa<InlineAsm>(CI->getCalledValue()))
+ if (const TargetAsmInfo *TAI =
+ TLI.getTargetMachine().getTargetAsmInfo()) {
+ if (TAI->ExpandInlineAsm(CI))
+ BBI = BB->begin();
+ }
+ } else if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
+ MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
} else if (CastInst *CI = dyn_cast<CastInst>(I)) {
+ // If the source of the cast is a constant, then this should have
+ // already been constant folded. The only reason NOT to constant fold
+ // it is if something (e.g. LSR) was careful to place the constant
+ // evaluation in a block other than then one that uses it (e.g. to hoist
+ // the address of globals out of a loop). If this is the case, we don't
+ // want to forward-subst the cast.
+ if (isa<Constant>(CI->getOperand(0)))
+ continue;
+
// If this is a noop copy, sink it into user blocks to reduce the number
// of virtual registers that must be created and coallesced.
MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
// If, after promotion, these are the same types, this is a noop copy.
if (SrcVT == DstVT)
- OptimizeNoopCopyExpression(CI);
+ MadeChange |= OptimizeNoopCopyExpression(CI);
}
}
}
+ }
FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
return true;
}
-
-SDOperand SelectionDAGISel::
-CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
- SDOperand Op = SDL.getValue(V);
+SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
+ unsigned Reg) {
+ SDOperand Op = getValue(V);
assert((Op.getOpcode() != ISD::CopyFromReg ||
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
"Copy from a reg to the same reg!");
// register use.
MVT::ValueType SrcVT = Op.getValueType();
MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
- SelectionDAG &DAG = SDL.DAG;
if (SrcVT == DestVT) {
- return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+ return DAG.getCopyToReg(getRoot(), Reg, Op);
} else if (SrcVT == MVT::Vector) {
// Handle copies from generic vectors to registers.
MVT::ValueType PTyElementVT, PTyLegalElementVT;
// Loop over all of the elements of the resultant vector,
// VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
// copying them into output registers.
- std::vector<SDOperand> OutChains;
- SDOperand Root = SDL.getRoot();
+ SmallVector<SDOperand, 8> OutChains;
+ SDOperand Root = getRoot();
for (unsigned i = 0; i != NE; ++i) {
SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
- Op, DAG.getConstant(i, MVT::i32));
+ Op, DAG.getConstant(i, TLI.getPointerTy()));
if (PTyElementVT == PTyLegalElementVT) {
// Elements are legal.
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
// Elements are expanded.
// The src value is expanded into multiple registers.
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
- Elt, DAG.getConstant(0, MVT::i32));
+ Elt, DAG.getConstant(0, TLI.getPointerTy()));
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
- Elt, DAG.getConstant(1, MVT::i32));
+ Elt, DAG.getConstant(1, TLI.getPointerTy()));
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
}
}
- return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
- } else if (SrcVT < DestVT) {
+ return DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &OutChains[0], OutChains.size());
+ } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) {
// The src value is promoted to the register.
if (MVT::isFloatingPoint(SrcVT))
Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
else
Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
- return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+ return DAG.getCopyToReg(getRoot(), Reg, Op);
} else {
+ DestVT = TLI.getTypeToExpandTo(SrcVT);
+ unsigned NumVals = TLI.getNumElements(SrcVT);
+ if (NumVals == 1)
+ return DAG.getCopyToReg(getRoot(), Reg,
+ DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
+ assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
// The src value is expanded into multiple registers.
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
- Op, DAG.getConstant(0, MVT::i32));
+ Op, DAG.getConstant(0, TLI.getPointerTy()));
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
- Op, DAG.getConstant(1, MVT::i32));
- Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
+ Op, DAG.getConstant(1, TLI.getPointerTy()));
+ Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
return DAG.getCopyToReg(Op, Reg+1, Hi);
}
}
// whereever we got it to the vreg that other BB's will reference it as.
if (FuncInfo.ValueMap.count(AI)) {
SDOperand Copy =
- CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
+ SDL.CopyValueToVirtualRegister(AI, FuncInfo.ValueMap[AI]);
UnorderedChains.push_back(Copy);
}
}
- // Next, if the function has live ins that need to be copied into vregs,
- // emit the copies now, into the top of the block.
- MachineFunction &MF = SDL.DAG.getMachineFunction();
- if (MF.livein_begin() != MF.livein_end()) {
- SSARegMap *RegMap = MF.getSSARegMap();
- const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
- for (MachineFunction::livein_iterator LI = MF.livein_begin(),
- E = MF.livein_end(); LI != E; ++LI)
- if (LI->second)
- MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
- LI->first, RegMap->getRegClass(LI->second));
- }
-
// Finally, if the target has anything special to do, allow it to do so.
+ // FIXME: this should insert code into the DAG!
EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
}
-
void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
FunctionLoweringInfo &FuncInfo) {
std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
if (VMI != FuncInfo.ValueMap.end())
UnorderedChains.push_back(
- CopyValueToVirtualRegister(SDL, I, VMI->second));
+ SDL.CopyValueToVirtualRegister(I, VMI->second));
}
// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
// BB. As such, the start of the BB might correspond to a different MBB than
// the end.
//
+ TerminatorInst *TI = LLVMBB->getTerminator();
// Emit constants only once even if used by multiple PHI nodes.
std::map<Constant*, unsigned> ConstantsOut;
-
+
+ // Vector bool would be better, but vector<bool> is really slow.
+ std::vector<unsigned char> SuccsHandled;
+ if (TI->getNumSuccessors())
+ SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
+
// Check successor nodes PHI nodes that expect a constant to be available from
// this block.
- TerminatorInst *TI = LLVMBB->getTerminator();
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
BasicBlock *SuccBB = TI->getSuccessor(succ);
- MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
+ if (!isa<PHINode>(SuccBB->begin())) continue;
+ MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
+
+ // If this terminator has multiple identical successors (common for
+ // switches), only handle each succ once.
+ unsigned SuccMBBNo = SuccMBB->getNumber();
+ if (SuccsHandled[SuccMBBNo]) continue;
+ SuccsHandled[SuccMBBNo] = true;
+
+ MachineBasicBlock::iterator MBBI = SuccMBB->begin();
PHINode *PN;
// At this point we know that there is a 1-1 correspondence between LLVM PHI
// nodes and Machine PHI nodes, but the incoming operands have not been
// emitted yet.
for (BasicBlock::iterator I = SuccBB->begin();
- (PN = dyn_cast<PHINode>(I)); ++I)
- if (!PN->use_empty()) {
- unsigned Reg;
- Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
- if (Constant *C = dyn_cast<Constant>(PHIOp)) {
- unsigned &RegOut = ConstantsOut[C];
- if (RegOut == 0) {
- RegOut = FuncInfo.CreateRegForValue(C);
- UnorderedChains.push_back(
- CopyValueToVirtualRegister(SDL, C, RegOut));
- }
- Reg = RegOut;
- } else {
- Reg = FuncInfo.ValueMap[PHIOp];
- if (Reg == 0) {
- assert(isa<AllocaInst>(PHIOp) &&
- FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
- "Didn't codegen value into a register!??");
- Reg = FuncInfo.CreateRegForValue(PHIOp);
- UnorderedChains.push_back(
- CopyValueToVirtualRegister(SDL, PHIOp, Reg));
- }
+ (PN = dyn_cast<PHINode>(I)); ++I) {
+ // Ignore dead phi's.
+ if (PN->use_empty()) continue;
+
+ unsigned Reg;
+ Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
+
+ if (Constant *C = dyn_cast<Constant>(PHIOp)) {
+ unsigned &RegOut = ConstantsOut[C];
+ if (RegOut == 0) {
+ RegOut = FuncInfo.CreateRegForValue(C);
+ UnorderedChains.push_back(
+ SDL.CopyValueToVirtualRegister(C, RegOut));
}
-
- // Remember that this register needs to added to the machine PHI node as
- // the input for this MBB.
- MVT::ValueType VT = TLI.getValueType(PN->getType());
- unsigned NumElements;
- if (VT != MVT::Vector)
- NumElements = TLI.getNumElements(VT);
- else {
- MVT::ValueType VT1,VT2;
- NumElements =
- TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
- VT1, VT2);
+ Reg = RegOut;
+ } else {
+ Reg = FuncInfo.ValueMap[PHIOp];
+ if (Reg == 0) {
+ assert(isa<AllocaInst>(PHIOp) &&
+ FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
+ "Didn't codegen value into a register!??");
+ Reg = FuncInfo.CreateRegForValue(PHIOp);
+ UnorderedChains.push_back(
+ SDL.CopyValueToVirtualRegister(PHIOp, Reg));
}
- for (unsigned i = 0, e = NumElements; i != e; ++i)
- PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
}
+
+ // Remember that this register needs to added to the machine PHI node as
+ // the input for this MBB.
+ MVT::ValueType VT = TLI.getValueType(PN->getType());
+ unsigned NumElements;
+ if (VT != MVT::Vector)
+ NumElements = TLI.getNumElements(VT);
+ else {
+ MVT::ValueType VT1,VT2;
+ NumElements =
+ TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
+ VT1, VT2);
+ }
+ for (unsigned i = 0, e = NumElements; i != e; ++i)
+ PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
+ }
}
ConstantsOut.clear();
if (i == e)
UnorderedChains.push_back(Root);
}
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &UnorderedChains[0], UnorderedChains.size()));
}
// Lower the terminator after the copies are emitted.
}
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
+ // Get alias analysis for load/store combining.
+ AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
+
// Run the DAG combiner in pre-legalize mode.
- DAG.Combine(false);
+ DAG.Combine(false, AA);
- DEBUG(std::cerr << "Lowered selection DAG:\n");
+ DOUT << "Lowered selection DAG:\n";
DEBUG(DAG.dump());
// Second step, hack on the DAG until it only uses operations and types that
// the target supports.
DAG.Legalize();
- DEBUG(std::cerr << "Legalized selection DAG:\n");
+ DOUT << "Legalized selection DAG:\n";
DEBUG(DAG.dump());
// Run the DAG combiner in post-legalize mode.
- DAG.Combine(true);
+ DAG.Combine(true, AA);
if (ViewISelDAGs) DAG.viewGraph();
// code to the MachineBasicBlock.
InstructionSelectBasicBlock(DAG);
- DEBUG(std::cerr << "Selected machine code:\n");
+ DOUT << "Selected machine code:\n";
DEBUG(BB->dump());
}
MachineInstr *PHI = PHINodesToUpdate[i].first;
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
- PHI->addRegOperand(PHINodesToUpdate[i].second);
+ PHI->addRegOperand(PHINodesToUpdate[i].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
return;
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
if (PHIBB == JT.Default) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(RangeBB);
}
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
}
return;
}
+ // If the switch block involved a branch to one of the actual successors, we
+ // need to update PHI nodes in that block.
+ for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
+ MachineInstr *PHI = PHINodesToUpdate[i].first;
+ assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
+ "This is not a machine PHI node that we are updating!");
+ if (BB->isSuccessor(PHI->getParent())) {
+ PHI->addRegOperand(PHINodesToUpdate[i].second, false);
+ PHI->addMachineBasicBlockOperand(BB);
+ }
+ }
+
// If we generated any switch lowering information, build and codegen any
// additional DAGs necessary.
- for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
+ for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
CurDAG = &SDAG;
SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
+
// Set the current basic block to the mbb we wish to insert the code into
BB = SwitchCases[i].ThisBB;
SDL.setCurrentBasicBlock(BB);
+
// Emit the code
SDL.visitSwitchCase(SwitchCases[i]);
SDAG.setRoot(SDL.getRoot());
CodeGenAndEmitDAG(SDAG);
- // Iterate over the phi nodes, if there is a phi node in a successor of this
- // block (for instance, the default block), then add a pair of operands to
- // the phi node for this block, as if we were coming from the original
- // BB before switch expansion.
- for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
- MachineInstr *PHI = PHINodesToUpdate[pi].first;
- MachineBasicBlock *PHIBB = PHI->getParent();
- assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
- "This is not a machine PHI node that we are updating!");
- if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
- PHI->addMachineBasicBlockOperand(BB);
+
+ // Handle any PHI nodes in successors of this chunk, as if we were coming
+ // from the original BB before switch expansion. Note that PHI nodes can
+ // occur multiple times in PHINodesToUpdate. We have to be very careful to
+ // handle them the right number of times.
+ while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
+ for (MachineBasicBlock::iterator Phi = BB->begin();
+ Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
+ // This value for this PHI node is recorded in PHINodesToUpdate, get it.
+ for (unsigned pn = 0; ; ++pn) {
+ assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
+ if (PHINodesToUpdate[pn].first == Phi) {
+ Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
+ Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
+ break;
+ }
+ }
}
+
+ // Don't process RHS if same block as LHS.
+ if (BB == SwitchCases[i].FalseBB)
+ SwitchCases[i].FalseBB = 0;
+
+ // If we haven't handled the RHS, do so now. Otherwise, we're done.
+ SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
+ SwitchCases[i].FalseBB = 0;
}
+ assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
}
}
+
//===----------------------------------------------------------------------===//
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
/// target node in the graph.
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
if (ViewSchedDAGs) DAG.viewGraph();
- ScheduleDAG *SL = NULL;
-
- switch (ISHeuristic) {
- default: assert(0 && "Unrecognized scheduling heuristic");
- case defaultScheduling:
- if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
- SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
- else {
- assert(TLI.getSchedulingPreference() ==
- TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
- SL = createBURRListDAGScheduler(DAG, BB);
- }
- break;
- case noScheduling:
- SL = createBFS_DAGScheduler(DAG, BB);
- break;
- case simpleScheduling:
- SL = createSimpleDAGScheduler(false, DAG, BB);
- break;
- case simpleNoItinScheduling:
- SL = createSimpleDAGScheduler(true, DAG, BB);
- break;
- case listSchedulingBURR:
- SL = createBURRListDAGScheduler(DAG, BB);
- break;
- case listSchedulingTD:
- SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
- break;
+
+ RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
+
+ if (!Ctor) {
+ Ctor = ISHeuristic;
+ RegisterScheduler::setDefault(Ctor);
}
+
+ ScheduleDAG *SL = Ctor(this, &DAG, BB);
BB = SL->Run();
delete SL;
}
+
HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
return new HazardRecognizer();
}
+//===----------------------------------------------------------------------===//
+// Helper functions used by the generated instruction selector.
+//===----------------------------------------------------------------------===//
+// Calls to these methods are generated by tblgen.
+
+/// CheckAndMask - The isel is trying to match something like (and X, 255). If
+/// the dag combiner simplified the 255, we still want to match. RHS is the
+/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
+/// specified in the .td file (e.g. 255).
+bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) {
+ uint64_t ActualMask = RHS->getValue();
+ uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
+
+ // If the actual mask exactly matches, success!
+ if (ActualMask == DesiredMask)
+ return true;
+
+ // If the actual AND mask is allowing unallowed bits, this doesn't match.
+ if (ActualMask & ~DesiredMask)
+ return false;
+
+ // Otherwise, the DAG Combiner may have proven that the value coming in is
+ // either already zero or is not demanded. Check for known zero input bits.
+ uint64_t NeededMask = DesiredMask & ~ActualMask;
+ if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
+ return true;
+
+ // TODO: check to see if missing bits are just not demanded.
+
+ // Otherwise, this pattern doesn't match.
+ return false;
+}
+
+/// CheckOrMask - The isel is trying to match something like (or X, 255). If
+/// the dag combiner simplified the 255, we still want to match. RHS is the
+/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
+/// specified in the .td file (e.g. 255).
+bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
+ int64_t DesiredMaskS) {
+ uint64_t ActualMask = RHS->getValue();
+ uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
+
+ // If the actual mask exactly matches, success!
+ if (ActualMask == DesiredMask)
+ return true;
+
+ // If the actual AND mask is allowing unallowed bits, this doesn't match.
+ if (ActualMask & ~DesiredMask)
+ return false;
+
+ // Otherwise, the DAG Combiner may have proven that the value coming in is
+ // either already zero or is not demanded. Check for known zero input bits.
+ uint64_t NeededMask = DesiredMask & ~ActualMask;
+
+ uint64_t KnownZero, KnownOne;
+ getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
+
+ // If all the missing bits in the or are already known to be set, match!
+ if ((NeededMask & KnownOne) == NeededMask)
+ return true;
+
+ // TODO: check to see if missing bits are just not demanded.
+
+ // Otherwise, this pattern doesn't match.
+ return false;
+}
+
+
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
void SelectionDAGISel::
Ops.push_back(InOps[0]); // input chain.
Ops.push_back(InOps[1]); // input asm string.
- const char *AsmStr = cast<ExternalSymbolSDNode>(InOps[1])->getSymbol();
unsigned i = 2, e = InOps.size();
if (InOps[e-1].getValueType() == MVT::Flag)
--e; // Don't process a flag operand if it is here.
// Otherwise, this is a memory operand. Ask the target to select it.
std::vector<SDOperand> SelOps;
if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
- std::cerr << "Could not match memory address. Inline asm failure!\n";
+ cerr << "Could not match memory address. Inline asm failure!\n";
exit(1);
}
// Add this to the output node.
- Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
+ Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
+ MVT::i32));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
i += 2;
}
projects / oota-llvm.git / blobdiff