Handle code gen for the unreachable instruction if it's the only instruction in

[oota-llvm.git] / lib / CodeGen / SelectionDAG / SelectionDAGBuilder.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 458e865a6b3c804c1470007f934031941415a777..1fa887c69e0e8b615edb494e47b80a9a99ba5545 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -796,6 +796,7 @@ void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
 #define HANDLE_INST(NUM, OPCODE, CLASS) \
     case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
 #include "llvm/Instruction.def"
+#undef HANDLE_INST
   }
 
   // Assign the ordering to the freshly created DAG nodes.
@@ -2194,6 +2195,19 @@ void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
                           getValue(I.getAddress())));
 }
 
+void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
+  // If the function consists of a single "unreachable" instruction, emit a
+  // "trap". This prevents the back-ends from generating empty functions or
+  // functions which have a prologue, but no epilogue.
+  const BasicBlock *BB = I.getParent();
+  const Function *F = BB->getParent();
+
+  if (F->size() == 1 && BB->size() == 1 &&
+      isa<UnreachableInst>(BB->getTerminator()))
+      DAG.setRoot(DAG.getNode(ISD::TRAP, getCurDebugLoc(),
+                              MVT::Other, getRoot()));
+}
+
 void SelectionDAGBuilder::visitFSub(const User &I) {
   // -0.0 - X --> fneg
   const Type *Ty = I.getType();