std::vector<SUnit*> Queue;
SF Picker;
unsigned CurQueueId;
- bool isBottomUp;
+ bool TracksRegPressure;
protected:
// SUnits - The SUnits for the current graph.
public:
RegReductionPriorityQueue(MachineFunction &mf,
- bool isbottomup,
+ bool tracksrp,
const TargetInstrInfo *tii,
const TargetRegisterInfo *tri,
const TargetLowering *tli)
- : Picker(this), CurQueueId(0), isBottomUp(isbottomup),
+ : Picker(this), CurQueueId(0), TracksRegPressure(tracksrp),
MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
- unsigned NumRC = TRI->getNumRegClasses();
- RegLimit.resize(NumRC);
- RegPressure.resize(NumRC);
- std::fill(RegLimit.begin(), RegLimit.end(), 0);
- std::fill(RegPressure.begin(), RegPressure.end(), 0);
- for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
- E = TRI->regclass_end(); I != E; ++I)
- RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
+ if (TracksRegPressure) {
+ unsigned NumRC = TRI->getNumRegClasses();
+ RegLimit.resize(NumRC);
+ RegPressure.resize(NumRC);
+ std::fill(RegLimit.begin(), RegLimit.end(), 0);
+ std::fill(RegPressure.begin(), RegPressure.end(), 0);
+ for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
+ E = TRI->regclass_end(); I != E; ++I)
+ RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
+ }
}
void initNodes(std::vector<SUnit> &sunits) {
return false;
}
- void OpenPredLives(SUnit *SU) {
+ void ScheduledNode(SUnit *SU) {
+ if (!TracksRegPressure)
+ return;
+
const SDNode *N = SU->getNode();
if (!N->isMachineOpcode())
return;
else
RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
}
+
+ dumpRegPressure();
}
- void ClosePredLives(SUnit *SU) {
+ void UnscheduledNode(SUnit *SU) {
+ if (!TracksRegPressure)
+ return;
+
const SDNode *N = SU->getNode();
if (!N->isMachineOpcode())
return;
unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
}
- }
- void ScheduledNode(SUnit *SU) {
- if (!TLI || !isBottomUp)
- return;
- OpenPredLives(SU);
- dumpRegPressure();
- }
-
- void UnscheduledNode(SUnit *SU) {
- if (!TLI || !isBottomUp)
- return;
- ClosePredLives(SU);
dumpRegPressure();
}
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
BURegReductionPriorityQueue *PQ =
- new BURegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
+ new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
SrcRegReductionPriorityQueue *PQ =
- new SrcRegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
+ new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
const TargetLowering *TLI = &IS->getTargetLowering();
HybridBURRPriorityQueue *PQ =
- new HybridBURRPriorityQueue(*IS->MF, true, TII, TRI,
+ new HybridBURRPriorityQueue(*IS->MF, RegPressureAware, TII, TRI,
(RegPressureAware ? TLI : 0));
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, true, PQ);
PQ->setScheduleDAG(SD);