#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include <iostream>
using namespace llvm;
-
/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
/// This SUnit graph is similar to the SelectionDAG, but represents flagged
/// together nodes with a single SUnit.
N = *UI;
break;
}
- if (!HasFlagUse) break;
+ if (!HasFlagUse) break;
}
// Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
- if (TII->isTwoAddrInstr(Opc))
- SU->isTwoAddress = true;
+ for (unsigned i = 0, ee = TII->getNumOperands(Opc); i != ee; ++i) {
+ if (TII->getOperandConstraint(Opc, i, TOI::TIED_TO) != -1) {
+ SU->isTwoAddress = true;
+ break;
+ }
+ }
if (TII->isCommutableInstr(Opc))
SU->isCommutable = true;
}
assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
bool isChain = OpVT == MVT::Other;
- if (SU->Preds.insert(std::make_pair(OpSU, isChain)).second) {
+ if (SU->addPred(OpSU, isChain)) {
if (!isChain) {
SU->NumPreds++;
SU->NumPredsLeft++;
SU->NumChainPredsLeft++;
}
}
- if (OpSU->Succs.insert(std::make_pair(SU, isChain)).second) {
+ if (OpSU->addSucc(SU, isChain)) {
if (!isChain) {
OpSU->NumSuccs++;
OpSU->NumSuccsLeft++;
return;
}
-static void CalculateDepths(SUnit *SU, unsigned Depth) {
- if (SU->Depth == 0 || Depth > SU->Depth) {
- SU->Depth = Depth;
- for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Succs.begin(),
- E = SU->Succs.end(); I != E; ++I)
- CalculateDepths(I->first, Depth+1);
+static void CalculateDepths(SUnit &SU, unsigned Depth) {
+ if (SU.Depth == 0 || Depth > SU.Depth) {
+ SU.Depth = Depth;
+ for (SUnit::succ_iterator I = SU.Succs.begin(), E = SU.Succs.end();
+ I != E; ++I)
+ CalculateDepths(*I->first, Depth+1);
}
}
void ScheduleDAG::CalculateDepths() {
SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
- ::CalculateDepths(Entry, 0U);
+ ::CalculateDepths(*Entry, 0U);
for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
- ::CalculateDepths(&SUnits[i], 0U);
+ ::CalculateDepths(SUnits[i], 0U);
}
}
-static void CalculateHeights(SUnit *SU, unsigned Height) {
- if (SU->Height == 0 || Height > SU->Height) {
- SU->Height = Height;
- for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
- E = SU->Preds.end(); I != E; ++I)
- CalculateHeights(I->first, Height+1);
+static void CalculateHeights(SUnit &SU, unsigned Height) {
+ if (SU.Height == 0 || Height > SU.Height) {
+ SU.Height = Height;
+ for (SUnit::pred_iterator I = SU.Preds.begin(), E = SU.Preds.end();
+ I != E; ++I)
+ CalculateHeights(*I->first, Height+1);
}
}
void ScheduleDAG::CalculateHeights() {
SUnit *Root = SUnitMap[DAG.getRoot().Val];
- ::CalculateHeights(Root, 0U);
+ ::CalculateHeights(*Root, 0U);
}
/// CountResults - The results of target nodes have register or immediate
/// operands first, then an optional chain, and optional flag operands (which do
/// not go into the machine instrs.)
-static unsigned CountResults(SDNode *Node) {
+unsigned ScheduleDAG::CountResults(SDNode *Node) {
unsigned N = Node->getNumValues();
while (N && Node->getValueType(N - 1) == MVT::Flag)
--N;
/// CountOperands The inputs to target nodes have any actual inputs first,
/// followed by an optional chain operand, then flag operands. Compute the
/// number of actual operands that will go into the machine instr.
-static unsigned CountOperands(SDNode *Node) {
+unsigned ScheduleDAG::CountOperands(SDNode *Node) {
unsigned N = Node->getNumOperands();
while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
--N;
// the machine instruction.
unsigned ResultReg =
RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
- MI->addRegOperand(ResultReg, MachineOperand::Def);
+ MI->addRegOperand(ResultReg, true);
for (unsigned i = 1; i != NumResults; ++i) {
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
+ MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
}
return ResultReg;
}
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
- MI->addRegOperand(R->getReg(), MachineOperand::Use);
+ MI->addRegOperand(R->getReg(), false);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
dyn_cast<ConstantPoolSDNode>(Op)) {
int Offset = CP->getOffset();
unsigned Align = CP->getAlignment();
+ const Type *Type = CP->getType();
// MachineConstantPool wants an explicit alignment.
if (Align == 0) {
- if (CP->get()->getType() == Type::DoubleTy)
+ if (Type == Type::DoubleTy)
Align = 3; // always 8-byte align doubles.
else {
- Align = TM.getTargetData()
- ->getTypeAlignmentShift(CP->get()->getType());
+ Align = TM.getTargetData()->getTypeAlignmentShift(Type);
if (Align == 0) {
// Alignment of packed types. FIXME!
- Align = TM.getTargetData()->getTypeSize(CP->get()->getType());
+ Align = TM.getTargetData()->getTypeSize(Type);
Align = Log2_64(Align);
}
}
}
- unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);
+ unsigned Idx;
+ if (CP->isMachineConstantPoolEntry())
+ Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
+ else
+ Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
MI->addConstantPoolIndexOperand(Idx, Offset);
} else if (ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Op)) {
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
#endif
// Create the new machine instruction.
- MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
+ MachineInstr *MI = new MachineInstr(II);
// Add result register values for things that are defined by this
// instruction.
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg;
- MI->addRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, true);
break;
}
}
if (CommuteSet.count(Node)) {
MachineInstr *NewMI = TII->commuteInstruction(MI);
if (NewMI == 0)
- DEBUG(std::cerr << "Sched: COMMUTING FAILED!\n");
+ DOUT << "Sched: COMMUTING FAILED!\n";
else {
- DEBUG(std::cerr << "Sched: COMMUTED TO: " << *NewMI);
+ DOUT << "Sched: COMMUTED TO: " << *NewMI;
if (MI != NewMI) {
delete MI;
MI = NewMI;
// Create the inline asm machine instruction.
MachineInstr *MI =
- new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
+ new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
// Add the asm string as an external symbol operand.
const char *AsmStr =
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Use);
+ MI->addRegOperand(Reg, false);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, true);
}
break;
case 3: { // Immediate.
assert(NumVals == 1 && "Unknown immediate value!");
- uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
- MI->addImmOperand(Val);
+ if (ConstantSDNode *CS=dyn_cast<ConstantSDNode>(Node->getOperand(i))){
+ MI->addImmOperand(CS->getValue());
+ } else {
+ GlobalAddressSDNode *GA =
+ cast<GlobalAddressSDNode>(Node->getOperand(i));
+ MI->addGlobalAddressOperand(GA->getGlobal(), GA->getOffset());
+ }
++i;
break;
}
if (SUnit *SU = Sequence[i])
SU->dump(&DAG);
else
- std::cerr << "**** NOOP ****\n";
+ cerr << "**** NOOP ****\n";
}
}
/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
/// a group of nodes flagged together.
void SUnit::dump(const SelectionDAG *G) const {
- std::cerr << "SU(" << NodeNum << "): ";
+ cerr << "SU(" << NodeNum << "): ";
Node->dump(G);
- std::cerr << "\n";
+ cerr << "\n";
if (FlaggedNodes.size() != 0) {
for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
- std::cerr << " ";
+ cerr << " ";
FlaggedNodes[i]->dump(G);
- std::cerr << "\n";
+ cerr << "\n";
}
}
}
void SUnit::dumpAll(const SelectionDAG *G) const {
dump(G);
- std::cerr << " # preds left : " << NumPredsLeft << "\n";
- std::cerr << " # succs left : " << NumSuccsLeft << "\n";
- std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
- std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
- std::cerr << " Latency : " << Latency << "\n";
- std::cerr << " Depth : " << Depth << "\n";
- std::cerr << " Height : " << Height << "\n";
+ cerr << " # preds left : " << NumPredsLeft << "\n";
+ cerr << " # succs left : " << NumSuccsLeft << "\n";
+ cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
+ cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
+ cerr << " Latency : " << Latency << "\n";
+ cerr << " Depth : " << Depth << "\n";
+ cerr << " Height : " << Height << "\n";
if (Preds.size() != 0) {
- std::cerr << " Predecessors:\n";
- for (std::set<std::pair<SUnit*,bool> >::const_iterator I = Preds.begin(),
- E = Preds.end(); I != E; ++I) {
+ cerr << " Predecessors:\n";
+ for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
+ I != E; ++I) {
if (I->second)
- std::cerr << " ch ";
+ cerr << " ch #";
else
- std::cerr << " val ";
- I->first->dump(G);
+ cerr << " val #";
+ cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
}
}
if (Succs.size() != 0) {
- std::cerr << " Successors:\n";
- for (std::set<std::pair<SUnit*, bool> >::const_iterator I = Succs.begin(),
- E = Succs.end(); I != E; ++I) {
+ cerr << " Successors:\n";
+ for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
+ I != E; ++I) {
if (I->second)
- std::cerr << " ch ";
+ cerr << " ch #";
else
- std::cerr << " val ";
- I->first->dump(G);
+ cerr << " val #";
+ cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
}
}
- std::cerr << "\n";
+ cerr << "\n";
}
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