#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetInstrItineraries.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Constant.h"
+#include "llvm/Support/MathExtras.h"
#include <iostream>
using namespace llvm;
+/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
+/// This SUnit graph is similar to the SelectionDAG, but represents flagged
+/// together nodes with a single SUnit.
+void ScheduleDAG::BuildSchedUnits() {
+ // Reserve entries in the vector for each of the SUnits we are creating. This
+ // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
+ // invalidated.
+ SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
+
+ const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
+
+ for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
+ E = DAG.allnodes_end(); NI != E; ++NI) {
+ if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
+ continue;
+
+ // If this node has already been processed, stop now.
+ if (SUnitMap[NI]) continue;
+
+ SUnit *NodeSUnit = NewSUnit(NI);
+
+ // See if anything is flagged to this node, if so, add them to flagged
+ // nodes. Nodes can have at most one flag input and one flag output. Flags
+ // are required the be the last operand and result of a node.
+
+ // Scan up, adding flagged preds to FlaggedNodes.
+ SDNode *N = NI;
+ if (N->getNumOperands() &&
+ N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
+ do {
+ N = N->getOperand(N->getNumOperands()-1).Val;
+ NodeSUnit->FlaggedNodes.push_back(N);
+ SUnitMap[N] = NodeSUnit;
+ } while (N->getNumOperands() &&
+ N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
+ std::reverse(NodeSUnit->FlaggedNodes.begin(),
+ NodeSUnit->FlaggedNodes.end());
+ }
+
+ // Scan down, adding this node and any flagged succs to FlaggedNodes if they
+ // have a user of the flag operand.
+ N = NI;
+ while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
+ SDOperand FlagVal(N, N->getNumValues()-1);
+
+ // There are either zero or one users of the Flag result.
+ bool HasFlagUse = false;
+ for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
+ UI != E; ++UI)
+ if (FlagVal.isOperand(*UI)) {
+ HasFlagUse = true;
+ NodeSUnit->FlaggedNodes.push_back(N);
+ SUnitMap[N] = NodeSUnit;
+ N = *UI;
+ break;
+ }
+ if (!HasFlagUse) break;
+ }
+
+ // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
+ // Update the SUnit
+ NodeSUnit->Node = N;
+ SUnitMap[N] = NodeSUnit;
+
+ // Compute the latency for the node. We use the sum of the latencies for
+ // all nodes flagged together into this SUnit.
+ if (InstrItins.isEmpty()) {
+ // No latency information.
+ NodeSUnit->Latency = 1;
+ } else {
+ NodeSUnit->Latency = 0;
+ if (N->isTargetOpcode()) {
+ unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode());
+ InstrStage *S = InstrItins.begin(SchedClass);
+ InstrStage *E = InstrItins.end(SchedClass);
+ for (; S != E; ++S)
+ NodeSUnit->Latency += S->Cycles;
+ }
+ for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) {
+ SDNode *FNode = NodeSUnit->FlaggedNodes[i];
+ if (FNode->isTargetOpcode()) {
+ unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
+ InstrStage *S = InstrItins.begin(SchedClass);
+ InstrStage *E = InstrItins.end(SchedClass);
+ for (; S != E; ++S)
+ NodeSUnit->Latency += S->Cycles;
+ }
+ }
+ }
+ }
+
+ // Pass 2: add the preds, succs, etc.
+ for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
+ SUnit *SU = &SUnits[su];
+ SDNode *MainNode = SU->Node;
+
+ if (MainNode->isTargetOpcode()) {
+ unsigned Opc = MainNode->getTargetOpcode();
+ if (TII->isTwoAddrInstr(Opc))
+ SU->isTwoAddress = true;
+ if (TII->isCommutableInstr(Opc))
+ SU->isCommutable = true;
+ }
+
+ // Find all predecessors and successors of the group.
+ // Temporarily add N to make code simpler.
+ SU->FlaggedNodes.push_back(MainNode);
+
+ for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
+ SDNode *N = SU->FlaggedNodes[n];
+
+ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
+ SDNode *OpN = N->getOperand(i).Val;
+ if (isPassiveNode(OpN)) continue; // Not scheduled.
+ SUnit *OpSU = SUnitMap[OpN];
+ assert(OpSU && "Node has no SUnit!");
+ if (OpSU == SU) continue; // In the same group.
+
+ MVT::ValueType OpVT = N->getOperand(i).getValueType();
+ assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
+ bool isChain = OpVT == MVT::Other;
+
+ if (SU->addPred(OpSU, isChain)) {
+ if (!isChain) {
+ SU->NumPreds++;
+ SU->NumPredsLeft++;
+ } else {
+ SU->NumChainPredsLeft++;
+ }
+ }
+ if (OpSU->addSucc(SU, isChain)) {
+ if (!isChain) {
+ OpSU->NumSuccs++;
+ OpSU->NumSuccsLeft++;
+ } else {
+ OpSU->NumChainSuccsLeft++;
+ }
+ }
+ }
+ }
+
+ // Remove MainNode from FlaggedNodes again.
+ SU->FlaggedNodes.pop_back();
+ }
+
+ return;
+}
+
+static void CalculateDepths(SUnit &SU, unsigned Depth) {
+ if (SU.Depth == 0 || Depth > SU.Depth) {
+ SU.Depth = Depth;
+ for (SUnit::succ_iterator I = SU.Succs.begin(), E = SU.Succs.end();
+ I != E; ++I)
+ CalculateDepths(*I->first, Depth+1);
+ }
+}
+
+void ScheduleDAG::CalculateDepths() {
+ SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
+ ::CalculateDepths(*Entry, 0U);
+ for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
+ if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
+ ::CalculateDepths(SUnits[i], 0U);
+ }
+}
+
+static void CalculateHeights(SUnit &SU, unsigned Height) {
+ if (SU.Height == 0 || Height > SU.Height) {
+ SU.Height = Height;
+ for (SUnit::pred_iterator I = SU.Preds.begin(), E = SU.Preds.end();
+ I != E; ++I)
+ CalculateHeights(*I->first, Height+1);
+ }
+}
+void ScheduleDAG::CalculateHeights() {
+ SUnit *Root = SUnitMap[DAG.getRoot().Val];
+ ::CalculateHeights(*Root, 0U);
+}
+
/// CountResults - The results of target nodes have register or immediate
/// operands first, then an optional chain, and optional flag operands (which do
/// not go into the machine instrs.)
return N;
}
-/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
-///
-void ScheduleDAG::PrepareNodeInfo() {
- // Allocate node information
- Info = new NodeInfo[NodeCount];
-
- unsigned i = 0;
- for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
- E = DAG.allnodes_end(); I != E; ++I, ++i) {
- // Fast reference to node schedule info
- NodeInfo* NI = &Info[i];
- // Set up map
- Map[I] = NI;
- // Set node
- NI->Node = I;
- // Set pending visit count
- NI->setPending(I->use_size());
- }
-}
-
-/// IdentifyGroups - Put flagged nodes into groups.
-///
-void ScheduleDAG::IdentifyGroups() {
- for (unsigned i = 0, N = NodeCount; i < N; i++) {
- NodeInfo* NI = &Info[i];
- SDNode *Node = NI->Node;
-
- // For each operand (in reverse to only look at flags)
- for (unsigned N = Node->getNumOperands(); 0 < N--;) {
- // Get operand
- SDOperand Op = Node->getOperand(N);
- // No more flags to walk
- if (Op.getValueType() != MVT::Flag) break;
- // Add to node group
- AddToGroup(getNI(Op.Val), NI);
- // Let everyone else know
- HasGroups = true;
- }
+static const TargetRegisterClass *getInstrOperandRegClass(
+ const MRegisterInfo *MRI,
+ const TargetInstrInfo *TII,
+ const TargetInstrDescriptor *II,
+ unsigned Op) {
+ if (Op >= II->numOperands) {
+ assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+ return NULL;
}
+ const TargetOperandInfo &toi = II->OpInfo[Op];
+ return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
}
-static unsigned CreateVirtualRegisters(MachineInstr *MI,
+static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
+ MachineInstr *MI,
unsigned NumResults,
SSARegMap *RegMap,
+ const TargetInstrInfo *TII,
const TargetInstrDescriptor &II) {
// Create the result registers for this node and add the result regs to
// the machine instruction.
- const TargetOperandInfo *OpInfo = II.OpInfo;
- unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
+ unsigned ResultReg =
+ RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
MI->addRegOperand(ResultReg, MachineOperand::Def);
for (unsigned i = 1; i != NumResults; ++i) {
- assert(OpInfo[i].RegClass && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
- MachineOperand::Def);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+ assert(RC && "Isn't a register operand!");
+ MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
}
return ResultReg;
}
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- assert(II->OpInfo[IIOpNum].RegClass &&
- "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ assert(RC && "Don't have operand info for this instruction!");
+ assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
}
} else if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Op)) {
- MI->addZeroExtImm64Operand(C->getValue());
+ MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), MachineOperand::Use);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
- MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
+ MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
} else if (BasicBlockSDNode *BB =
dyn_cast<BasicBlockSDNode>(Op)) {
MI->addMachineBasicBlockOperand(BB->getBasicBlock());
} else if (FrameIndexSDNode *FI =
dyn_cast<FrameIndexSDNode>(Op)) {
MI->addFrameIndexOperand(FI->getIndex());
+ } else if (JumpTableSDNode *JT =
+ dyn_cast<JumpTableSDNode>(Op)) {
+ MI->addJumpTableIndexOperand(JT->getIndex());
} else if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(Op)) {
int Offset = CP->getOffset();
if (Align == 0) {
if (CP->get()->getType() == Type::DoubleTy)
Align = 3; // always 8-byte align doubles.
- else
+ else {
Align = TM.getTargetData()
- .getTypeAlignmentShift(CP->get()->getType());
+ ->getTypeAlignmentShift(CP->get()->getType());
+ if (Align == 0) {
+ // Alignment of packed types. FIXME!
+ Align = TM.getTargetData()->getTypeSize(CP->get()->getType());
+ Align = Log2_64(Align);
+ }
+ }
}
unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align);
MI->addConstantPoolIndexOperand(Idx, Offset);
} else if (ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Op)) {
- MI->addExternalSymbolOperand(ES->getSymbol(), false);
+ MI->addExternalSymbolOperand(ES->getSymbol());
} else {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag &&
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- assert(II->OpInfo[IIOpNum].RegClass &&
- "Don't have operand info for this instruction!");
- assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass &&
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ assert(RC && "Don't have operand info for this instruction!");
+ assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
}
}
unsigned NodeOperands = CountOperands(Node);
unsigned NumMIOperands = NodeOperands + NumResults;
#ifndef NDEBUG
- assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
+ assert((unsigned(II.numOperands) == NumMIOperands ||
+ (II.Flags & M_VARIABLE_OPS)) &&
"#operands for dag node doesn't match .td file!");
#endif
// Create the new machine instruction.
- MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
+ MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
// Add result register values for things that are defined by this
// instruction.
// Otherwise, create new virtual registers.
if (NumResults && VRBase == 0)
- VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, II);
+ VRBase = CreateVirtualRegisters(MRI, MI, NumResults, RegMap, TII, II);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
for (unsigned i = 0; i != NodeOperands; ++i)
AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap);
-
+
+ // Commute node if it has been determined to be profitable.
+ if (CommuteSet.count(Node)) {
+ MachineInstr *NewMI = TII->commuteInstruction(MI);
+ if (NewMI == 0)
+ DEBUG(std::cerr << "Sched: COMMUTING FAILED!\n");
+ else {
+ DEBUG(std::cerr << "Sched: COMMUTED TO: " << *NewMI);
+ if (MI != NewMI) {
+ delete MI;
+ MI = NewMI;
+ }
+ }
+ }
+
// Now that we have emitted all operands, emit this instruction itself.
if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
BB->insert(BB->end(), MI);
} else {
switch (Node->getOpcode()) {
default:
- Node->dump();
+#ifndef NDEBUG
+ Node->dump();
+#endif
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
case ISD::CopyToReg: {
unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (InReg != DestReg) // Coallesced away the copy?
+ if (InReg != DestReg) // Coalesced away the copy?
MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
RegMap->getRegClass(InReg));
break;
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
- MI->addExternalSymbolOperand(AsmStr, false);
+ MI->addExternalSymbolOperand(AsmStr);
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
unsigned NumVals = Flags >> 3;
- MI->addZeroExtImm64Operand(Flags);
+ MI->addImmOperand(Flags);
++i; // Skip the ID value.
switch (Flags & 7) {
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Use);
+ MI->addRegOperand(Reg, MachineOperand::Use);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, MachineOperand::Def);
}
break;
case 3: { // Immediate.
assert(NumVals == 1 && "Unknown immediate value!");
uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
- MI->addZeroExtImm64Operand(Val);
+ MI->addImmOperand(Val);
++i;
break;
}
TII->insertNoop(*BB, BB->end());
}
-/// EmitAll - Emit all nodes in schedule sorted order.
-///
-void ScheduleDAG::EmitAll() {
- std::map<SDNode*, unsigned> VRBaseMap;
-
- // For each node in the ordering
- for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
- // Get the scheduling info
- NodeInfo *NI = Ordering[i];
- if (NI->isInGroup()) {
- NodeGroupIterator NGI(Ordering[i]);
- while (NodeInfo *NI = NGI.next()) EmitNode(NI->Node, VRBaseMap);
- } else {
- EmitNode(NI->Node, VRBaseMap);
- }
- }
-}
-
-/// isFlagDefiner - Returns true if the node defines a flag result.
-static bool isFlagDefiner(SDNode *A) {
- unsigned N = A->getNumValues();
- return N && A->getValueType(N - 1) == MVT::Flag;
-}
-
-/// isFlagUser - Returns true if the node uses a flag result.
-///
-static bool isFlagUser(SDNode *A) {
- unsigned N = A->getNumOperands();
- return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
-}
-
-/// printNI - Print node info.
-///
-void ScheduleDAG::printNI(std::ostream &O, NodeInfo *NI) const {
-#ifndef NDEBUG
- SDNode *Node = NI->Node;
- O << " "
- << std::hex << Node << std::dec
- << ", Lat=" << NI->Latency
- << ", Slot=" << NI->Slot
- << ", ARITY=(" << Node->getNumOperands() << ","
- << Node->getNumValues() << ")"
- << " " << Node->getOperationName(&DAG);
- if (isFlagDefiner(Node)) O << "<#";
- if (isFlagUser(Node)) O << ">#";
-#endif
-}
-
-/// printChanges - Hilight changes in order caused by scheduling.
-///
-void ScheduleDAG::printChanges(unsigned Index) const {
-#ifndef NDEBUG
- // Get the ordered node count
- unsigned N = Ordering.size();
- // Determine if any changes
- unsigned i = 0;
- for (; i < N; i++) {
- NodeInfo *NI = Ordering[i];
- if (NI->Preorder != i) break;
+/// EmitSchedule - Emit the machine code in scheduled order.
+void ScheduleDAG::EmitSchedule() {
+ // If this is the first basic block in the function, and if it has live ins
+ // that need to be copied into vregs, emit the copies into the top of the
+ // block before emitting the code for the block.
+ MachineFunction &MF = DAG.getMachineFunction();
+ if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
+ for (MachineFunction::livein_iterator LI = MF.livein_begin(),
+ E = MF.livein_end(); LI != E; ++LI)
+ if (LI->second)
+ MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
+ LI->first, RegMap->getRegClass(LI->second));
}
- if (i < N) {
- std::cerr << Index << ". New Ordering\n";
-
- for (i = 0; i < N; i++) {
- NodeInfo *NI = Ordering[i];
- std::cerr << " " << NI->Preorder << ". ";
- printNI(std::cerr, NI);
- std::cerr << "\n";
- if (NI->isGroupDominator()) {
- NodeGroup *Group = NI->Group;
- for (NIIterator NII = Group->group_begin(), E = Group->group_end();
- NII != E; NII++) {
- std::cerr << " ";
- printNI(std::cerr, *NII);
- std::cerr << "\n";
- }
- }
+
+ // Finally, emit the code for all of the scheduled instructions.
+ std::map<SDNode*, unsigned> VRBaseMap;
+ for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
+ if (SUnit *SU = Sequence[i]) {
+ for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
+ EmitNode(SU->FlaggedNodes[j], VRBaseMap);
+ EmitNode(SU->Node, VRBaseMap);
+ } else {
+ // Null SUnit* is a noop.
+ EmitNoop();
}
- } else {
- std::cerr << Index << ". No Changes\n";
}
-#endif
}
-/// print - Print ordering to specified output stream.
-///
-void ScheduleDAG::print(std::ostream &O) const {
-#ifndef NDEBUG
- using namespace std;
- O << "Ordering\n";
- for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
- NodeInfo *NI = Ordering[i];
- printNI(O, NI);
- O << "\n";
- if (NI->isGroupDominator()) {
- NodeGroup *Group = NI->Group;
- for (NIIterator NII = Group->group_begin(), E = Group->group_end();
- NII != E; NII++) {
- O << " ";
- printNI(O, *NII);
- O << "\n";
- }
- }
+/// dump - dump the schedule.
+void ScheduleDAG::dumpSchedule() const {
+ for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
+ if (SUnit *SU = Sequence[i])
+ SU->dump(&DAG);
+ else
+ std::cerr << "**** NOOP ****\n";
}
-#endif
}
-void ScheduleDAG::dump(const char *tag) const {
- std::cerr << tag; dump();
-}
-
-void ScheduleDAG::dump() const {
- print(std::cerr);
-}
/// Run - perform scheduling.
///
RegMap = BB->getParent()->getSSARegMap();
ConstPool = BB->getParent()->getConstantPool();
- // Number the nodes
- NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
-
Schedule();
return BB;
}
-
-/// CountInternalUses - Returns the number of edges between the two nodes.
-///
-static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U) {
- unsigned N = 0;
- for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
- SDOperand Op = U->Node->getOperand(M);
- if (Op.Val == D->Node) N++;
+/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
+/// a group of nodes flagged together.
+void SUnit::dump(const SelectionDAG *G) const {
+ std::cerr << "SU(" << NodeNum << "): ";
+ Node->dump(G);
+ std::cerr << "\n";
+ if (FlaggedNodes.size() != 0) {
+ for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
+ std::cerr << " ";
+ FlaggedNodes[i]->dump(G);
+ std::cerr << "\n";
+ }
}
-
- return N;
}
-//===----------------------------------------------------------------------===//
-/// Add - Adds a definer and user pair to a node group.
-///
-void ScheduleDAG::AddToGroup(NodeInfo *D, NodeInfo *U) {
- // Get current groups
- NodeGroup *DGroup = D->Group;
- NodeGroup *UGroup = U->Group;
- // If both are members of groups
- if (DGroup && UGroup) {
- // There may have been another edge connecting
- if (DGroup == UGroup) return;
- // Add the pending users count
- DGroup->addPending(UGroup->getPending());
- // For each member of the users group
- NodeGroupIterator UNGI(U);
- while (NodeInfo *UNI = UNGI.next() ) {
- // Change the group
- UNI->Group = DGroup;
- // For each member of the definers group
- NodeGroupIterator DNGI(D);
- while (NodeInfo *DNI = DNGI.next() ) {
- // Remove internal edges
- DGroup->addPending(-CountInternalUses(DNI, UNI));
- }
- }
- // Merge the two lists
- DGroup->group_insert(DGroup->group_end(),
- UGroup->group_begin(), UGroup->group_end());
- } else if (DGroup) {
- // Make user member of definers group
- U->Group = DGroup;
- // Add users uses to definers group pending
- DGroup->addPending(U->Node->use_size());
- // For each member of the definers group
- NodeGroupIterator DNGI(D);
- while (NodeInfo *DNI = DNGI.next() ) {
- // Remove internal edges
- DGroup->addPending(-CountInternalUses(DNI, U));
+void SUnit::dumpAll(const SelectionDAG *G) const {
+ dump(G);
+
+ std::cerr << " # preds left : " << NumPredsLeft << "\n";
+ std::cerr << " # succs left : " << NumSuccsLeft << "\n";
+ std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
+ std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
+ std::cerr << " Latency : " << Latency << "\n";
+ std::cerr << " Depth : " << Depth << "\n";
+ std::cerr << " Height : " << Height << "\n";
+
+ if (Preds.size() != 0) {
+ std::cerr << " Predecessors:\n";
+ for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
+ I != E; ++I) {
+ if (I->second)
+ std::cerr << " ch #";
+ else
+ std::cerr << " val #";
+ std::cerr << I->first << "\n";
}
- DGroup->group_push_back(U);
- } else if (UGroup) {
- // Make definer member of users group
- D->Group = UGroup;
- // Add definers uses to users group pending
- UGroup->addPending(D->Node->use_size());
- // For each member of the users group
- NodeGroupIterator UNGI(U);
- while (NodeInfo *UNI = UNGI.next() ) {
- // Remove internal edges
- UGroup->addPending(-CountInternalUses(D, UNI));
+ }
+ if (Succs.size() != 0) {
+ std::cerr << " Successors:\n";
+ for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
+ I != E; ++I) {
+ if (I->second)
+ std::cerr << " ch #";
+ else
+ std::cerr << " val #";
+ std::cerr << I->first << "\n";
}
- UGroup->group_insert(UGroup->group_begin(), D);
- } else {
- D->Group = U->Group = DGroup = new NodeGroup();
- DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
- CountInternalUses(D, U));
- DGroup->group_push_back(D);
- DGroup->group_push_back(U);
-
- if (HeadNG == NULL)
- HeadNG = DGroup;
- if (TailNG != NULL)
- TailNG->Next = DGroup;
- TailNG = DGroup;
}
+ std::cerr << "\n";
}
projects / oota-llvm.git / blobdiff