/// getTypeAction - Return how we should legalize values of this type, either
/// it is already legal or we need to expand it into multiple registers of
/// smaller integer type, or we need to promote it to a larger type.
- LegalizeAction getTypeAction(MVT::ValueType VT) const {
+ LegalizeAction getTypeAction(MVT VT) const {
return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
}
/// isTypeLegal - Return true if this type is legal on this target.
///
- bool isTypeLegal(MVT::ValueType VT) const {
+ bool isTypeLegal(MVT VT) const {
return getTypeAction(VT) == Legal;
}
///
/// If this is a legal shuffle, this method returns the (possibly promoted)
/// build_vector Mask. If it's not a legal shuffle, it returns null.
- SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
+ SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const;
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
SDOperand &Hi);
- SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
- SDOperand Source);
+ SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source);
- SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
- MVT::ValueType DestVT);
+ SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT);
SDOperand ExpandBUILD_VECTOR(SDNode *Node);
SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
- SDOperand ExpandLegalINT_TO_FP(bool isSigned,
- SDOperand LegalOp,
- MVT::ValueType DestVT);
- SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
- bool isSigned);
- SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
- bool isSigned);
+ SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT);
+ SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned);
+ SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned);
SDOperand ExpandBSWAP(SDOperand Op);
SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
///
/// Note that this will also return true for shuffles that are promoted to a
/// different type.
-SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
- SDOperand Mask) const {
+SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
default: return 0;
case TargetLowering::Legal:
case TargetLowering::Promote: {
// If this is promoted to a different type, convert the shuffle mask and
// ask if it is legal in the promoted type!
- MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
+ MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
// If we changed # elements, change the shuffle mask.
unsigned NumEltsGrowth =
- MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
+ NVT.getVectorNumElements() / VT.getVectorNumElements();
assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
if (NumEltsGrowth > 1) {
// Renumber the elements.
}
assert(Order.size() == Visited.size() &&
- Order.size() ==
- (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
+ Order.size() == DAG.allnodes_size() &&
"Error: DAG is cyclic!");
}
/// HandleOp - Legalize, Promote, or Expand the specified operand as
/// appropriate for its type.
void SelectionDAGLegalize::HandleOp(SDOperand Op) {
- MVT::ValueType VT = Op.getValueType();
+ MVT VT = Op.getValueType();
switch (getTypeAction(VT)) {
default: assert(0 && "Bad type action!");
case Legal: (void)LegalizeOp(Op); break;
case Promote: (void)PromoteOp(Op); break;
case Expand:
- if (!MVT::isVector(VT)) {
+ if (!VT.isVector()) {
// If this is an illegal scalar, expand it into its two component
// pieces.
SDOperand X, Y;
if (Op.getOpcode() == ISD::TargetConstant)
break; // Allow illegal target nodes.
ExpandOp(Op, X, Y);
- } else if (MVT::getVectorNumElements(VT) == 1) {
+ } else if (VT.getVectorNumElements() == 1) {
// If this is an illegal single element vector, convert it to a
// scalar operation.
(void)ScalarizeVectorOp(Op);
// double. This shrinks FP constants and canonicalizes them for targets where
// an FP extending load is the same cost as a normal load (such as on the x87
// fp stack or PPC FP unit).
- MVT::ValueType VT = CFP->getValueType(0);
+ MVT VT = CFP->getValueType(0);
ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
if (!UseCP) {
if (VT!=MVT::f64 && VT!=MVT::f32)
(VT == MVT::f64) ? MVT::i64 : MVT::i32);
}
- MVT::ValueType OrigVT = VT;
- MVT::ValueType SVT = VT;
+ MVT OrigVT = VT;
+ MVT SVT = VT;
while (SVT != MVT::f32) {
- SVT = (unsigned)SVT - 1;
+ SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
// Only do this if the target has a native EXTLOAD instruction from
// smaller type.
TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
TLI.ShouldShrinkFPConstant(OrigVT)) {
- const Type *SType = MVT::getTypeForValueType(SVT);
+ const Type *SType = SVT.getTypeForMVT();
LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
VT = SVT;
Extend = true;
/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
/// operations.
static
-SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
+SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
SelectionDAG &DAG, TargetLowering &TLI) {
- MVT::ValueType VT = Node->getValueType(0);
- MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
+ MVT VT = Node->getValueType(0);
+ MVT SrcVT = Node->getOperand(1).getValueType();
assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
"fcopysign expansion only supported for f32 and f64");
- MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
+ MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
// First get the sign bit of second operand.
SDOperand Mask1 = (SrcVT == MVT::f64)
SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
// Shift right or sign-extend it if the two operands have different types.
- int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
+ int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
if (SizeDiff > 0) {
SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
SDOperand Chain = ST->getChain();
SDOperand Ptr = ST->getBasePtr();
SDOperand Val = ST->getValue();
- MVT::ValueType VT = Val.getValueType();
+ MVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
int SVOffset = ST->getSrcValueOffset();
- if (MVT::isFloatingPoint(ST->getMemoryVT()) ||
- MVT::isVector(ST->getMemoryVT())) {
+ if (ST->getMemoryVT().isFloatingPoint() ||
+ ST->getMemoryVT().isVector()) {
// Expand to a bitconvert of the value to the integer type of the
// same size, then a (misaligned) int store.
- MVT::ValueType intVT;
- if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
+ MVT intVT;
+ if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
intVT = MVT::i128;
- else if (MVT::is64BitVector(VT) || VT==MVT::f64)
+ else if (VT.is64BitVector() || VT==MVT::f64)
intVT = MVT::i64;
else if (VT==MVT::f32)
intVT = MVT::i32;
return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
SVOffset, ST->isVolatile(), Alignment);
}
- assert(MVT::isInteger(ST->getMemoryVT()) &&
- !MVT::isVector(ST->getMemoryVT()) &&
+ assert(ST->getMemoryVT().isInteger() &&
+ !ST->getMemoryVT().isVector() &&
"Unaligned store of unknown type.");
// Get the half-size VT
- MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
- int NumBits = MVT::getSizeInBits(NewStoredVT);
+ MVT NewStoredVT =
+ (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
+ int NumBits = NewStoredVT.getSizeInBits();
int IncrementSize = NumBits / 8;
// Divide the stored value in two parts.
int SVOffset = LD->getSrcValueOffset();
SDOperand Chain = LD->getChain();
SDOperand Ptr = LD->getBasePtr();
- MVT::ValueType VT = LD->getValueType(0);
- MVT::ValueType LoadedVT = LD->getMemoryVT();
- if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
+ MVT VT = LD->getValueType(0);
+ MVT LoadedVT = LD->getMemoryVT();
+ if (VT.isFloatingPoint() || VT.isVector()) {
// Expand to a (misaligned) integer load of the same size,
// then bitconvert to floating point or vector.
- MVT::ValueType intVT;
- if (MVT::is128BitVector(LoadedVT) ||
+ MVT intVT;
+ if (LoadedVT.is128BitVector() ||
LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
intVT = MVT::i128;
- else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
+ else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
intVT = MVT::i64;
else if (LoadedVT == MVT::f32)
intVT = MVT::i32;
SVOffset, LD->isVolatile(),
LD->getAlignment());
SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
- if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
+ if (VT.isFloatingPoint() && LoadedVT != VT)
Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
SDOperand Ops[] = { Result, Chain };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- Ops, 2);
+ return DAG.getMergeValues(Ops, 2);
}
- assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
+ assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
"Unaligned load of unsupported type.");
// Compute the new VT that is half the size of the old one. This is an
// integer MVT.
- unsigned NumBits = MVT::getSizeInBits(LoadedVT);
- MVT::ValueType NewLoadedVT;
- NewLoadedVT = MVT::getIntegerType(NumBits/2);
+ unsigned NumBits = LoadedVT.getSizeInBits();
+ MVT NewLoadedVT;
+ NewLoadedVT = MVT::getIntegerVT(NumBits/2);
NumBits >>= 1;
unsigned Alignment = LD->getAlignment();
Hi.getValue(1));
SDOperand Ops[] = { Result, TF };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
+ return DAG.getMergeValues(Ops, 2);
}
/// UnrollVectorOp - We know that the given vector has a legal type, however
/// no way of lowering. "Unroll" the vector, splitting out the scalars and
/// operating on each element individually.
SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
- MVT::ValueType VT = Op.getValueType();
+ MVT VT = Op.getValueType();
assert(isTypeLegal(VT) &&
"Caller should expand or promote operands that are not legal!");
assert(Op.Val->getNumValues() == 1 &&
"Can't unroll a vector with multiple results!");
- unsigned NE = MVT::getVectorNumElements(VT);
- MVT::ValueType EltVT = MVT::getVectorElementType(VT);
+ unsigned NE = VT.getVectorNumElements();
+ MVT EltVT = VT.getVectorElementType();
SmallVector<SDOperand, 8> Scalars;
SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
for (unsigned i = 0; i != NE; ++i) {
for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
SDOperand Operand = Op.getOperand(j);
- MVT::ValueType OperandVT = Operand.getValueType();
- if (MVT::isVector(OperandVT)) {
+ MVT OperandVT = Operand.getValueType();
+ if (OperandVT.isVector()) {
// A vector operand; extract a single element.
- MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
+ MVT OperandEltVT = OperandVT.getVectorElementType();
Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
OperandEltVT,
Operand,
}
/// GetFPLibCall - Return the right libcall for the given floating point type.
-static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
+static RTLIB::Libcall GetFPLibCall(MVT VT,
RTLIB::Libcall Call_F32,
RTLIB::Libcall Call_F64,
RTLIB::Libcall Call_F80,
// with a "move to register" or "extload into register" instruction, then
// permute it into place, if the idx is a constant and if the idx is
// supported by the target.
- MVT::ValueType VT = Tmp1.getValueType();
- MVT::ValueType EltVT = MVT::getVectorElementType(VT);
- MVT::ValueType IdxVT = Tmp3.getValueType();
- MVT::ValueType PtrVT = TLI.getPointerTy();
+ MVT VT = Tmp1.getValueType();
+ MVT EltVT = VT.getVectorElementType();
+ MVT IdxVT = Tmp3.getValueType();
+ MVT PtrVT = TLI.getPointerTy();
SDOperand StackPtr = DAG.CreateStackTemporary(VT);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
SPFI);
// Truncate or zero extend offset to target pointer type.
- unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
+ unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
// Add the offset to the index.
- unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
+ unsigned EltSize = EltVT.getSizeInBits()/8;
Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
// Store the scalar value.
case ISD::VALUETYPE:
case ISD::SRCVALUE:
case ISD::MEMOPERAND:
- case ISD::STRING:
case ISD::CONDCODE:
case ISD::ARG_FLAGS:
// Primitives must all be legal.
Result = DAG.getConstant(0, TLI.getPointerTy());
break;
case ISD::FRAME_TO_ARGS_OFFSET: {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom:
break;
case ISD::EXCEPTIONADDR: {
Tmp1 = LegalizeOp(Node->getOperand(0));
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
// Fall Thru
case TargetLowering::Legal: {
SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
- Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- Ops, 2);
+ Result = DAG.getMergeValues(Ops, 2);
break;
}
}
case ISD::EHSELECTION: {
Tmp1 = LegalizeOp(Node->getOperand(0));
Tmp2 = LegalizeOp(Node->getOperand(1));
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
// Fall Thru
case TargetLowering::Legal: {
SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
- Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- Ops, 2);
+ Result = DAG.getMergeValues(Ops, 2);
break;
}
}
AddLegalizedOperand(Op.getValue(1), Tmp2);
return Op.ResNo ? Tmp2 : Tmp1;
case ISD::EH_RETURN: {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
// The only "good" option for this node is to custom lower it.
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported at all!");
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
return Result.getValue(Op.ResNo);
case ISD::UNDEF: {
- MVT::ValueType VT = Op.getValueType();
+ MVT VT = Op.getValueType();
switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand:
- if (MVT::isInteger(VT))
+ if (VT.isInteger())
Result = DAG.getConstant(0, VT);
- else if (MVT::isFloatingPoint(VT))
- Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
+ else if (VT.isFloatingPoint())
+ Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
VT);
else
assert(0 && "Unknown value type!");
return Result.getValue(Op.ResNo);
}
- case ISD::LOCATION:
- assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
+ case ISD::DBG_STOPPOINT:
+ assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
- switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
+ switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
case TargetLowering::Promote:
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
- bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
+ bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
+ const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
if (MMI && (useDEBUG_LOC || useLABEL)) {
- const std::string &FName =
- cast<StringSDNode>(Node->getOperand(3))->getValue();
- const std::string &DirName =
- cast<StringSDNode>(Node->getOperand(4))->getValue();
- unsigned SrcFile = MMI->RecordSource(DirName, FName);
+ const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
+ unsigned SrcFile = MMI->RecordSource(CompileUnit);
- SmallVector<SDOperand, 8> Ops;
- Ops.push_back(Tmp1); // chain
- SDOperand LineOp = Node->getOperand(1);
- SDOperand ColOp = Node->getOperand(2);
+ unsigned Line = DSP->getLine();
+ unsigned Col = DSP->getColumn();
if (useDEBUG_LOC) {
- Ops.push_back(LineOp); // line #
- Ops.push_back(ColOp); // col #
+ SmallVector<SDOperand, 8> Ops;
+ Ops.push_back(Tmp1); // chain
+ Ops.push_back(DAG.getConstant(Line, MVT::i32)); // line #
+ Ops.push_back(DAG.getConstant(Col, MVT::i32)); // col #
Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
} else {
- unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
- unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
- Ops.push_back(DAG.getConstant(ID, MVT::i32));
- Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
- Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
+ Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
}
} else {
Result = Tmp1; // chain
}
break;
- case ISD::LABEL:
- assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
- switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
+ case ISD::DBG_LABEL:
+ case ISD::EH_LABEL:
+ assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
+ switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
- Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
- Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+ Result = DAG.UpdateNodeOperands(Result, Tmp1);
break;
case TargetLowering::Expand:
Result = LegalizeOp(Node->getOperand(0));
break;
}
- case ISD::ATOMIC_LCS: {
+ case ISD::ATOMIC_CMP_SWAP: {
unsigned int num_operands = 4;
assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
SDOperand Ops[4];
AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
- }
- case ISD::ATOMIC_LAS:
- case ISD::ATOMIC_LSS:
+ }
+ case ISD::ATOMIC_LOAD_ADD:
+ case ISD::ATOMIC_LOAD_SUB:
case ISD::ATOMIC_LOAD_AND:
case ISD::ATOMIC_LOAD_OR:
case ISD::ATOMIC_LOAD_XOR:
+ case ISD::ATOMIC_LOAD_NAND:
case ISD::ATOMIC_LOAD_MIN:
case ISD::ATOMIC_LOAD_MAX:
case ISD::ATOMIC_LOAD_UMIN:
for (unsigned int x = 0; x < num_operands; ++x)
Ops[x] = LegalizeOp(Node->getOperand(x));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom:
Result = TLI.LowerOperation(Result, DAG);
break;
case TargetLowering::Expand:
- Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0);
+ Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0);
break;
case TargetLowering::Legal:
break;
AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
- }
+ }
case ISD::Constant: {
ConstantSDNode *CN = cast<ConstantSDNode>(Node);
unsigned opAction =
// SCALAR_TO_VECTOR requires that the type of the value being inserted
// match the element type of the vector being created.
if (Tmp2.getValueType() ==
- MVT::getVectorElementType(Op.getValueType())) {
+ Op.getValueType().getVectorElementType()) {
SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
Tmp1.getValueType(), Tmp2);
- unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
- MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
- MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
+ unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
+ MVT ShufMaskVT =
+ MVT::getIntVectorWithNumElements(NumElts);
+ MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
// We generate a shuffle of InVec and ScVec, so the shuffle mask
// should be 0,1,2,3,4,5... with the appropriate element replaced with
}
// FALLTHROUGH
case TargetLowering::Expand: {
- MVT::ValueType VT = Node->getValueType(0);
- MVT::ValueType EltVT = MVT::getVectorElementType(VT);
- MVT::ValueType PtrVT = TLI.getPointerTy();
+ MVT VT = Node->getValueType(0);
+ MVT EltVT = VT.getVectorElementType();
+ MVT PtrVT = TLI.getPointerTy();
SDOperand Mask = Node->getOperand(2);
unsigned NumElems = Mask.getNumOperands();
SmallVector<SDOperand,8> Ops;
}
case TargetLowering::Promote: {
// Change base type to a different vector type.
- MVT::ValueType OVT = Node->getValueType(0);
- MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+ MVT OVT = Node->getValueType(0);
+ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
// Cast the two input vectors.
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
// process, no libcalls can/will be inserted, guaranteeing that no calls
// can overlap.
assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
- SDOperand InCallSEQ = LastCALLSEQ_END;
// Note that we are selecting this call!
LastCALLSEQ_END = SDOperand(CallEnd, 0);
IsLegalizingCall = true;
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
case ISD::DYNAMIC_STACKALLOC: {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
SDOperand Table = Result.getOperand(1);
SDOperand Index = Result.getOperand(2);
- MVT::ValueType PTy = TLI.getPointerTy();
+ MVT PTy = TLI.getPointerTy();
MachineFunction &MF = DAG.getMachineFunction();
unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD) {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
Tmp3 = Result.getValue(0);
Tmp4 = Result.getValue(1);
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
+ getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
TLI);
break;
case TargetLowering::Promote: {
// Only promote a load of vector type to another.
- assert(MVT::isVector(VT) && "Cannot promote this load!");
+ assert(VT.isVector() && "Cannot promote this load!");
// Change base type to a different vector type.
- MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
+ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
return Op.ResNo ? Tmp4 : Tmp3;
} else {
- MVT::ValueType SrcVT = LD->getMemoryVT();
- unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
+ MVT SrcVT = LD->getMemoryVT();
+ unsigned SrcWidth = SrcVT.getSizeInBits();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile();
- if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
+ if (SrcWidth != SrcVT.getStoreSizeInBits() &&
// Some targets pretend to have an i1 loading operation, and actually
// load an i8. This trick is correct for ZEXTLOAD because the top 7
// bits are guaranteed to be zero; it helps the optimizers understand
TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
// Promote to a byte-sized load if not loading an integral number of
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
- unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
- MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
+ unsigned NewWidth = SrcVT.getStoreSizeInBits();
+ MVT NVT = MVT::getIntegerVT(NewWidth);
SDOperand Ch;
// The extra bits are guaranteed to be zero, since we stored them that
Tmp2 = LegalizeOp(Ch);
} else if (SrcWidth & (SrcWidth - 1)) {
// If not loading a power-of-2 number of bits, expand as two loads.
- assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
+ assert(SrcVT.isExtended() && !SrcVT.isVector() &&
"Unsupported extload!");
unsigned RoundWidth = 1 << Log2_32(SrcWidth);
assert(RoundWidth < SrcWidth);
assert(ExtraWidth < RoundWidth);
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
"Load size not an integral number of bytes!");
- MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
- MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
+ MVT RoundVT = MVT::getIntegerVT(RoundWidth);
+ MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
SDOperand Lo, Hi, Ch;
unsigned IncrementSize;
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
+ getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
TLI);
}
}
case ISD::EXTRACT_ELEMENT: {
- MVT::ValueType OpTy = Node->getOperand(0).getValueType();
+ MVT OpTy = Node->getOperand(0).getValueType();
switch (getTypeAction(OpTy)) {
default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
case Legal:
if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
// 1 -> Hi
Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
- DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
+ DAG.getConstant(OpTy.getSizeInBits()/2,
TLI.getShiftAmountTy()));
Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
} else {
Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
break;
case Expand:
- if (!MVT::isVector(Tmp2.getValueType())) {
+ if (!Tmp2.getValueType().isVector()) {
SDOperand Lo, Hi;
ExpandOp(Tmp2, Lo, Hi);
} else {
SDNode *InVal = Tmp2.Val;
int InIx = Tmp2.ResNo;
- unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
- MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
+ unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
+ MVT EVT = InVal->getValueType(InIx).getVectorElementType();
// Figure out if there is a simple type corresponding to this Vector
// type. If so, convert to the vector type.
- MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+ MVT TVT = MVT::getVectorVT(EVT, NumElems);
if (TLI.isTypeLegal(TVT)) {
// Turn this into a return of the vector type.
Tmp2 = LegalizeOp(Tmp2);
break;
case Expand: {
SDOperand Lo, Hi;
- assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
+ assert(!Node->getOperand(i).getValueType().isExtended() &&
"FIXME: TODO: implement returning non-legal vector types!");
ExpandOp(Node->getOperand(i), Lo, Hi);
NewValues.push_back(Lo);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
break;
- } else if (getTypeAction(MVT::i32) == Legal) {
+ } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
// Otherwise, if the target supports 32-bit registers, use 2 32-bit
// stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
- MVT::ValueType VT = Tmp3.getValueType();
+ MVT VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
+ getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
TLI);
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Promote:
- assert(MVT::isVector(VT) && "Unknown legal promote case!");
+ assert(VT.isVector() && "Unknown legal promote case!");
Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
// If this is a vector type, then we have to calculate the increment as
// the product of the element size in bytes, and the number of elements
// in the high half of the vector.
- if (MVT::isVector(ST->getValue().getValueType())) {
+ if (ST->getValue().getValueType().isVector()) {
SDNode *InVal = ST->getValue().Val;
int InIx = ST->getValue().ResNo;
- MVT::ValueType InVT = InVal->getValueType(InIx);
- unsigned NumElems = MVT::getVectorNumElements(InVT);
- MVT::ValueType EVT = MVT::getVectorElementType(InVT);
+ MVT InVT = InVal->getValueType(InIx);
+ unsigned NumElems = InVT.getVectorNumElements();
+ MVT EVT = InVT.getVectorElementType();
// Figure out if there is a simple type corresponding to this Vector
// type. If so, convert to the vector type.
- MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+ MVT TVT = MVT::getVectorVT(EVT, NumElems);
if (TLI.isTypeLegal(TVT)) {
// Turn this into a normal store of the vector type.
Tmp3 = LegalizeOp(ST->getValue());
break;
} else {
SplitVectorOp(ST->getValue(), Lo, Hi);
- IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
- MVT::getSizeInBits(EVT)/8;
+ IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
+ EVT.getSizeInBits()/8;
}
} else {
ExpandOp(ST->getValue(), Lo, Hi);
- IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
+ IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
if (TLI.isBigEndian())
std::swap(Lo, Hi);
SVOffset, MVT::i8, isVolatile, Alignment);
}
- MVT::ValueType StVT = ST->getMemoryVT();
- unsigned StWidth = MVT::getSizeInBits(StVT);
+ MVT StVT = ST->getMemoryVT();
+ unsigned StWidth = StVT.getSizeInBits();
- if (StWidth != MVT::getStoreSizeInBits(StVT)) {
+ if (StWidth != StVT.getStoreSizeInBits()) {
// Promote to a byte-sized store with upper bits zero if not
// storing an integral number of bytes. For example, promote
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
- MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
+ MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, NVT, isVolatile, Alignment);
} else if (StWidth & (StWidth - 1)) {
// If not storing a power-of-2 number of bits, expand as two stores.
- assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
+ assert(StVT.isExtended() && !StVT.isVector() &&
"Unsupported truncstore!");
unsigned RoundWidth = 1 << Log2_32(StWidth);
assert(RoundWidth < StWidth);
assert(ExtraWidth < RoundWidth);
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
"Store size not an integral number of bytes!");
- MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
- MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
+ MVT RoundVT = MVT::getIntegerVT(RoundWidth);
+ MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
SDOperand Lo, Hi;
unsigned IncrementSize;
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
+ getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
TLI);
}
break;
case TargetLowering::Promote: {
- MVT::ValueType NVT =
+ MVT NVT =
TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
unsigned ExtOp, TruncOp;
- if (MVT::isVector(Tmp2.getValueType())) {
+ if (Tmp2.getValueType().isVector()) {
ExtOp = ISD::BIT_CONVERT;
TruncOp = ISD::BIT_CONVERT;
- } else if (MVT::isInteger(Tmp2.getValueType())) {
+ } else if (Tmp2.getValueType().isInteger()) {
ExtOp = ISD::ANY_EXTEND;
TruncOp = ISD::TRUNCATE;
} else {
// First step, figure out the appropriate operation to use.
// Allow SETCC to not be supported for all legal data types
// Mostly this targets FP
- MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
- MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
+ MVT NewInTy = Node->getOperand(0).getValueType();
+ MVT OldVT = NewInTy; OldVT = OldVT;
// Scan for the appropriate larger type to use.
while (1) {
- NewInTy = (MVT::ValueType)(NewInTy+1);
+ NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
- assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
+ assert(NewInTy.isInteger() == OldVT.isInteger() &&
"Fell off of the edge of the integer world");
- assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
+ assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
"Fell off of the edge of the floating point world");
// If the target supports SETCC of this type, use it.
if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
break;
}
- if (MVT::isInteger(NewInTy))
+ if (NewInTy.isInteger())
assert(0 && "Cannot promote Legal Integer SETCC yet");
else {
Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
case TargetLowering::Expand:
// Expand a setcc node into a select_cc of the same condition, lhs, and
// rhs that selects between const 1 (true) and const 0 (false).
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
Tmp3);
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Expand: {
- MVT::ValueType VT = Op.getValueType();
+ MVT VT = Op.getValueType();
// See if multiply or divide can be lowered using two-result operations.
SDVTList VTs = DAG.getVTList(VT, VT);
break;
}
- assert(MVT::isVector(Node->getValueType(0)) &&
+ assert(Node->getValueType(0).isVector() &&
"Cannot expand this binary operator!");
// Expand the operation into a bunch of nasty scalar code.
Result = LegalizeOp(UnrollVectorOp(Op));
case ISD::AND:
case ISD::OR:
case ISD::XOR: {
- MVT::ValueType OVT = Node->getValueType(0);
- MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
- assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
+ MVT OVT = Node->getValueType(0);
+ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+ assert(OVT.isVector() && "Cannot promote this BinOp!");
// Bit convert each of the values to the new type.
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
TargetLowering::Legal) {
// Get the sign bit of the RHS.
- MVT::ValueType IVT =
+ MVT IVT =
Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
}
// Otherwise, do bitwise ops!
- MVT::ValueType NVT =
+ MVT NVT =
Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
return Result;
case ISD::BUILD_PAIR: {
- MVT::ValueType PairTy = Node->getValueType(0);
+ MVT PairTy = Node->getValueType(0);
// TODO: handle the case where the Lo and Hi operands are not of legal type
Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
- DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
+ DAG.getConstant(PairTy.getSizeInBits()/2,
TLI.getShiftAmountTy()));
Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
break;
case TargetLowering::Expand: {
unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
bool isSigned = DivOpc == ISD::SDIV;
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
// See if remainder can be lowered using two-result operations.
SDVTList VTs = DAG.getVTList(VT, VT);
break;
}
- if (MVT::isInteger(VT)) {
+ if (VT.isInteger()) {
if (TLI.getOperationAction(DivOpc, VT) ==
TargetLowering::Legal) {
// X % Y -> X-X/Y*Y
Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
- } else if (MVT::isVector(VT)) {
+ } else if (VT.isVector()) {
Result = LegalizeOp(UnrollVectorOp(Op));
} else {
assert(VT == MVT::i32 &&
Result = ExpandLibCall(LC, Node, isSigned, Dummy);
}
} else {
- assert(MVT::isFloatingPoint(VT) &&
+ assert(VT.isFloatingPoint() &&
"remainder op must have integer or floating-point type");
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
Result = LegalizeOp(UnrollVectorOp(Op));
} else {
// Floating point mod -> fmod libcall.
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom:
SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
- DAG.getConstant(MVT::getSizeInBits(VT)/8,
+ DAG.getConstant(VT.getSizeInBits()/8,
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
Result = DAG.UpdateNodeOperands(Result, Tmp1);
break;
case TargetLowering::Promote: {
- MVT::ValueType OVT = Tmp1.getValueType();
- MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
- unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
+ MVT OVT = Tmp1.getValueType();
+ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+ unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
}
break;
case TargetLowering::Promote: {
- MVT::ValueType OVT = Tmp1.getValueType();
- MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+ MVT OVT = Tmp1.getValueType();
+ MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
// Zero extend the argument.
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
case ISD::CTTZ:
//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
- DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
+ DAG.getConstant(NVT.getSizeInBits(), NVT),
ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
- DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
+ DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
break;
case ISD::CTLZ:
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
- DAG.getConstant(MVT::getSizeInBits(NVT) -
- MVT::getSizeInBits(OVT), NVT));
+ DAG.getConstant(NVT.getSizeInBits() -
+ OVT.getSizeInBits(), NVT));
break;
}
break;
break;
case ISD::FABS: {
// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
Tmp2 = DAG.getConstantFP(0.0, VT);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
ISD::SETUGT);
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS: {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
// Expand unsupported unary vector operators by unrolling them.
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
Result = LegalizeOp(UnrollVectorOp(Op));
break;
}
}
break;
case ISD::FPOWI: {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
// Expand unsupported unary vector operators by unrolling them.
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
Result = LegalizeOp(UnrollVectorOp(Op));
break;
}
if (!isTypeLegal(Node->getOperand(0).getValueType())) {
Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
Node->getValueType(0));
- } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
+ } else if (Op.getOperand(0).getValueType().isVector()) {
// The input has to be a vector type, we have to either scalarize it, pack
// it, or convert it based on whether the input vector type is legal.
SDNode *InVal = Node->getOperand(0).Val;
int InIx = Node->getOperand(0).ResNo;
- unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
- MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
+ unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
+ MVT EVT = InVal->getValueType(InIx).getVectorElementType();
// Figure out if there is a simple type corresponding to this Vector
// type. If so, convert to the vector type.
- MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+ MVT TVT = MVT::getVectorVT(EVT, NumElems);
if (TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the vector input.
Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
case TargetLowering::Expand:
if (Node->getOpcode() == ISD::FP_TO_UINT) {
SDOperand True, False;
- MVT::ValueType VT = Node->getOperand(0).getValueType();
- MVT::ValueType NVT = Node->getValueType(0);
+ MVT VT = Node->getOperand(0).getValueType();
+ MVT NVT = Node->getValueType(0);
const uint64_t zero[] = {0, 0};
- APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
- APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
+ APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
+ APInt x = APInt::getSignBit(NVT.getSizeInBits());
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
Tmp2 = DAG.getConstantFP(apf, VT);
Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
}
break;
case Expand: {
- MVT::ValueType VT = Op.getValueType();
- MVT::ValueType OVT = Node->getOperand(0).getValueType();
+ MVT VT = Op.getValueType();
+ MVT OVT = Node->getOperand(0).getValueType();
// Convert ppcf128 to i32
if (OVT == MVT::ppcf128 && VT == MVT::i32) {
if (Node->getOpcode() == ISD::FP_TO_SINT) {
break;
case ISD::FP_EXTEND: {
- MVT::ValueType DstVT = Op.getValueType();
- MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
+ MVT DstVT = Op.getValueType();
+ MVT SrcVT = Op.getOperand(0).getValueType();
if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
// The only other way we can lower this is to turn it into a STORE,
// LOAD pair, targetting a temporary location (a stack slot).
break;
}
case ISD::FP_ROUND: {
- MVT::ValueType DstVT = Op.getValueType();
- MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
+ MVT DstVT = Op.getValueType();
+ MVT SrcVT = Op.getOperand(0).getValueType();
if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
if (SrcVT == MVT::ppcf128) {
SDOperand Lo;
case ISD::FP_ROUND_INREG:
case ISD::SIGN_EXTEND_INREG: {
Tmp1 = LegalizeOp(Node->getOperand(0));
- MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
+ MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
// If this operation is not supported, convert it to a shl/shr or load/store
// pair.
if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
// NOTE: we could fall back on load/store here too for targets without
// SAR. However, it is doubtful that any exist.
- unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
- MVT::getSizeInBits(ExtraVT);
+ unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
+ ExtraVT.getSizeInBits();
SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
Node->getOperand(0), ShiftCst);
return Op.ResNo ? Tmp1 : Result;
}
case ISD::FLT_ROUNDS_: {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action not supported for this op yet!");
case TargetLowering::Custom:
break;
}
case ISD::TRAP: {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action not supported for this op yet!");
case TargetLowering::Legal:
/// have the correct bits for the low portion of the register, but no guarantee
/// is made about the top bits: it may be zero, sign-extended, or garbage.
SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
- MVT::ValueType VT = Op.getValueType();
- MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
+ MVT VT = Op.getValueType();
+ MVT NVT = TLI.getTypeToTransformTo(VT);
assert(getTypeAction(VT) == Promote &&
"Caller should expand or legalize operands that are not promotable!");
- assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
+ assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
"Cannot promote to smaller type!");
SDOperand Tmp1, Tmp2, Tmp3;
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Legal:
Result = LegalizeOp(Node->getOperand(0));
- assert(Result.getValueType() >= NVT &&
+ assert(Result.getValueType().bitsGE(NVT) &&
"This truncation doesn't make sense!");
- if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
+ if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
break;
case Promote:
break;
}
- case ISD::ATOMIC_LCS: {
+ case ISD::ATOMIC_CMP_SWAP: {
+ AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
Tmp2 = PromoteOp(Node->getOperand(2));
Tmp3 = PromoteOp(Node->getOperand(3));
- Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
- Node->getOperand(1), Tmp2, Tmp3,
- cast<AtomicSDNode>(Node)->getVT());
+ Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
+ AtomNode->getBasePtr(), Tmp2, Tmp3,
+ AtomNode->getSrcValue(),
+ AtomNode->getAlignment());
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
break;
}
- case ISD::ATOMIC_LAS:
- case ISD::ATOMIC_LSS:
+ case ISD::ATOMIC_LOAD_ADD:
+ case ISD::ATOMIC_LOAD_SUB:
case ISD::ATOMIC_LOAD_AND:
case ISD::ATOMIC_LOAD_OR:
case ISD::ATOMIC_LOAD_XOR:
+ case ISD::ATOMIC_LOAD_NAND:
case ISD::ATOMIC_LOAD_MIN:
case ISD::ATOMIC_LOAD_MAX:
case ISD::ATOMIC_LOAD_UMIN:
case ISD::ATOMIC_LOAD_UMAX:
case ISD::ATOMIC_SWAP: {
+ AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
Tmp2 = PromoteOp(Node->getOperand(2));
- Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
- Node->getOperand(1), Tmp2,
- cast<AtomicSDNode>(Node)->getVT());
+ Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
+ AtomNode->getBasePtr(), Tmp2,
+ AtomNode->getSrcValue(),
+ AtomNode->getAlignment());
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
break;
// These operators require that their input be sign extended.
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
- if (MVT::isInteger(NVT)) {
+ if (NVT.isInteger()) {
Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
DAG.getValueType(VT));
Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
// Perform FP_ROUND: this is probably overly pessimistic.
- if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
+ if (NVT.isFloatingPoint() && NoExcessFPPrecision)
Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
DAG.getValueType(VT));
break;
// These operators require that their input be zero extended.
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
- assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
+ assert(NVT.isInteger() && "Operators don't apply to FP!");
Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
Tmp2 = Node->getOperand(1); // Get the pointer.
if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
- Result = TLI.CustomPromoteOperation(Tmp3, DAG);
+ Result = TLI.LowerOperation(Tmp3, DAG);
} else {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
- DAG.getConstant(MVT::getSizeInBits(VT)/8,
+ DAG.getConstant(VT.getSizeInBits()/8,
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
break;
}
- case ISD::SELECT:
+ case ISD::SELECT: {
Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
- Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
+
+ MVT VT2 = Tmp2.getValueType();
+ assert(VT2 == Tmp3.getValueType()
+ && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
+ // Ensure that the resulting node is at least the same size as the operands'
+ // value types, because we cannot assume that TLI.getSetCCValueType() is
+ // constant.
+ Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
break;
+ }
case ISD::SELECT_CC:
Tmp2 = PromoteOp(Node->getOperand(2)); // True
Tmp3 = PromoteOp(Node->getOperand(3)); // False
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
- DAG.getConstant(MVT::getSizeInBits(NVT) -
- MVT::getSizeInBits(VT),
+ DAG.getConstant(NVT.getSizeInBits() -
+ VT.getSizeInBits(),
TLI.getShiftAmountTy()));
break;
case ISD::CTPOP:
case ISD::CTTZ:
// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
- DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
+ DAG.getConstant(NVT.getSizeInBits(), NVT),
ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
- DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
+ DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
break;
case ISD::CTLZ:
//Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
- DAG.getConstant(MVT::getSizeInBits(NVT) -
- MVT::getSizeInBits(VT), NVT));
+ DAG.getConstant(NVT.getSizeInBits() -
+ VT.getSizeInBits(), NVT));
break;
}
break;
SDOperand Vec = Op.getOperand(0);
SDOperand Idx = Op.getOperand(1);
- MVT::ValueType TVT = Vec.getValueType();
- unsigned NumElems = MVT::getVectorNumElements(TVT);
+ MVT TVT = Vec.getValueType();
+ unsigned NumElems = TVT.getVectorNumElements();
switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
default: assert(0 && "This action is not supported yet!");
SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
// Add the offset to the index.
- unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
+ unsigned EltSize = Op.getValueType().getSizeInBits()/8;
Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, Idx.getValueType()));
- if (MVT::getSizeInBits(Idx.getValueType()) >
- MVT::getSizeInBits(TLI.getPointerTy()))
+ if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
else
Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
SDOperand Vec = Op.getOperand(0);
SDOperand Idx = LegalizeOp(Op.getOperand(1));
- unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
+ unsigned NumElems = Vec.getValueType().getVectorNumElements();
- if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
+ if (NumElems == Op.getValueType().getVectorNumElements()) {
// This must be an access of the desired vector length. Return it.
return Vec;
}
Tmp2 = PromoteOp(RHS); // RHS
// If this is an FP compare, the operands have already been extended.
- if (MVT::isInteger(LHS.getValueType())) {
- MVT::ValueType VT = LHS.getValueType();
- MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
+ if (LHS.getValueType().isInteger()) {
+ MVT VT = LHS.getValueType();
+ MVT NVT = TLI.getTypeToTransformTo(VT);
// Otherwise, we have to insert explicit sign or zero extends. Note
// that we could insert sign extends for ALL conditions, but zero extend
}
break;
case Expand: {
- MVT::ValueType VT = LHS.getValueType();
+ MVT VT = LHS.getValueType();
if (VT == MVT::f32 || VT == MVT::f64) {
// Expand into one or more soft-fp libcall(s).
- RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
+ RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
switch (cast<CondCodeSDNode>(CC)->get()) {
case ISD::SETEQ:
case ISD::SETOEQ:
default: assert(0 && "Unsupported FP setcc!");
}
}
-
+
SDOperand Dummy;
- Tmp1 = ExpandLibCall(LC1,
- DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
+ SDOperand Ops[2] = { LHS, RHS };
+ Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
CC);
- LHS = ExpandLibCall(LC2,
- DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
+ LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
/// a load from the stack slot to DestVT, extending it if needed.
/// The resultant code need not be legal.
SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
- MVT::ValueType SlotVT,
- MVT::ValueType DestVT) {
+ MVT SlotVT,
+ MVT DestVT) {
// Create the stack frame object.
SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
int SPFI = StackPtrFI->getIndex();
- unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
- unsigned SlotSize = MVT::getSizeInBits(SlotVT);
- unsigned DestSize = MVT::getSizeInBits(DestVT);
+ unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
+ unsigned SlotSize = SlotVT.getSizeInBits();
+ unsigned DestSize = DestVT.getSizeInBits();
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
assert(SrcSize == SlotSize && "Invalid store");
Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
PseudoSourceValue::getFixedStack(),
- SPFI, SlotVT);
+ SPFI);
}
// Result is a load from the stack slot.
// If all elements are constants, create a load from the constant pool.
if (isConstant) {
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
std::vector<Constant*> CV;
for (unsigned i = 0, e = NumElems; i != e; ++i) {
if (ConstantFPSDNode *V =
} else {
assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
const Type *OpNTy =
- MVT::getTypeForValueType(Node->getOperand(0).getValueType());
+ Node->getOperand(0).getValueType().getTypeForMVT();
CV.push_back(UndefValue::get(OpNTy));
}
}
if (SplatValue.Val) { // Splat of one value?
// Build the shuffle constant vector: <0, 0, 0, 0>
- MVT::ValueType MaskVT =
- MVT::getIntVectorWithNumElements(NumElems);
- SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
+ MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
+ SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
std::vector<SDOperand> ZeroVec(NumElems, Zero);
SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&ZeroVec[0], ZeroVec.size());
std::swap(Val1, Val2);
// Build the shuffle constant vector: e.g. <0, 4, 0, 4>
- MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
- MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT);
+ MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
+ MVT MaskEltVT = MaskVT.getVectorElementType();
std::vector<SDOperand> MaskVec(NumElems);
// Set elements of the shuffle mask for Val1.
// Otherwise, we can't handle this case efficiently. Allocate a sufficiently
// aligned object on the stack, store each element into it, then load
// the result as a vector.
- MVT::ValueType VT = Node->getValueType(0);
+ MVT VT = Node->getValueType(0);
// Create the stack frame object.
SDOperand FIPtr = DAG.CreateStackTemporary(VT);
// Emit a store of each element to the stack slot.
SmallVector<SDOperand, 8> Stores;
- unsigned TypeByteSize =
- MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
+ unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
// Store (in the right endianness) the elements to memory.
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
// Ignore undef elements.
ExpandOp(Op, LHSL, LHSH);
SDOperand Ops[] = { LHSL, LHSH, Amt };
- MVT::ValueType VT = LHSL.getValueType();
+ MVT VT = LHSL.getValueType();
Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
Hi = Lo.getValue(1);
}
assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
"This is not a shift!");
- MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
+ MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
SDOperand ShAmt = LegalizeOp(Amt);
- MVT::ValueType ShTy = ShAmt.getValueType();
- unsigned ShBits = MVT::getSizeInBits(ShTy);
- unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
- unsigned NVTBits = MVT::getSizeInBits(NVT);
+ MVT ShTy = ShAmt.getValueType();
+ unsigned ShBits = ShTy.getSizeInBits();
+ unsigned VTBits = Op.getValueType().getSizeInBits();
+ unsigned NVTBits = NVT.getSizeInBits();
// Handle the case when Amt is an immediate.
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
- const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
+ MVT ArgVT = Node->getOperand(i).getValueType();
+ const Type *ArgTy = ArgVT.getTypeForMVT();
Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
- const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
+ const Type *RetTy = Node->getValueType(0).getTypeForMVT();
std::pair<SDOperand,SDOperand> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
false, Callee, Args, DAG);
/// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
///
SDOperand SelectionDAGLegalize::
-ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
- MVT::ValueType SourceVT = Source.getValueType();
+ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
+ MVT SourceVT = Source.getValueType();
bool ExpandSource = getTypeAction(SourceVT) == Expand;
// Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0);
- else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
+ else if (DestTy.bitsGT(MVT::f32))
// FIXME: Avoid the extend by construction the right constantpool?
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
CPIdx,
else
assert(0 && "Unexpected conversion");
- MVT::ValueType SCVT = SignedConv.getValueType();
+ MVT SCVT = SignedConv.getValueType();
if (SCVT != DestTy) {
// Destination type needs to be expanded as well. The FADD now we are
// constructing will be expanded into a libcall.
- if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
- assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy));
+ if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
+ assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
SignedConv, SignedConv.getValue(1));
}
/// legal for the target.
SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDOperand Op0,
- MVT::ValueType DestVT) {
+ MVT DestVT) {
if (Op0.getValueType() == MVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
if (DestVT == MVT::f64) {
// do nothing
Result = Sub;
- } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
+ } else if (DestVT.bitsLT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
DAG.getIntPtrConstant(0));
- } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
+ } else if (DestVT.bitsGT(MVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
}
return Result;
// as a negative number. To counteract this, the dynamic code adds an
// offset depending on the data type.
uint64_t FF;
- switch (Op0.getValueType()) {
+ switch (Op0.getValueType().getSimpleVT()) {
default: assert(0 && "Unsupported integer type!");
case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
/// operation that takes a larger input.
SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
- MVT::ValueType DestVT,
+ MVT DestVT,
bool isSigned) {
// First step, figure out the appropriate *INT_TO_FP operation to use.
- MVT::ValueType NewInTy = LegalOp.getValueType();
+ MVT NewInTy = LegalOp.getValueType();
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
while (1) {
- NewInTy = (MVT::ValueType)(NewInTy+1);
- assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
+ NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
+ assert(NewInTy.isInteger() && "Ran out of possibilities!");
// If the target supports SINT_TO_FP of this type, use it.
switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
/// operation that returns a larger result.
SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
- MVT::ValueType DestVT,
+ MVT DestVT,
bool isSigned) {
// First step, figure out the appropriate FP_TO*INT operation to use.
- MVT::ValueType NewOutTy = DestVT;
+ MVT NewOutTy = DestVT;
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
while (1) {
- NewOutTy = (MVT::ValueType)(NewOutTy+1);
- assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
+ NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
+ assert(NewOutTy.isInteger() && "Ran out of possibilities!");
// If the target supports FP_TO_SINT returning this type, use it.
switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
// Okay, we found the operation and type to use.
SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
-
+
// If the operation produces an invalid type, it must be custom lowered. Use
// the target lowering hooks to expand it. Just keep the low part of the
// expanded operation, we know that we're truncating anyway.
if (getTypeAction(NewOutTy) == Expand) {
- Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
+ Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
assert(Operation.Val && "Didn't return anything");
}
-
+
// Truncate the result of the extended FP_TO_*INT operation to the desired
// size.
return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
///
SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
- MVT::ValueType VT = Op.getValueType();
- MVT::ValueType SHVT = TLI.getShiftAmountTy();
+ MVT VT = Op.getValueType();
+ MVT SHVT = TLI.getShiftAmountTy();
SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
- switch (VT) {
+ switch (VT.getSimpleVT()) {
default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
case MVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
};
- MVT::ValueType VT = Op.getValueType();
- MVT::ValueType ShVT = TLI.getShiftAmountTy();
- unsigned len = MVT::getSizeInBits(VT);
+ MVT VT = Op.getValueType();
+ MVT ShVT = TLI.getShiftAmountTy();
+ unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
// return popcount(~x);
//
// but see also: http://www.hackersdelight.org/HDcode/nlz.cc
- MVT::ValueType VT = Op.getValueType();
- MVT::ValueType ShVT = TLI.getShiftAmountTy();
- unsigned len = MVT::getSizeInBits(VT);
+ MVT VT = Op.getValueType();
+ MVT ShVT = TLI.getShiftAmountTy();
+ unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
// unless the target has ctlz but not ctpop, in which case we use:
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
- MVT::ValueType VT = Op.getValueType();
+ MVT VT = Op.getValueType();
SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
DAG.getNode(ISD::XOR, VT, Op, Tmp2),
if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
TLI.isOperationLegal(ISD::CTLZ, VT))
return DAG.getNode(ISD::SUB, VT,
- DAG.getConstant(MVT::getSizeInBits(VT), VT),
+ DAG.getConstant(VT.getSizeInBits(), VT),
DAG.getNode(ISD::CTLZ, VT, Tmp3));
return DAG.getNode(ISD::CTPOP, VT, Tmp3);
}
/// ExpandedNodes map is filled in for any results that are expanded, and the
/// Lo/Hi values are returned.
void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
- MVT::ValueType VT = Op.getValueType();
- MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
+ MVT VT = Op.getValueType();
+ MVT NVT = TLI.getTypeToTransformTo(VT);
SDNode *Node = Op.Val;
assert(getTypeAction(VT) == Expand && "Not an expanded type!");
- assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
- MVT::isVector(VT)) &&
- "Cannot expand to FP value or to larger int value!");
+ assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
+ VT.isVector()) && "Cannot expand to FP value or to larger int value!");
// See if we already expanded it.
DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
Lo = ExpandEXTRACT_VECTOR_ELT(Op);
return ExpandOp(Lo, Lo, Hi);
case ISD::UNDEF:
- NVT = TLI.getTypeToExpandTo(VT);
Lo = DAG.getNode(ISD::UNDEF, NVT);
Hi = DAG.getNode(ISD::UNDEF, NVT);
break;
case ISD::Constant: {
- unsigned NVTBits = MVT::getSizeInBits(NVT);
+ unsigned NVTBits = NVT.getSizeInBits();
const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
// The high part gets the sign extension from the lo-part. This handles
// things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, NVT, Lo,
- DAG.getConstant(MVT::getSizeInBits(NVT)-1,
+ DAG.getConstant(NVT.getSizeInBits()-1,
TLI.getShiftAmountTy()));
break;
case ISD::CTLZ: {
// ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
ExpandOp(Node->getOperand(0), Lo, Hi);
- SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
+ SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
ISD::SETNE);
case ISD::CTTZ: {
// cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
ExpandOp(Node->getOperand(0), Lo, Hi);
- SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
+ SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
ISD::SETNE);
}
// Increment the pointer to the other half.
- unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
+ unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
if (TLI.isBigEndian())
std::swap(Lo, Hi);
} else {
- MVT::ValueType EVT = LD->getMemoryVT();
+ MVT EVT = LD->getMemoryVT();
if ((VT == MVT::f64 && EVT == MVT::f32) ||
(VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
if (ExtType == ISD::SEXTLOAD) {
// The high part is obtained by SRA'ing all but one of the bits of the
// lo part.
- unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
+ unsigned LoSize = Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SRA, NVT, Lo,
DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
} else if (ExtType == ISD::ZEXTLOAD) {
// The high part is obtained by SRA'ing all but one of the bits of the lo
// part.
- unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
+ unsigned LoSize = Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SRA, NVT, Lo,
DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
break;
// If source operand will be expanded to the same type as VT, i.e.
// i64 <- f64, i32 <- f32, expand the source operand instead.
- MVT::ValueType VT0 = Node->getOperand(0).getValueType();
+ MVT VT0 = Node->getOperand(0).getValueType();
if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
ExpandOp(Node->getOperand(0), Lo, Hi);
break;
break;
}
- case ISD::ATOMIC_LCS: {
+ case ISD::ATOMIC_CMP_SWAP: {
SDOperand Tmp = TLI.LowerOperation(Op, DAG);
assert(Tmp.Val && "Node must be custom expanded!");
ExpandOp(Tmp.getValue(0), Lo, Hi);
// If the target wants to custom expand this, let them.
if (TLI.getOperationAction(Node->getOpcode(), VT) ==
TargetLowering::Custom) {
- Op = TLI.LowerOperation(Op, DAG);
- if (Op.Val) {
- ExpandOp(Op, Lo, Hi);
+ SDOperand Result = TLI.LowerOperation(Op, DAG);
+ if (Result.Val) {
+ ExpandOp(Result, Lo, Hi);
break;
}
}
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: {
bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
- MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
+ MVT SrcVT = Node->getOperand(0).getValueType();
// Promote the operand if needed. Do this before checking for
// ppcf128 so conversions of i16 and i8 work.
/// two smaller values, still of vector type.
void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
SDOperand &Hi) {
- assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
+ assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
SDNode *Node = Op.Val;
- unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
+ unsigned NumElements = Op.getValueType().getVectorNumElements();
assert(NumElements > 1 && "Cannot split a single element vector!");
- MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
+ MVT NewEltVT = Op.getValueType().getVectorElementType();
unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
- MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
- MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
+ MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
+ MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
// See if we already split it.
std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
// Build the low part.
SDOperand Mask = Node->getOperand(2);
SmallVector<SDOperand, 8> Ops;
- MVT::ValueType PtrVT = TLI.getPointerTy();
+ MVT PtrVT = TLI.getPointerTy();
// Insert all of the elements from the input that are needed. We use
// buildvector of extractelement here because the input vectors will have
SplitVectorOp(Node->getOperand(1), LL, LH);
SplitVectorOp(Node->getOperand(2), RL, RH);
- if (MVT::isVector(Cond.getValueType())) {
+ if (Cond.getValueType().isVector()) {
// Handle a vector merge.
SDOperand CL, CH;
SplitVectorOp(Cond, CL, CH);
}
break;
}
+ case ISD::SELECT_CC: {
+ SDOperand CondLHS = Node->getOperand(0);
+ SDOperand CondRHS = Node->getOperand(1);
+ SDOperand CondCode = Node->getOperand(4);
+
+ SDOperand LL, LH, RL, RH;
+ SplitVectorOp(Node->getOperand(2), LL, LH);
+ SplitVectorOp(Node->getOperand(3), RL, RH);
+
+ // Handle a simple select with vector operands.
+ Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
+ LL, RL, CondCode);
+ Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
+ LH, RH, CondCode);
+ break;
+ }
case ISD::VSETCC: {
SDOperand LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
bool isVolatile = LD->isVolatile();
Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
- unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
+ unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
// We know the result is a vector. The input may be either a vector or a
// scalar value.
SDOperand InOp = Node->getOperand(0);
- if (!MVT::isVector(InOp.getValueType()) ||
- MVT::getVectorNumElements(InOp.getValueType()) == 1) {
+ if (!InOp.getValueType().isVector() ||
+ InOp.getValueType().getVectorNumElements() == 1) {
// The input is a scalar or single-element vector.
// Lower to a store/load so that it can be split.
// FIXME: this could be improved probably.
/// (e.g. v1f32), convert it into the equivalent operation that returns a
/// scalar (e.g. f32) value.
SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
- assert(MVT::isVector(Op.getValueType()) &&
- "Bad ScalarizeVectorOp invocation!");
+ assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
SDNode *Node = Op.Val;
- MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
- assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
+ MVT NewVT = Op.getValueType().getVectorElementType();
+ assert(Op.getValueType().getVectorNumElements() == 1);
// See if we already scalarized it.
std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
Result = Node->getOperand(0);
assert(Result.getValueType() == NewVT);
break;
- case ISD::BIT_CONVERT:
- Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
+ case ISD::BIT_CONVERT: {
+ SDOperand Op0 = Op.getOperand(0);
+ if (Op0.getValueType().getVectorNumElements() == 1)
+ Op0 = ScalarizeVectorOp(Op0);
+ Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
break;
+ }
case ISD::SELECT:
Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
ScalarizeVectorOp(Op.getOperand(1)),
ScalarizeVectorOp(Op.getOperand(2)));
break;
+ case ISD::SELECT_CC:
+ Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
+ Node->getOperand(1),
+ ScalarizeVectorOp(Op.getOperand(2)),
+ ScalarizeVectorOp(Op.getOperand(3)),
+ Node->getOperand(4));
+ break;
case ISD::VSETCC: {
SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
projects / oota-llvm.git / blobdiff