#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/DwarfWriter.h"
+#include "llvm/Analysis/DebugInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/GlobalVariable.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/MathExtras.h"
class VISIBILITY_HIDDEN SelectionDAGLegalize {
TargetLowering &TLI;
SelectionDAG &DAG;
+ bool TypesNeedLegalizing;
+ bool Fast;
// Libcall insertion helpers.
-
+
/// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
/// legalized. We use this to ensure that calls are properly serialized
/// against each other, including inserted libcalls.
SDValue LastCALLSEQ_END;
-
+
/// IsLegalizingCall - This member is used *only* for purposes of providing
- /// helpful assertions that a libcall isn't created while another call is
+ /// helpful assertions that a libcall isn't created while another call is
/// being legalized (which could lead to non-serialized call sequences).
bool IsLegalizingCall;
-
+
+ /// IsLegalizingCallArguments - This member is used only for the purpose
+ /// of providing assert to check for LegalizeTypes because legalizing an
+ /// operation might introduce call nodes that might need type legalization.
+ bool IsLegalizingCallArgs;
+
enum LegalizeAction {
Legal, // The target natively supports this operation.
Promote, // This operation should be executed in a larger type.
Expand // Try to expand this to other ops, otherwise use a libcall.
};
-
+
/// ValueTypeActions - This is a bitvector that contains two bits for each
/// value type, where the two bits correspond to the LegalizeAction enum.
/// This can be queried with "getTypeAction(VT)".
/// which operands are the split version of the input. This allows us
/// to avoid splitting the same node more than once.
std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
-
+
/// ScalarizedNodes - For nodes that need to be converted from vector types to
/// scalar types, this contains the mapping of ones we have already
/// processed to the result.
std::map<SDValue, SDValue> ScalarizedNodes;
-
+
/// WidenNodes - For nodes that need to be widened from one vector type to
/// another, this contains the mapping of those that we have already widen.
/// This allows us to avoid widening more than once.
}
public:
- explicit SelectionDAGLegalize(SelectionDAG &DAG);
+ explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
+ bool fast);
/// getTypeAction - Return how we should legalize values of this type, either
/// it is already legal or we need to expand it into multiple registers of
/// HandleOp - Legalize, Promote, or Expand the specified operand as
/// appropriate for its type.
void HandleOp(SDValue Op);
-
+
/// LegalizeOp - We know that the specified value has a legal type.
/// Recursively ensure that the operands have legal types, then return the
/// result.
SDValue LegalizeOp(SDValue O);
-
+
/// UnrollVectorOp - We know that the given vector has a legal type, however
/// the operation it performs is not legal and is an operation that we have
/// no way of lowering. "Unroll" the vector, splitting out the scalars and
/// operating on each element individually.
SDValue UnrollVectorOp(SDValue O);
-
+
/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
/// is necessary to spill the vector being inserted into to memory, perform
/// the insert there, and then read the result back.
SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
- SDValue Idx);
+ SDValue Idx, DebugLoc dl);
/// PromoteOp - Given an operation that produces a value in an invalid type,
/// promote it to compute the value into a larger type. The produced value
/// types.
void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
- /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
+ /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
/// (e.g., v3i32 to v4i32). The produced value will have the correct value
/// for the existing elements but no guarantee is made about the new elements
/// at the end of the vector: it may be zero, ones, or garbage. This is useful
/// SplitVectorOp - Given an operand of vector type, break it down into
/// two smaller values.
void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
-
+
/// ScalarizeVectorOp - Given an operand of single-element vector type
/// (e.g. v1f32), convert it into the equivalent operation that returns a
/// scalar (e.g. f32) value.
SDValue ScalarizeVectorOp(SDValue O);
-
+
/// Useful 16 element vector type that is used to pass operands for widening.
- typedef SmallVector<SDValue, 16> SDValueVector;
-
+ typedef SmallVector<SDValue, 16> SDValueVector;
+
/// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
/// the LdChain contains a single load and false if it contains a token
/// factor for multiple loads. It takes
/// LdChain: location to return the load chain
/// Op: load operation to widen
/// NVT: widen vector result type we want for the load
- bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
+ bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
SDValue Op, MVT NVT);
-
+
/// Helper genWidenVectorLoads - Helper function to generate a set of
/// loads to load a vector with a resulting wider type. It takes
/// LdChain: list of chains for the load we have generated
/// SVOffset: memory disambiugation offset
/// Alignment: alignment of the memory
/// isVolatile: volatile load
- /// LdWidth: width of memory that we want to load
+ /// LdWidth: width of memory that we want to load
/// ResType: the wider result result type for the resulting loaded vector
SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
SDValue BasePtr, const Value *SV,
int SVOffset, unsigned Alignment,
bool isVolatile, unsigned LdWidth,
- MVT ResType);
-
+ MVT ResType, DebugLoc dl);
+
/// StoreWidenVectorOp - Stores a widen vector into non widen memory
/// location. It takes
/// ST: store node that we want to replace
/// Chain: incoming store chain
/// BasePtr: base address of where we want to store into
- SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
+ SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
SDValue BasePtr);
-
+
/// Helper genWidenVectorStores - Helper function to generate a set of
/// stores to store a widen vector into non widen memory
// It takes
// SVOffset: memory disambiugation offset
// Alignment: alignment of the memory
// isVolatile: volatile lod
- // ValOp: value to store
- // StWidth: width of memory that we want to store
+ // ValOp: value to store
+ // StWidth: width of memory that we want to store
void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
SDValue BasePtr, const Value *SV,
int SVOffset, unsigned Alignment,
bool isVolatile, SDValue ValOp,
- unsigned StWidth);
-
+ unsigned StWidth, DebugLoc dl);
+
/// isShuffleLegal - Return non-null if a vector shuffle is legal with the
/// specified mask and type. Targets can specify exactly which masks they
/// support and the code generator is tasked with not creating illegal masks.
/// If this is a legal shuffle, this method returns the (possibly promoted)
/// build_vector Mask. If it's not a legal shuffle, it returns null.
SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
-
+
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
- void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
- void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
- void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
- LegalizeSetCCOperands(LHS, RHS, CC);
- LegalizeSetCCCondCode(VT, LHS, RHS, CC);
+ void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
+ DebugLoc dl);
+ void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
+ DebugLoc dl);
+ void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
+ DebugLoc dl) {
+ LegalizeSetCCOperands(LHS, RHS, CC, dl);
+ LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
}
-
+
SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
SDValue &Hi);
- SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
+ SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
- SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
+ SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
SDValue ExpandBUILD_VECTOR(SDNode *Node);
SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
- SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
- SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
- SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
- SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
-
- SDValue ExpandBSWAP(SDValue Op);
- SDValue ExpandBitCount(unsigned Opc, SDValue Op);
+ SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
+ SDValue Op, DebugLoc dl);
+ SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
+ DebugLoc dl);
+ SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
+ DebugLoc dl);
+ SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
+ DebugLoc dl);
+
+ SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
+ SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
- SDValue &Lo, SDValue &Hi);
+ SDValue &Lo, SDValue &Hi, DebugLoc dl);
void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
- SDValue &Lo, SDValue &Hi);
+ SDValue &Lo, SDValue &Hi, DebugLoc dl);
SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
SDValue InOp = Mask.getOperand(i);
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
if (InOp.getOpcode() == ISD::UNDEF)
- Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
+ Ops.push_back(DAG.getUNDEF(EltVT));
else {
unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
}
}
}
- Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
+ Mask = DAG.getBUILD_VECTOR(NVT, Mask.getDebugLoc(), &Ops[0], Ops.size());
}
VT = NVT;
break;
return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
}
-SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
- : TLI(dag.getTargetLoweringInfo()), DAG(dag),
- ValueTypeActions(TLI.getValueTypeActions()) {
+SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
+ bool types, bool fast)
+ : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
+ Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
assert(MVT::LAST_VALUETYPE <= 32 &&
"Too many value types for ValueTypeActions to hold!");
}
void SelectionDAGLegalize::LegalizeDAG() {
LastCALLSEQ_END = DAG.getEntryNode();
IsLegalizingCall = false;
-
+ IsLegalizingCallArgs = false;
+
// The legalize process is inherently a bottom-up recursive process (users
// legalize their uses before themselves). Given infinite stack space, we
// could just start legalizing on the root and traverse the whole graph. In
return Node;
if (Node->use_empty())
return 0; // No CallSeqEnd
-
+
// The chain is usually at the end.
SDValue TheChain(Node, Node->getNumValues()-1);
if (TheChain.getValueType() != MVT::Other) {
TheChain = SDValue(Node, i);
break;
}
-
- // Otherwise, we walked into a node without a chain.
+
+ // Otherwise, we walked into a node without a chain.
if (TheChain.getValueType() != MVT::Other)
return 0;
}
}
-
+
for (SDNode::use_iterator UI = Node->use_begin(),
E = Node->use_end(); UI != E; ++UI) {
-
+
// Make sure to only follow users of our token chain.
SDNode *User = *UI;
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
return 0;
}
-/// FindCallStartFromCallEnd - Given a chained node that is part of a call
+/// FindCallStartFromCallEnd - Given a chained node that is part of a call
/// sequence, find the CALLSEQ_START node that initiates the call sequence.
static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
assert(Node && "Didn't find callseq_start for a call??");
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
-
+
assert(Node->getOperand(0).getValueType() == MVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
}
/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
-/// see if any uses can reach Dest. If no dest operands can get to dest,
+/// see if any uses can reach Dest. If no dest operands can get to dest,
/// legalize them, legalize ourself, and return false, otherwise, return true.
///
/// Keep track of the nodes we fine that actually do lead to Dest in
bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
if (N == Dest) return true; // N certainly leads to Dest :)
-
+
// If we've already processed this node and it does lead to Dest, there is no
// need to reprocess it.
if (NodesLeadingTo.count(N)) return true;
-
+
// If the first result of this node has been already legalized, then it cannot
// reach N.
switch (getTypeAction(N->getValueType(0))) {
- case Legal:
+ case Legal:
if (LegalizedNodes.count(SDValue(N, 0))) return false;
break;
case Promote:
if (ExpandedNodes.count(SDValue(N, 0))) return false;
break;
}
-
+
// Okay, this node has not already been legalized. Check and legalize all
// operands. If none lead to Dest, then we can legalize this node.
bool OperandsLeadToDest = false;
/// appropriate for its type.
void SelectionDAGLegalize::HandleOp(SDValue Op) {
MVT VT = Op.getValueType();
+ // If the type legalizer was run then we should never see any illegal result
+ // types here except for target constants (the type legalizer does not touch
+ // those) or for build vector used as a mask for a vector shuffle.
+ // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
+ assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
+ IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant ||
+ Op.getOpcode() == ISD::BUILD_VECTOR) &&
+ "Illegal type introduced after type legalization?");
switch (getTypeAction(VT)) {
default: assert(0 && "Bad type action!");
case Legal: (void)LegalizeOp(Op); break;
/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
/// a load from the constant pool.
static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
- SelectionDAG &DAG, TargetLowering &TLI) {
+ SelectionDAG &DAG, const TargetLowering &TLI) {
bool Extend = false;
+ DebugLoc dl = CFP->getDebugLoc();
// If a FP immediate is precise when represented as a float and if the
// target can do an extending load from float to double, we put it into
SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
if (Extend)
- return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
+ return DAG.getExtLoad(ISD::EXTLOAD, dl,
+ OrigVT, DAG.getEntryNode(),
CPIdx, PseudoSourceValue::getConstantPool(),
0, VT, false, Alignment);
- return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
+ return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0, false, Alignment);
}
/// operations.
static
SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
- SelectionDAG &DAG, TargetLowering &TLI) {
+ SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ DebugLoc dl = Node->getDebugLoc();
MVT VT = Node->getValueType(0);
MVT SrcVT = Node->getOperand(1).getValueType();
assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
SDValue Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
- Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
- SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
- SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
+ Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
+ SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
+ Node->getOperand(1));
+ SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
// Shift right or sign-extend it if the two operands have different types.
int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
if (SizeDiff > 0) {
- SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
+ SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
- SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
+ SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
} else if (SizeDiff < 0) {
- SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
- SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
+ SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
+ SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
}
SDValue Mask2 = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
: DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
- Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
- SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
- Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
+ Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
+ SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
+ Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
// Or the value with the sign bit.
- Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
+ Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
return Result;
}
/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
static
SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
- TargetLowering &TLI) {
+ const TargetLowering &TLI) {
SDValue Chain = ST->getChain();
SDValue Ptr = ST->getBasePtr();
SDValue Val = ST->getValue();
MVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
int SVOffset = ST->getSrcValueOffset();
+ DebugLoc dl = ST->getDebugLoc();
if (ST->getMemoryVT().isFloatingPoint() ||
ST->getMemoryVT().isVector()) {
- // Expand to a bitconvert of the value to the integer type of the
- // same size, then a (misaligned) int store.
- MVT intVT;
- if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
- intVT = MVT::i128;
- else if (VT.is64BitVector() || VT==MVT::f64)
- intVT = MVT::i64;
- else if (VT==MVT::f32)
- intVT = MVT::i32;
- else
- assert(0 && "Unaligned store of unsupported type");
+ MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
+ if (TLI.isTypeLegal(intVT)) {
+ // Expand to a bitconvert of the value to the integer type of the
+ // same size, then a (misaligned) int store.
+ // FIXME: Does not handle truncating floating point stores!
+ SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
+ return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
+ SVOffset, ST->isVolatile(), Alignment);
+ } else {
+ // Do a (aligned) store to a stack slot, then copy from the stack slot
+ // to the final destination using (unaligned) integer loads and stores.
+ MVT StoredVT = ST->getMemoryVT();
+ MVT RegVT =
+ TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
+ unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
+ unsigned RegBytes = RegVT.getSizeInBits() / 8;
+ unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
+
+ // Make sure the stack slot is also aligned for the register type.
+ SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
+
+ // Perform the original store, only redirected to the stack slot.
+ SDValue Store = DAG.getTruncStore(Chain, dl,
+ Val, StackPtr, NULL, 0,StoredVT);
+ SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
+ SmallVector<SDValue, 8> Stores;
+ unsigned Offset = 0;
+
+ // Do all but one copies using the full register width.
+ for (unsigned i = 1; i < NumRegs; i++) {
+ // Load one integer register's worth from the stack slot.
+ SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
+ // Store it to the final location. Remember the store.
+ Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
+ ST->getSrcValue(), SVOffset + Offset,
+ ST->isVolatile(),
+ MinAlign(ST->getAlignment(), Offset)));
+ // Increment the pointers.
+ Offset += RegBytes;
+ StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
+ Increment);
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
+ }
- SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
- return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
- SVOffset, ST->isVolatile(), Alignment);
+ // The last store may be partial. Do a truncating store. On big-endian
+ // machines this requires an extending load from the stack slot to ensure
+ // that the bits are in the right place.
+ MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
+
+ // Load from the stack slot.
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
+ NULL, 0, MemVT);
+
+ Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
+ ST->getSrcValue(), SVOffset + Offset,
+ MemVT, ST->isVolatile(),
+ MinAlign(ST->getAlignment(), Offset)));
+ // The order of the stores doesn't matter - say it with a TokenFactor.
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+ Stores.size());
+ }
}
assert(ST->getMemoryVT().isInteger() &&
!ST->getMemoryVT().isVector() &&
// Divide the stored value in two parts.
SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
SDValue Lo = Val;
- SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
+ SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
// Store the two parts
SDValue Store1, Store2;
- Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
+ Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
ST->getSrcValue(), SVOffset, NewStoredVT,
ST->isVolatile(), Alignment);
- Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
Alignment = MinAlign(Alignment, IncrementSize);
- Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
+ Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
ST->getSrcValue(), SVOffset + IncrementSize,
NewStoredVT, ST->isVolatile(), Alignment);
- return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
}
/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
static
SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
- TargetLowering &TLI) {
+ const TargetLowering &TLI) {
int SVOffset = LD->getSrcValueOffset();
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
MVT VT = LD->getValueType(0);
MVT LoadedVT = LD->getMemoryVT();
+ DebugLoc dl = LD->getDebugLoc();
if (VT.isFloatingPoint() || VT.isVector()) {
- // Expand to a (misaligned) integer load of the same size,
- // then bitconvert to floating point or vector.
- MVT intVT;
- if (LoadedVT.is128BitVector() ||
- LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
- intVT = MVT::i128;
- else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
- intVT = MVT::i64;
- else if (LoadedVT == MVT::f32)
- intVT = MVT::i32;
- else
- assert(0 && "Unaligned load of unsupported type");
-
- SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
- SVOffset, LD->isVolatile(),
+ MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
+ if (TLI.isTypeLegal(intVT)) {
+ // Expand to a (misaligned) integer load of the same size,
+ // then bitconvert to floating point or vector.
+ SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
+ SVOffset, LD->isVolatile(),
LD->getAlignment());
- SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
- if (VT.isFloatingPoint() && LoadedVT != VT)
- Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
+ SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
+ if (VT.isFloatingPoint() && LoadedVT != VT)
+ Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
+
+ SDValue Ops[] = { Result, Chain };
+ return DAG.getMergeValues(Ops, 2, dl);
+ } else {
+ // Copy the value to a (aligned) stack slot using (unaligned) integer
+ // loads and stores, then do a (aligned) load from the stack slot.
+ MVT RegVT = TLI.getRegisterType(intVT);
+ unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
+ unsigned RegBytes = RegVT.getSizeInBits() / 8;
+ unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
+
+ // Make sure the stack slot is also aligned for the register type.
+ SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
+
+ SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
+ SmallVector<SDValue, 8> Stores;
+ SDValue StackPtr = StackBase;
+ unsigned Offset = 0;
+
+ // Do all but one copies using the full register width.
+ for (unsigned i = 1; i < NumRegs; i++) {
+ // Load one integer register's worth from the original location.
+ SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
+ SVOffset + Offset, LD->isVolatile(),
+ MinAlign(LD->getAlignment(), Offset));
+ // Follow the load with a store to the stack slot. Remember the store.
+ Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
+ NULL, 0));
+ // Increment the pointers.
+ Offset += RegBytes;
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
+ StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
+ Increment);
+ }
+
+ // The last copy may be partial. Do an extending load.
+ MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
+ LD->getSrcValue(), SVOffset + Offset,
+ MemVT, LD->isVolatile(),
+ MinAlign(LD->getAlignment(), Offset));
+ // Follow the load with a store to the stack slot. Remember the store.
+ // On big-endian machines this requires a truncating store to ensure
+ // that the bits end up in the right place.
+ Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
+ NULL, 0, MemVT));
+
+ // The order of the stores doesn't matter - say it with a TokenFactor.
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+ Stores.size());
- SDValue Ops[] = { Result, Chain };
- return DAG.getMergeValues(Ops, 2);
+ // Finally, perform the original load only redirected to the stack slot.
+ Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
+ NULL, 0, LoadedVT);
+
+ // Callers expect a MERGE_VALUES node.
+ SDValue Ops[] = { Load, TF };
+ return DAG.getMergeValues(Ops, 2, dl);
+ }
}
assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
"Unaligned load of unsupported type.");
MVT NewLoadedVT;
NewLoadedVT = MVT::getIntegerVT(NumBits/2);
NumBits >>= 1;
-
+
unsigned Alignment = LD->getAlignment();
unsigned IncrementSize = NumBits / 8;
ISD::LoadExtType HiExtType = LD->getExtensionType();
// Load the value in two parts
SDValue Lo, Hi;
if (TLI.isLittleEndian()) {
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
- Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
- Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
+ Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
MinAlign(Alignment, IncrementSize));
} else {
- Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
- NewLoadedVT,LD->isVolatile(), Alignment);
- Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
+ Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
+ SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
MinAlign(Alignment, IncrementSize));
}
// aggregate the two parts
SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
- SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
- Result = DAG.getNode(ISD::OR, VT, Result, Lo);
+ SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
+ Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
- SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
SDValue Ops[] = { Result, TF };
- return DAG.getMergeValues(Ops, 2);
+ return DAG.getMergeValues(Ops, 2, dl);
}
/// UnrollVectorOp - We know that the given vector has a legal type, however
"Can't unroll a vector with multiple results!");
unsigned NE = VT.getVectorNumElements();
MVT EltVT = VT.getVectorElementType();
+ DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 8> Scalars;
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
if (OperandVT.isVector()) {
// A vector operand; extract a single element.
MVT OperandEltVT = OperandVT.getVectorElementType();
- Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
+ Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
OperandEltVT,
Operand,
DAG.getConstant(i, MVT::i32));
Operands[j] = Operand;
}
}
- Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
- &Operands[0], Operands.size()));
+
+ switch (Op.getOpcode()) {
+ default:
+ Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
+ &Operands[0], Operands.size()));
+ break;
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
+ case ISD::ROTL:
+ case ISD::ROTR:
+ Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
+ DAG.getShiftAmountOperand(Operands[1])));
+ break;
+ }
}
- return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
+ return DAG.getBUILD_VECTOR(VT, dl, &Scalars[0], Scalars.size());
}
/// GetFPLibCall - Return the right libcall for the given floating point type.
/// is necessary to spill the vector being inserted into to memory, perform
/// the insert there, and then read the result back.
SDValue SelectionDAGLegalize::
-PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
+PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
+ DebugLoc dl) {
SDValue Tmp1 = Vec;
SDValue Tmp2 = Val;
SDValue Tmp3 = Idx;
-
+
// If the target doesn't support this, we have to spill the input vector
// to a temporary stack slot, update the element, then reload it. This is
// badness. We could also load the value into a vector register (either
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
// Store the vector.
- SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
// Truncate or zero extend offset to target pointer type.
unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
- Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
+ Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
// Add the offset to the index.
unsigned EltSize = EltVT.getSizeInBits()/8;
- Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
- SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
+ Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
+ SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
// Store the scalar value.
- Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
+ Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
// Load the updated vector.
- return DAG.getLoad(VT, Ch, StackPtr,
+ return DAG.getLoad(VT, dl, Ch, StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
}
+
/// LegalizeOp - We know that the specified value has a legal type, and
/// that its operands are legal. Now ensure that the operation itself
/// is legal, recursively ensuring that the operands' operations remain
SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
return Op;
-
+
assert(isTypeLegal(Op.getValueType()) &&
"Caller should expand or promote operands that are not legal!");
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
// If this operation defines any values that cannot be represented in a
// register on this target, make sure to expand or promote them.
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
SDValue Result = Op;
bool isCustom = false;
-
+
switch (Node->getOpcode()) {
case ISD::FrameIndex:
case ISD::EntryToken:
// The only option for these nodes is to custom lower them. If the target
// does not custom lower them, then return zero.
Tmp1 = TLI.LowerOperation(Op, DAG);
- if (Tmp1.getNode())
+ if (Tmp1.getNode())
Result = Tmp1;
else
Result = DAG.getConstant(0, TLI.getPointerTy());
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
unsigned Reg = TLI.getExceptionAddressRegister();
- Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
+ Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
}
break;
case TargetLowering::Custom:
// Fall Thru
case TargetLowering::Legal: {
SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
- Result = DAG.getMergeValues(Ops, 2);
+ Result = DAG.getMergeValues(Ops, 2, dl);
break;
}
}
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
unsigned Reg = TLI.getExceptionSelectorRegister();
- Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
+ Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
}
break;
case TargetLowering::Custom:
// Fall Thru
case TargetLowering::Legal: {
SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
- Result = DAG.getMergeValues(Ops, 2);
+ Result = DAG.getMergeValues(Ops, 2, dl);
break;
}
}
}
break;
}
-
+
case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_WO_CHAIN:
case ISD::INTRINSIC_VOID: {
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
Ops.push_back(LegalizeOp(Node->getOperand(i)));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
-
+
// Allow the target to custom lower its intrinsics if it wants to.
- if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
+ if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
TargetLowering::Custom) {
Tmp3 = TLI.LowerOperation(Result, DAG);
if (Tmp3.getNode()) Result = Tmp3;
assert(Result.getNode()->getNumValues() == 2 &&
"Cannot return more than two values!");
- // Since loads produce two values, make sure to remember that we
+ // Since loads produce two values, make sure to remember that we
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.getResNo());
- }
+ }
case ISD::DBG_STOPPOINT:
assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
-
+
switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
case TargetLowering::Promote:
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
- MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
- bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
-
+ DwarfWriter *DW = DAG.getDwarfWriter();
+ bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
+ MVT::Other);
+ bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
+
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
- if (MMI && (useDEBUG_LOC || useLABEL)) {
- const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
- unsigned SrcFile = MMI->RecordSource(CompileUnit);
+ GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
+ if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
+ DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
+ unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
+ CU.getFilename());
unsigned Line = DSP->getLine();
unsigned Col = DSP->getColumn();
-
- if (useDEBUG_LOC) {
- SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
+
+ if (Fast) {
+ // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
+ // won't hurt anything.
+ if (useDEBUG_LOC) {
+ SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
DAG.getConstant(Col, MVT::i32),
DAG.getConstant(SrcFile, MVT::i32) };
- Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
+ Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
+ } else {
+ unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
+ Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
+ }
} else {
- unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
- Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
+ Result = Tmp1; // chain
}
} else {
Result = Tmp1; // chain
Result = LegalizeOp(Node->getOperand(0));
break;
}
- break;
-
+ break;
+
case ISD::DEBUG_LOC:
assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
break;
}
}
- break;
+ break;
case ISD::DBG_LABEL:
case ISD::EH_LABEL:
break;
}
- case ISD::ATOMIC_CMP_SWAP_8:
- case ISD::ATOMIC_CMP_SWAP_16:
- case ISD::ATOMIC_CMP_SWAP_32:
- case ISD::ATOMIC_CMP_SWAP_64: {
+ case ISD::ATOMIC_CMP_SWAP: {
unsigned int num_operands = 4;
assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
SDValue Ops[4];
for (unsigned int x = 0; x < num_operands; ++x)
Ops[x] = LegalizeOp(Node->getOperand(x));
Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom:
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
return Result.getValue(Op.getResNo());
}
- case ISD::ATOMIC_LOAD_ADD_8:
- case ISD::ATOMIC_LOAD_SUB_8:
- case ISD::ATOMIC_LOAD_AND_8:
- case ISD::ATOMIC_LOAD_OR_8:
- case ISD::ATOMIC_LOAD_XOR_8:
- case ISD::ATOMIC_LOAD_NAND_8:
- case ISD::ATOMIC_LOAD_MIN_8:
- case ISD::ATOMIC_LOAD_MAX_8:
- case ISD::ATOMIC_LOAD_UMIN_8:
- case ISD::ATOMIC_LOAD_UMAX_8:
- case ISD::ATOMIC_SWAP_8:
- case ISD::ATOMIC_LOAD_ADD_16:
- case ISD::ATOMIC_LOAD_SUB_16:
- case ISD::ATOMIC_LOAD_AND_16:
- case ISD::ATOMIC_LOAD_OR_16:
- case ISD::ATOMIC_LOAD_XOR_16:
- case ISD::ATOMIC_LOAD_NAND_16:
- case ISD::ATOMIC_LOAD_MIN_16:
- case ISD::ATOMIC_LOAD_MAX_16:
- case ISD::ATOMIC_LOAD_UMIN_16:
- case ISD::ATOMIC_LOAD_UMAX_16:
- case ISD::ATOMIC_SWAP_16:
- case ISD::ATOMIC_LOAD_ADD_32:
- case ISD::ATOMIC_LOAD_SUB_32:
- case ISD::ATOMIC_LOAD_AND_32:
- case ISD::ATOMIC_LOAD_OR_32:
- case ISD::ATOMIC_LOAD_XOR_32:
- case ISD::ATOMIC_LOAD_NAND_32:
- case ISD::ATOMIC_LOAD_MIN_32:
- case ISD::ATOMIC_LOAD_MAX_32:
- case ISD::ATOMIC_LOAD_UMIN_32:
- case ISD::ATOMIC_LOAD_UMAX_32:
- case ISD::ATOMIC_SWAP_32:
- case ISD::ATOMIC_LOAD_ADD_64:
- case ISD::ATOMIC_LOAD_SUB_64:
- case ISD::ATOMIC_LOAD_AND_64:
- case ISD::ATOMIC_LOAD_OR_64:
- case ISD::ATOMIC_LOAD_XOR_64:
- case ISD::ATOMIC_LOAD_NAND_64:
- case ISD::ATOMIC_LOAD_MIN_64:
- case ISD::ATOMIC_LOAD_MAX_64:
- case ISD::ATOMIC_LOAD_UMIN_64:
- case ISD::ATOMIC_LOAD_UMAX_64:
- case ISD::ATOMIC_SWAP_64: {
+ case ISD::ATOMIC_LOAD_ADD:
+ case ISD::ATOMIC_LOAD_SUB:
+ case ISD::ATOMIC_LOAD_AND:
+ case ISD::ATOMIC_LOAD_OR:
+ case ISD::ATOMIC_LOAD_XOR:
+ case ISD::ATOMIC_LOAD_NAND:
+ case ISD::ATOMIC_LOAD_MIN:
+ case ISD::ATOMIC_LOAD_MAX:
+ case ISD::ATOMIC_LOAD_UMIN:
+ case ISD::ATOMIC_LOAD_UMAX:
+ case ISD::ATOMIC_SWAP: {
unsigned int num_operands = 3;
assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
SDValue Ops[3];
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
}
break;
-
+
case ISD::FORMAL_ARGUMENTS:
case ISD::CALL:
// The only option for this is to custom lower it.
Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
MVT::Flag)) &&
"Lowering call/formal_arguments produced unexpected # results!");
-
+
// Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
// remember that we legalized all of them, so it doesn't get relegalized.
for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
break;
case ISD::INSERT_SUBREG: {
Tmp1 = LegalizeOp(Node->getOperand(0));
- Tmp2 = LegalizeOp(Node->getOperand(1));
+ Tmp2 = LegalizeOp(Node->getOperand(1));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
assert(idx && "Operand must be a constant");
Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
}
- break;
+ break;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
case Expand:
// FIXME: An alternative would be to check to see if the target is not
- // going to custom lower this operation, we could bitcast to half elt
+ // going to custom lower this operation, we could bitcast to half elt
// width and perform two inserts at that width, if that is legal.
Tmp2 = Node->getOperand(1);
break;
}
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-
+
switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");
if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
// SCALAR_TO_VECTOR requires that the type of the value being inserted
// match the element type of the vector being created.
- if (Tmp2.getValueType() ==
+ if (Tmp2.getValueType() ==
Op.getValueType().getVectorElementType()) {
- SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
+ SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
Tmp1.getValueType(), Tmp2);
-
+
unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
MVT ShufMaskVT =
MVT::getIntVectorWithNumElements(NumElts);
MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
-
+
// We generate a shuffle of InVec and ScVec, so the shuffle mask
// should be 0,1,2,3,4,5... with the appropriate element replaced with
// elt 0 of the RHS.
else
ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
}
- SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
- &ShufOps[0], ShufOps.size());
-
- Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
+ SDValue ShufMask = DAG.getBUILD_VECTOR(ShufMaskVT, dl,
+ &ShufOps[0], ShufOps.size());
+
+ Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
Tmp1, ScVec, ShufMask);
Result = LegalizeOp(Result);
break;
}
}
- Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
+ Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
break;
}
}
Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
break;
}
-
+
Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
Result = DAG.UpdateNodeOperands(Result, Tmp1);
switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
- Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
+ Ops.push_back(DAG.getUNDEF(EltVT));
} else {
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
if (Idx < NumElems)
- Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
+ Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
DAG.getConstant(Idx, PtrVT)));
else
- Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
+ Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
DAG.getConstant(Idx - NumElems, PtrVT)));
}
}
- Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
+ Result = DAG.getBUILD_VECTOR(VT, dl, &Ops[0], Ops.size());
break;
}
case TargetLowering::Promote: {
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
// Cast the two input vectors.
- Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
- Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
-
+ Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
+ Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
+
// Convert the shuffle mask to the right # elements.
Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
assert(Tmp3.getNode() && "Shuffle not legal?");
- Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
- Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
+ Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
break;
}
}
break;
-
+
case ISD::EXTRACT_VECTOR_ELT:
Tmp1 = Node->getOperand(0);
Tmp2 = LegalizeOp(Node->getOperand(1));
Result = ExpandEXTRACT_VECTOR_ELT(Result);
break;
- case ISD::EXTRACT_SUBVECTOR:
+ case ISD::EXTRACT_SUBVECTOR:
Tmp1 = Node->getOperand(0);
Tmp2 = LegalizeOp(Node->getOperand(1));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
Result = ExpandEXTRACT_SUBVECTOR(Result);
break;
-
+
case ISD::CONCAT_VECTORS: {
// Use extract/insert/build vector for now. We might try to be
// more clever later.
MVT EltVT = VVT.getVectorElementType();
unsigned NumSubElem = VVT.getVectorNumElements();
for (unsigned j=0; j < NumSubElem; ++j) {
- Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
+ Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
DAG.getConstant(j, PtrVT)));
}
}
- return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
- &Ops[0], Ops.size()));
+ return LegalizeOp(DAG.getBUILD_VECTOR(Node->getValueType(0), dl,
+ &Ops[0], Ops.size()));
}
case ISD::CALLSEQ_START: {
SDNode *CallEnd = FindCallEndFromCallStart(Node);
-
+
// Recursively Legalize all of the inputs of the call end that do not lead
// to this call start. This ensures that any libcalls that need be inserted
// are inserted *before* the CALLSEQ_START.
+ IsLegalizingCallArgs = true;
{SmallPtrSet<SDNode*, 32> NodesLeadingTo;
for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
NodesLeadingTo);
}
+ IsLegalizingCallArgs = false;
// Now that we legalized all of the inputs (which may have inserted
// libcalls) create the new CALLSEQ_START node.
// Merge in the last call, to ensure that this call start after the last
// call ended.
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
- Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
}
-
+
// Do not try to legalize the target-specific arguments (#1+).
if (Tmp1 != Node->getOperand(0)) {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
}
-
+
// Remember that the CALLSEQ_START is legalized.
AddLegalizedOperand(Op.getValue(0), Result);
if (Node->getNumValues() == 2) // If this has a flag result, remember it.
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
-
+
// Now that the callseq_start and all of the non-call nodes above this call
- // sequence have been legalized, legalize the call itself. During this
+ // sequence have been legalized, legalize the call itself. During this
// process, no libcalls can/will be inserted, guaranteeing that no calls
// can overlap.
assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
// Note that we are selecting this call!
LastCALLSEQ_END = SDValue(CallEnd, 0);
IsLegalizingCall = true;
-
+
// Legalize the call, starting from the CALLSEQ_END.
LegalizeOp(LastCALLSEQ_END);
assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
"Legalizing the call start should have legalized this node!");
return I->second;
}
-
- // Otherwise, the call start has been legalized and everything is going
+
+ // Otherwise, the call start has been legalized and everything is going
// according to plan. Just legalize ourselves normally here.
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Do not try to legalize the target-specific arguments (#1+), except for
assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
// This finishes up call legalization.
IsLegalizingCall = false;
-
+
// If the CALLSEQ_END node has a flag, remember that we legalized it.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
if (Node->getNumValues() == 2)
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
SDValue Size = Tmp2.getOperand(1);
- SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
+ SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
Chain = SP.getValue(1);
unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
unsigned StackAlign =
TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
if (Align > StackAlign)
- SP = DAG.getNode(ISD::AND, VT, SP,
+ SP = DAG.getNode(ISD::AND, dl, VT, SP,
DAG.getConstant(-(uint64_t)Align, VT));
- Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
- Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
+ Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
+ Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
- Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
+ Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
DAG.getIntPtrConstant(0, true), SDValue());
Tmp1 = LegalizeOp(Tmp1);
Changed |= Op != Ops.back();
Ops.back() = Op;
}
-
+
if (Changed)
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
-
+
// INLINE asm returns a chain and flag, make sure to add both to the map.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
case ISD::BR:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Ensure that libcalls are emitted before a branch.
- Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-
+
Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
break;
case ISD::BRIND:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Ensure that libcalls are emitted before a branch.
- Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-
+
switch (getTypeAction(Node->getOperand(1).getValueType())) {
default: assert(0 && "Indirect target must be legal type (pointer)!");
case Legal:
case ISD::BR_JT:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Ensure that libcalls are emitted before a branch.
- Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
- switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
+ switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
MVT PTy = TLI.getPointerTy();
MachineFunction &MF = DAG.getMachineFunction();
unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
- Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
- SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
-
- SDValue LD;
- switch (EntrySize) {
- default: assert(0 && "Size of jump table not supported yet."); break;
- case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
- PseudoSourceValue::getJumpTable(), 0); break;
- case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
- PseudoSourceValue::getJumpTable(), 0); break;
- }
+ Index= DAG.getNode(ISD::MUL, dl, PTy,
+ Index, DAG.getConstant(EntrySize, PTy));
+ SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
+ MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
+ SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
+ PseudoSourceValue::getJumpTable(), 0, MemVT);
Addr = LD;
if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
// For PIC, the sequence is:
// BRIND(load(Jumptable + index) + RelocBase)
// RelocBase can be JumpTable, GOT or some sort of global base.
- if (PTy != MVT::i32)
- Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
- Addr = DAG.getNode(ISD::ADD, PTy, Addr,
+ Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
TLI.getPICJumpTableRelocBase(Table, DAG));
}
- Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
+ Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
}
}
break;
case ISD::BRCOND:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Ensure that libcalls are emitted before a return.
- Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
break;
case Promote: {
Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
-
+
// The top bits of the promoted condition are not necessarily zero, ensure
// that the value is properly zero extended.
unsigned BitWidth = Tmp2.getValueSizeInBits();
- if (!DAG.MaskedValueIsZero(Tmp2,
+ if (!DAG.MaskedValueIsZero(Tmp2,
APInt::getHighBitsSet(BitWidth, BitWidth-1)))
- Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
+ Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
break;
}
}
// Basic block destination (Op#2) is always legal.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
-
- switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
+
+ switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
case TargetLowering::Custom:
// Expand brcond's setcc into its constituent parts and create a BR_CC
// Node.
if (Tmp2.getOpcode() == ISD::SETCC) {
- Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
+ Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
+ Tmp1, Tmp2.getOperand(2),
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node->getOperand(2));
} else {
- Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
+ Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
Node->getOperand(2));
case ISD::BR_CC:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Ensure that libcalls are emitted before a branch.
- Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
- Tmp2 = Node->getOperand(2); // LHS
+ Tmp2 = Node->getOperand(2); // LHS
Tmp3 = Node->getOperand(3); // RHS
Tmp4 = Node->getOperand(1); // CC
- LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
+ LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
+ Tmp2, Tmp3, Tmp4, dl);
LastCALLSEQ_END = DAG.getEntryNode();
// If we didn't get both a LHS and RHS back from LegalizeSetCC,
Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
Tmp4 = DAG.getCondCode(ISD::SETNE);
}
-
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
+
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
Node->getOperand(4));
-
+
switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
default: assert(0 && "Unexpected action for BR_CC!");
case TargetLowering::Legal: break;
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
Tmp3 = Result.getValue(0);
Tmp4 = Result.getValue(1);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
// Change base type to a different vector type.
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
- Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
+ Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
- Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
+ Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
Tmp4 = LegalizeOp(Tmp1.getValue(1));
break;
}
}
- // Since loads produce two values, make sure to remember that we
+ // Since loads produce two values, make sure to remember that we
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Tmp3);
AddLegalizedOperand(SDValue(Node, 1), Tmp4);
ISD::LoadExtType NewExtType =
ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
- Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
+ Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
NVT, isVolatile, Alignment);
if (ExtType == ISD::SEXTLOAD)
// Having the top bits zero doesn't help when sign extending.
- Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
+ Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
+ Result.getValueType(),
Result, DAG.getValueType(SrcVT));
else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
// All the top bits are guaranteed to be zero - inform the optimizers.
- Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
+ Result = DAG.getNode(ISD::AssertZext, dl,
+ Result.getValueType(), Result,
DAG.getValueType(SrcVT));
Tmp1 = LegalizeOp(Result);
if (TLI.isLittleEndian()) {
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
// Load the bottom RoundWidth bits.
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
+ Node->getValueType(0), Tmp1, Tmp2,
LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
Alignment);
// Load the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
- Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
+ Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
- Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
+ Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
LD->getSrcValue(), SVOffset + IncrementSize,
ExtraVT, isVolatile,
MinAlign(Alignment, IncrementSize));
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
- Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
+ Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
// Join the hi and lo parts.
- Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
+ Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
} else {
// Big endian - avoid unaligned loads.
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
// Load the top RoundWidth bits.
- Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
+ Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
Alignment);
// Load the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
- Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
+ Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
+ Node->getValueType(0), Tmp1, Tmp2,
LD->getSrcValue(), SVOffset + IncrementSize,
ExtraVT, isVolatile,
MinAlign(Alignment, IncrementSize));
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
- Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
+ Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
// Join the hi and lo parts.
- Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
+ Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
}
Tmp1 = LegalizeOp(Result);
case TargetLowering::Expand:
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
- SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
+ SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
- Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
+ Result = DAG.getNode(ISD::FP_EXTEND, dl,
+ Node->getValueType(0), Load);
Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
Tmp2 = LegalizeOp(Load.getValue(1));
break;
assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
// Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg.
- Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
+ Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(), SrcVT,
LD->isVolatile(), LD->getAlignment());
SDValue ValRes;
if (ExtType == ISD::SEXTLOAD)
- ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
+ ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
+ Result.getValueType(),
Result, DAG.getValueType(SrcVT));
else
- ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
+ ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
break;
case Legal:
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
// 1 -> Hi
- Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
+ Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
DAG.getConstant(OpTy.getSizeInBits()/2,
TLI.getShiftAmountTy()));
- Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
+ Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
} else {
// 0 -> Lo
- Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
+ Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
Node->getOperand(0));
}
break;
} else {
Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
}
-
+
// Since this produces two values, make sure to remember that we legalized
// both of them.
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Ensure that libcalls are emitted before a return.
- Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
LastCALLSEQ_END = DAG.getEntryNode();
-
+
switch (Node->getNumOperands()) {
case 3: // ret val
Tmp2 = Node->getOperand(1);
// Big endian systems want the hi reg first.
if (TLI.isBigEndian())
std::swap(Lo, Hi);
-
+
if (Hi.getNode())
- Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
+ Result = DAG.getNode(ISD::RET, dl, MVT::Other,
+ Tmp1, Lo, Tmp3, Hi,Tmp3);
else
- Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
+ Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
Result = LegalizeOp(Result);
} else {
SDNode *InVal = Tmp2.getNode();
int InIx = Tmp2.getResNo();
unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
MVT EVT = InVal->getValueType(InIx).getVectorElementType();
-
+
// Figure out if there is a simple type corresponding to this Vector
// type. If so, convert to the vector type.
MVT TVT = MVT::getVectorVT(EVT, NumElems);
Tmp2 = ScalarizeVectorOp(Tmp2);
Tmp2 = LegalizeOp(Tmp2);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-
+
// FIXME: Returns of gcc generic vectors smaller than a legal type
// should be returned in integer registers!
-
+
// The scalarized value type may not be legal, e.g. it might require
// promotion or expansion. Relegalize the return.
Result = LegalizeOp(Result);
// type should be returned by reference!
SDValue Lo, Hi;
SplitVectorOp(Tmp2, Lo, Hi);
- Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
+ Result = DAG.getNode(ISD::RET, dl, MVT::Other,
+ Tmp1, Lo, Tmp3, Hi,Tmp3);
Result = LegalizeOp(Result);
}
}
case Promote:
assert(0 && "Can't promote multiple return value yet!");
}
-
+
if (NewValues.size() == Node->getNumOperands())
Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
else
- Result = DAG.getNode(ISD::RET, MVT::Other,
+ Result = DAG.getNode(ISD::RET, dl, MVT::Other,
&NewValues[0], NewValues.size());
break;
}
// together.
// We generally can't do this one for long doubles.
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
- if (CFP->getValueType(0) == MVT::f32 &&
+ if (CFP->getValueType(0) == MVT::f32 &&
getTypeAction(MVT::i32) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32),
MVT::i32);
- Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
break;
} else if (CFP->getValueType(0) == MVT::f64) {
if (getTypeAction(MVT::i64) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
zextOrTrunc(64), MVT::i64);
- Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
break;
} else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
- Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
+ Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
+ Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(4));
- Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
+ Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
isVolatile, MinAlign(Alignment, 4U));
- Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
break;
}
}
}
-
+
switch (getTypeAction(ST->getMemoryVT())) {
case Legal: {
Tmp3 = LegalizeOp(ST->getValue());
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
+ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
MVT VT = Tmp3.getValueType();
break;
case TargetLowering::Promote:
assert(VT.isVector() && "Unknown legal promote case!");
- Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
+ Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
- Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
+ Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
ST->getSrcValue(), SVOffset, isVolatile,
Alignment);
break;
if (!ST->getMemoryVT().isVector()) {
// Truncate the value and store the result.
Tmp3 = PromoteOp(ST->getValue());
- Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, ST->getMemoryVT(),
isVolatile, Alignment);
break;
case Expand: {
unsigned IncrementSize = 0;
SDValue Lo, Hi;
-
+
// If this is a vector type, then we have to calculate the increment as
// the product of the element size in bytes, and the number of elements
// in the high half of the vector.
if (TLI.isTypeLegal(TVT)) {
// Turn this into a normal store of the vector type.
Tmp3 = LegalizeOp(ST->getValue());
- Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
Result = LegalizeOp(Result);
break;
} else if (NumElems == 1) {
// Turn this into a normal store of the scalar type.
Tmp3 = ScalarizeVectorOp(ST->getValue());
- Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
// The scalarized value type may not be legal, e.g. it might require
// promotion or expansion. Relegalize the scalar store.
std::swap(Lo, Hi);
}
- Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
+ Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
if (Hi.getNode() == NULL) {
break;
}
- Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
+ Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
assert(isTypeLegal(Tmp2.getValueType()) &&
"Pointers must be legal!");
SVOffset += IncrementSize;
Alignment = MinAlign(Alignment, IncrementSize);
- Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
+ Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
break;
} // case Expand
}
// Just store the low part. This may become a non-trunc store, so make
// sure to use getTruncStore, not UpdateNodeOperands below.
ExpandOp(ST->getValue(), Tmp3, Tmp4);
- return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, MVT::i8, isVolatile, Alignment);
}
// storing an integral number of bytes. For example, promote
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
- Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
- Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
+ Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, NVT, isVolatile, Alignment);
} else if (StWidth & (StWidth - 1)) {
// If not storing a power-of-2 number of bits, expand as two stores.
if (TLI.isLittleEndian()) {
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
// Store the bottom RoundWidth bits.
- Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, RoundVT,
isVolatile, Alignment);
// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
- Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
+ Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
- Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
+ Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
- Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
+ Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
SVOffset + IncrementSize, ExtraVT, isVolatile,
MinAlign(Alignment, IncrementSize));
} else {
// Big endian - avoid unaligned stores.
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
// Store the top RoundWidth bits.
- Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
+ Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
- Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
- RoundVT, isVolatile, Alignment);
+ Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
+ SVOffset, RoundVT, isVolatile, Alignment);
// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
- Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
+ Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
- Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
+ Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset + IncrementSize, ExtraVT, isVolatile,
MinAlign(Alignment, IncrementSize));
}
// The order of the stores doesn't matter.
- Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
} else {
if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
Tmp2 != ST->getBasePtr())
case Expand:
// TRUNCSTORE:i16 i32 -> STORE i16
assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
- Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
- Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
- isVolatile, Alignment);
+ Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
+ Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
+ SVOffset, isVolatile, Alignment);
break;
}
}
Result = DAG.UpdateNodeOperands(Result, Tmp1);
Tmp1 = Result.getValue(0);
Tmp2 = Result.getValue(1);
-
+
switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
}
break;
case TargetLowering::Expand:
- // Expand to CopyFromReg if the target set
+ // Expand to CopyFromReg if the target set
// StackPointerRegisterToSaveRestore.
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
- Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
+ Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
Node->getValueType(0));
Tmp2 = Tmp1.getValue(1);
} else {
- Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
+ Tmp1 = DAG.getUNDEF(Node->getValueType(0));
Tmp2 = Node->getOperand(0);
}
break;
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
-
+
switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
if (Tmp1.getNode()) Result = Tmp1;
break;
case TargetLowering::Expand:
- // Expand to CopyToReg if the target set
+ // Expand to CopyToReg if the target set
// StackPointerRegisterToSaveRestore.
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
- Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
+ Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
} else {
Result = Tmp1;
}
unsigned BitWidth = Tmp1.getValueSizeInBits();
if (!DAG.MaskedValueIsZero(Tmp1,
APInt::getHighBitsSet(BitWidth, BitWidth-1)))
- Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
+ Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
break;
}
}
Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-
+
switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
}
case TargetLowering::Expand:
if (Tmp1.getOpcode() == ISD::SETCC) {
- Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
+ Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
Tmp2, Tmp3,
cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
} else {
- Result = DAG.getSelectCC(Tmp1,
+ Result = DAG.getSelectCC(dl, Tmp1,
DAG.getConstant(0, Tmp1.getValueType()),
Tmp2, Tmp3, ISD::SETNE);
}
TruncOp = ISD::FP_ROUND;
}
// Promote each of the values to the new type.
- Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
- Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
+ Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
+ Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
// Perform the larger operation, then round down.
- Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
+ Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
if (TruncOp != ISD::FP_ROUND)
- Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
+ Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
else
- Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
+ Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
DAG.getIntPtrConstant(0));
break;
}
Tmp3 = LegalizeOp(Node->getOperand(2)); // True
Tmp4 = LegalizeOp(Node->getOperand(3)); // False
SDValue CC = Node->getOperand(4);
-
- LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
-
+
+ LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
+ Tmp1, Tmp2, CC, dl);
+
// If we didn't get both a LHS and RHS back from LegalizeSetCC,
// the LHS is a legal SETCC itself. In this case, we need to compare
// the result against zero to select between true and false values.
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
Tmp3 = Node->getOperand(2);
- LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
-
- // If we had to Expand the SetCC operands into a SELECT node, then it may
- // not always be possible to return a true LHS & RHS. In this case, just
+ LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
+
+ // If we had to Expand the SetCC operands into a SELECT node, then it may
+ // not always be possible to return a true LHS & RHS. In this case, just
// return the value we legalized, returned in the LHS
if (Tmp2.getNode() == 0) {
Result = Tmp1;
"Fell off of the edge of the integer world");
assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
"Fell off of the edge of the floating point world");
-
+
// If the target supports SETCC of this type, use it.
- if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
+ if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
break;
}
if (NewInTy.isInteger())
assert(0 && "Cannot promote Legal Integer SETCC yet");
else {
- Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
- Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
+ Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
+ Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
}
Tmp1 = LegalizeOp(Tmp1);
Tmp2 = LegalizeOp(Tmp2);
// Expand a setcc node into a select_cc of the same condition, lhs, and
// rhs that selects between const 1 (true) and const 0 (false).
MVT VT = Node->getValueType(0);
- Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
+ Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
Tmp3);
break;
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
SDValue CC = Node->getOperand(2);
-
+
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
// Everything is legal, see if we should expand this op or something.
Tmp1 = TLI.LowerOperation(Result, DAG);
if (Tmp1.getNode()) Result = Tmp1;
break;
+ case TargetLowering::Expand: {
+ // Unroll into a nasty set of scalar code for now.
+ MVT VT = Node->getValueType(0);
+ unsigned NumElems = VT.getVectorNumElements();
+ MVT EltVT = VT.getVectorElementType();
+ MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
+ SmallVector<SDValue, 8> Ops(NumElems);
+ for (unsigned i = 0; i < NumElems; ++i) {
+ SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
+ Tmp1, DAG.getIntPtrConstant(i));
+ Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
+ In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+ TmpEltVT, Tmp2,
+ DAG.getIntPtrConstant(i)),
+ CC);
+ Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
+ APInt::getAllOnesValue(EltVT.getSizeInBits()),
+ EltVT), DAG.getConstant(0, EltVT));
+ }
+ Result = DAG.getBUILD_VECTOR(VT, dl, &Ops[0], NumElems);
+ break;
+ }
}
break;
}
case ISD::SRL_PARTS: {
SmallVector<SDValue, 8> Ops;
bool Changed = false;
- for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
+ unsigned N = Node->getNumOperands();
+ for (unsigned i = 0; i + 1 < N; ++i) {
Ops.push_back(LegalizeOp(Node->getOperand(i)));
Changed |= Ops.back() != Node->getOperand(i);
}
+ Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
+ Changed |= Ops.back() != Node->getOperand(N-1);
if (Changed)
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
case ISD::FDIV:
case ISD::FPOW:
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
- switch (getTypeAction(Node->getOperand(1).getValueType())) {
+ Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
+
+ if ((Node->getOpcode() == ISD::SHL ||
+ Node->getOpcode() == ISD::SRL ||
+ Node->getOpcode() == ISD::SRA) &&
+ !Node->getValueType(0).isVector())
+ Tmp2 = DAG.getShiftAmountOperand(Tmp2);
+
+ switch (getTypeAction(Tmp2.getValueType())) {
case Expand: assert(0 && "Not possible");
case Legal:
- Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
+ Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
break;
case Promote:
- Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
+ Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
break;
}
- if ((Node->getOpcode() == ISD::SHL ||
- Node->getOpcode() == ISD::SRL ||
- Node->getOpcode() == ISD::SRA) &&
- !Node->getValueType(0).isVector()) {
- if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
- Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
- else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
- Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
- }
-
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
// Fall through if the custom lower can't deal with the operation
case TargetLowering::Expand: {
MVT VT = Op.getValueType();
-
+
// See if multiply or divide can be lowered using two-result operations.
SDVTList VTs = DAG.getVTList(VT, VT);
if (Node->getOpcode() == ISD::MUL) {
// and unsigned forms. If the target supports both SMUL_LOHI and
// UMUL_LOHI, form a preference by checking which forms of plain
// MULH it supports.
- bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
- bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
- bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
- bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
+ bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
+ bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
+ bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
+ bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
unsigned OpToUse = 0;
if (HasSMUL_LOHI && !HasMULHS) {
OpToUse = ISD::SMUL_LOHI;
OpToUse = ISD::UMUL_LOHI;
}
if (OpToUse) {
- Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
+ Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
+ 0);
break;
}
}
if (Node->getOpcode() == ISD::MULHS &&
- TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
- Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
+ TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
+ Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
+ VTs, Tmp1, Tmp2).getNode(),
1);
break;
}
- if (Node->getOpcode() == ISD::MULHU &&
- TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
- Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
+ if (Node->getOpcode() == ISD::MULHU &&
+ TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
+ Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
+ VTs, Tmp1, Tmp2).getNode(),
1);
break;
}
if (Node->getOpcode() == ISD::SDIV &&
- TLI.isOperationLegal(ISD::SDIVREM, VT)) {
- Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
+ TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
+ Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
+ VTs, Tmp1, Tmp2).getNode(),
0);
break;
}
if (Node->getOpcode() == ISD::UDIV &&
- TLI.isOperationLegal(ISD::UDIVREM, VT)) {
- Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
+ TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
+ Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
+ VTs, Tmp1, Tmp2).getNode(),
0);
break;
}
-
+
// Check to see if we have a libcall for this operator.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
bool isSigned = false;
case ISD::MUL:
if (VT == MVT::i32)
LC = RTLIB::MUL_I32;
+ else if (VT == MVT::i64)
+ LC = RTLIB::MUL_I64;
break;
case ISD::FPOW:
LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
RTLIB::POW_PPCF128);
break;
+ case ISD::FDIV:
+ LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
+ RTLIB::DIV_PPCF128);
+ break;
default: break;
}
if (LC != RTLIB::UNKNOWN_LIBCALL) {
Result = ExpandLibCall(LC, Node, isSigned, Dummy);
break;
}
-
+
assert(Node->getValueType(0).isVector() &&
"Cannot expand this binary operator!");
// Expand the operation into a bunch of nasty scalar code.
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
assert(OVT.isVector() && "Cannot promote this BinOp!");
// Bit convert each of the values to the new type.
- Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
- Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
+ Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
+ Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
// Bit convert the result back the original type.
- Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
break;
}
}
}
}
break;
-
+
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI:
case ISD::SDIVREM:
Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
break;
}
-
+
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
-
+
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
default: assert(0 && "Operation not supported");
case TargetLowering::Custom:
// Get the sign bit of the RHS.
MVT IVT =
Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
- SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
- SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
+ SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
+ SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
// Get the absolute value of the result.
- SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
+ SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
// Select between the nabs and abs value based on the sign bit of
// the input.
- Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
- DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
+ Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
+ DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
AbsVal),
AbsVal);
Result = LegalizeOp(Result);
break;
}
-
+
// Otherwise, do bitwise ops!
MVT NVT =
Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
- Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
Result = LegalizeOp(Result);
break;
}
}
break;
-
+
case ISD::ADDC:
case ISD::SUBC:
Tmp1 = LegalizeOp(Node->getOperand(0));
Tmp2 = LegalizeOp(Node->getOperand(1));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+ Tmp3 = Result.getValue(0);
+ Tmp4 = Result.getValue(1);
+
+ switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+ default: assert(0 && "This action is not supported yet!");
+ case TargetLowering::Legal:
+ break;
+ case TargetLowering::Custom:
+ Tmp1 = TLI.LowerOperation(Tmp3, DAG);
+ if (Tmp1.getNode() != NULL) {
+ Tmp3 = LegalizeOp(Tmp1);
+ Tmp4 = LegalizeOp(Tmp1.getValue(1));
+ }
+ break;
+ }
// Since this produces two values, make sure to remember that we legalized
// both of them.
- AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
- return Result;
+ AddLegalizedOperand(SDValue(Node, 0), Tmp3);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp4);
+ return Op.getResNo() ? Tmp4 : Tmp3;
case ISD::ADDE:
case ISD::SUBE:
Tmp2 = LegalizeOp(Node->getOperand(1));
Tmp3 = LegalizeOp(Node->getOperand(2));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+ Tmp3 = Result.getValue(0);
+ Tmp4 = Result.getValue(1);
+
+ switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+ default: assert(0 && "This action is not supported yet!");
+ case TargetLowering::Legal:
+ break;
+ case TargetLowering::Custom:
+ Tmp1 = TLI.LowerOperation(Tmp3, DAG);
+ if (Tmp1.getNode() != NULL) {
+ Tmp3 = LegalizeOp(Tmp1);
+ Tmp4 = LegalizeOp(Tmp1.getValue(1));
+ }
+ break;
+ }
// Since this produces two values, make sure to remember that we legalized
// both of them.
- AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
- AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
- return Result;
-
+ AddLegalizedOperand(SDValue(Node, 0), Tmp3);
+ AddLegalizedOperand(SDValue(Node, 1), Tmp4);
+ return Op.getResNo() ? Tmp4 : Tmp3;
+
case ISD::BUILD_PAIR: {
MVT PairTy = Node->getValueType(0);
// TODO: handle the case where the Lo and Hi operands are not of legal type
assert(0 && "Cannot promote/custom this yet!");
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
- Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
+ Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
break;
case TargetLowering::Expand:
- Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
- Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
- Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
+ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
+ Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
+ Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
DAG.getConstant(PairTy.getSizeInBits()/2,
TLI.getShiftAmountTy()));
- Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
+ Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
break;
}
break;
unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
bool isSigned = DivOpc == ISD::SDIV;
MVT VT = Node->getValueType(0);
-
+
// See if remainder can be lowered using two-result operations.
SDVTList VTs = DAG.getVTList(VT, VT);
if (Node->getOpcode() == ISD::SREM &&
- TLI.isOperationLegal(ISD::SDIVREM, VT)) {
- Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
+ TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
+ Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
+ VTs, Tmp1, Tmp2).getNode(), 1);
break;
}
if (Node->getOpcode() == ISD::UREM &&
- TLI.isOperationLegal(ISD::UDIVREM, VT)) {
- Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
+ TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
+ Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
+ VTs, Tmp1, Tmp2).getNode(), 1);
break;
}
if (TLI.getOperationAction(DivOpc, VT) ==
TargetLowering::Legal) {
// X % Y -> X-X/Y*Y
- Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
- Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
- Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
+ Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
+ Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
+ Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
} else if (VT.isVector()) {
Result = LegalizeOp(UnrollVectorOp(Op));
} else {
break;
case TargetLowering::Expand: {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
+ SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
- Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
- DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()),
- TLI.getPointerTy()));
+ Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
+ DAG.getConstant(TLI.getTargetData()->
+ getTypePaddedSize(VT.getTypeForMVT()),
+ TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
- Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
+ Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
// Load the actual argument out of the pointer VAList
- Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
+ Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
Tmp1 = LegalizeOp(Result.getValue(1));
Result = LegalizeOp(Result);
break;
}
}
- // Since VAARG produces two values, make sure to remember that we
+ // Since VAARG produces two values, make sure to remember that we
// legalized both of them.
AddLegalizedOperand(SDValue(Node, 0), Result);
AddLegalizedOperand(SDValue(Node, 1), Tmp1);
return Op.getResNo() ? Tmp1 : Result;
}
-
- case ISD::VACOPY:
+
+ case ISD::VACOPY:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
// output, returning the chain.
const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
- Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
- Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
+ Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
+ Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
break;
}
break;
- case ISD::VAEND:
+ case ISD::VAEND:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
break;
}
break;
-
- case ISD::VASTART:
+
+ case ISD::VASTART:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
-
+
switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal: break;
break;
}
break;
-
+
case ISD::ROTL:
case ISD::ROTR:
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
- Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
+ Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
default:
break;
}
break;
-
+
case ISD::BSWAP:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
- Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
- Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
- Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
+ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
+ Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
+ Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
break;
}
case TargetLowering::Expand:
- Result = ExpandBSWAP(Tmp1);
+ Result = ExpandBSWAP(Tmp1, dl);
break;
}
break;
-
+
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
// Zero extend the argument.
- Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
+ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
// Perform the larger operation, then subtract if needed.
- Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
+ Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
switch (Node->getOpcode()) {
case ISD::CTPOP:
Result = Tmp1;
break;
case ISD::CTTZ:
//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
- Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
- DAG.getConstant(NVT.getSizeInBits(), NVT),
+ Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
+ Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
ISD::SETEQ);
- Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
+ Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
break;
case ISD::CTLZ:
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
- Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
+ Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
DAG.getConstant(NVT.getSizeInBits() -
OVT.getSizeInBits(), NVT));
break;
break;
}
case TargetLowering::Expand:
- Result = ExpandBitCount(Node->getOpcode(), Tmp1);
+ Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
break;
}
break;
case ISD::FNEG:
// Expand Y = FNEG(X) -> Y = SUB -0.0, X
Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
- Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
+ Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
break;
case ISD::FABS: {
// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
MVT VT = Node->getValueType(0);
Tmp2 = DAG.getConstantFP(0.0, VT);
- Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
- ISD::SETUGT);
- Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
- Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
+ Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
+ Tmp1, Tmp2, ISD::SETUGT);
+ Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
+ Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
break;
}
case ISD::FSQRT:
case ISD::FSIN:
- case ISD::FCOS:
+ case ISD::FCOS:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::BIT_CONVERT:
if (!isTypeLegal(Node->getOperand(0).getValueType())) {
Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
- Node->getValueType(0));
+ Node->getValueType(0), dl);
} else if (Op.getOperand(0).getValueType().isVector()) {
// The input has to be a vector type, we have to either scalarize it, pack
// it, or convert it based on whether the input vector type is legal.
int InIx = Node->getOperand(0).getResNo();
unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
MVT EVT = InVal->getValueType(InIx).getVectorElementType();
-
+
// Figure out if there is a simple type corresponding to this Vector
// type. If so, convert to the vector type.
MVT TVT = MVT::getVectorVT(EVT, NumElems);
if (TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the vector input.
- Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
LegalizeOp(Node->getOperand(0)));
break;
} else if (NumElems == 1) {
// Turn this into a bit convert of the scalar input.
- Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
ScalarizeVectorOp(Node->getOperand(0)));
break;
} else {
default: assert(0 && "Unknown operation action!");
case TargetLowering::Expand:
Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
- Node->getValueType(0));
+ Node->getValueType(0), dl);
break;
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node->getOperand(0));
default: assert(0 && "Unknown cvt code!");
case ISD::CVT_SF:
case ISD::CVT_UF:
- break;
case ISD::CVT_FF:
+ break;
case ISD::CVT_FS:
case ISD::CVT_FU:
case ISD::CVT_SS:
case Promote:
Result = PromoteOp(Node->getOperand(0));
// For FP, make Op1 a i32
-
- Result = DAG.getConvertRndSat(Result.getValueType(), Result,
+
+ Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
DTyOp, STyOp, RndOp, SatOp, CvtCode);
break;
}
case ISD::UINT_TO_FP: {
bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
Result = LegalizeINT_TO_FP(Result, isSigned,
- Node->getValueType(0), Node->getOperand(0));
+ Node->getValueType(0), Node->getOperand(0), dl);
break;
}
case ISD::TRUNCATE:
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Legal:
Tmp1 = LegalizeOp(Node->getOperand(0));
- Result = DAG.UpdateNodeOperands(Result, Tmp1);
+ switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+ default: assert(0 && "Unknown TRUNCATE legalization operation action!");
+ case TargetLowering::Custom:
+ isCustom = true;
+ // FALLTHROUGH
+ case TargetLowering::Legal:
+ Result = DAG.UpdateNodeOperands(Result, Tmp1);
+ if (isCustom) {
+ Tmp1 = TLI.LowerOperation(Result, DAG);
+ if (Tmp1.getNode()) Result = Tmp1;
+ }
+ break;
+ case TargetLowering::Expand:
+ assert(Result.getValueType().isVector() && "must be vector type");
+ // Unroll the truncate. We should do better.
+ Result = LegalizeOp(UnrollVectorOp(Result));
+ }
break;
case Expand:
ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
// Since the result is legal, we should just be able to truncate the low
// part of the source.
- Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
+ Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
break;
case Promote:
Result = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
+ Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
break;
}
break;
break;
case TargetLowering::Promote:
Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
- Node->getOpcode() == ISD::FP_TO_SINT);
+ Node->getOpcode() == ISD::FP_TO_SINT,
+ dl);
break;
case TargetLowering::Expand:
if (Node->getOpcode() == ISD::FP_TO_UINT) {
APInt x = APInt::getSignBit(NVT.getSizeInBits());
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
Tmp2 = DAG.getConstantFP(apf, VT);
- Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
- Node->getOperand(0), Tmp2, ISD::SETLT);
- True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
- False = DAG.getNode(ISD::FP_TO_SINT, NVT,
- DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
- Tmp2));
- False = DAG.getNode(ISD::XOR, NVT, False,
+ Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
+ Node->getOperand(0),
+ Tmp2, ISD::SETLT);
+ True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
+ False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
+ DAG.getNode(ISD::FSUB, dl, VT,
+ Node->getOperand(0), Tmp2));
+ False = DAG.getNode(ISD::XOR, dl, NVT, False,
DAG.getConstant(x, NVT));
- Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
+ Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
break;
} else {
assert(0 && "Do not know how to expand FP_TO_SINT yet!");
// Convert ppcf128 to i32
if (OVT == MVT::ppcf128 && VT == MVT::i32) {
if (Node->getOpcode() == ISD::FP_TO_SINT) {
- Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
Node->getOperand(0), DAG.getValueType(MVT::f64));
- Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
+ Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
DAG.getIntPtrConstant(1));
- Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
+ Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
} else {
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
APFloat apf = APFloat(APInt(128, 2, TwoE31));
Tmp2 = DAG.getConstantFP(apf, OVT);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks.
- Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
- DAG.getNode(ISD::ADD, MVT::i32,
- DAG.getNode(ISD::FP_TO_SINT, VT,
- DAG.getNode(ISD::FSUB, OVT,
+ Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
+ Tmp2,
+ DAG.getNode(ISD::ADD, dl, MVT::i32,
+ DAG.getNode(ISD::FP_TO_SINT, dl, VT,
+ DAG.getNode(ISD::FSUB, dl, OVT,
Node->getOperand(0), Tmp2)),
DAG.getConstant(0x80000000, MVT::i32)),
- DAG.getNode(ISD::FP_TO_SINT, VT,
+ DAG.getNode(ISD::FP_TO_SINT, dl, VT,
Node->getOperand(0)),
DAG.getCondCode(ISD::SETGE));
}
if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
// The only other way we can lower this is to turn it into a STORE,
// LOAD pair, targetting a temporary location (a stack slot).
- Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
+ Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
break;
}
switch (getTypeAction(Node->getOperand(0).getValueType())) {
break;
case Promote:
Tmp1 = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
+ Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
break;
}
break;
ExpandOp(Node->getOperand(0), Lo, Result);
// Round it the rest of the way (e.g. to f32) if needed.
if (DstVT!=MVT::f64)
- Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
+ Result = DAG.getNode(ISD::FP_ROUND, dl,
+ DstVT, Result, Op.getOperand(1));
break;
}
// The only other way we can lower this is to turn it into a STORE,
// LOAD pair, targetting a temporary location (a stack slot).
- Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
+ Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
break;
}
switch (getTypeAction(Node->getOperand(0).getValueType())) {
break;
case Promote:
Tmp1 = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
+ Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
Node->getOperand(1));
break;
}
switch (Node->getOpcode()) {
case ISD::ANY_EXTEND:
Tmp1 = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
+ Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
break;
case ISD::ZERO_EXTEND:
Result = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
- Result = DAG.getZeroExtendInReg(Result,
+ Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
+ Result = DAG.getZeroExtendInReg(Result, dl,
Node->getOperand(0).getValueType());
break;
case ISD::SIGN_EXTEND:
Result = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
- Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
+ Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
+ Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
Result,
DAG.getValueType(Node->getOperand(0).getValueType()));
break;
unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
ExtraVT.getSizeInBits();
SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
- Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
+ Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
Node->getOperand(0), ShiftCst);
- Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
+ Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
Result, ShiftCst);
} else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
// The only way we can lower this is to turn it into a TRUNCSTORE,
// NOTE: there is a choice here between constantly creating new stack
// slots and always reusing the same one. We currently always create
// new ones, as reuse may inhibit scheduling.
- Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
- Node->getValueType(0));
+ Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
+ Node->getValueType(0), dl);
} else {
assert(0 && "Unknown op");
}
TLI.LowerCallTo(Tmp1, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
DAG.getExternalSymbol("abort", TLI.getPointerTy()),
- Args, DAG);
+ Args, DAG, dl);
Result = CallResult.second;
break;
}
break;
}
- case ISD::SADDO: {
+ case ISD::SADDO:
+ case ISD::SSUBO: {
MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action not supported for this op yet!");
SDValue LHS = LegalizeOp(Node->getOperand(0));
SDValue RHS = LegalizeOp(Node->getOperand(1));
- SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
- MVT SType = Node->getValueType(0);
+ SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
+ ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
+ LHS, RHS);
MVT OType = Node->getValueType(1);
- SDValue Zero = DAG.getConstant(0, OType);
-
- SDValue LHSPos = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
- SDValue RHSPos = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
- SDValue And1 = DAG.getNode(ISD::AND, OType, LHSPos, RHSPos);
+ SDValue Zero = DAG.getConstant(0, LHS.getValueType());
- And1 = DAG.getNode(ISD::AND, OType, And1,
- DAG.getSetCC(OType, Sum, Zero, ISD::SETLT));
+ // LHSSign -> LHS >= 0
+ // RHSSign -> RHS >= 0
+ // SumSign -> Sum >= 0
+ //
+ // Add:
+ // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
+ // Sub:
+ // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
+ //
+ SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
+ SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
+ SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
+ Node->getOpcode() == ISD::SADDO ?
+ ISD::SETEQ : ISD::SETNE);
- SDValue LHSNeg = DAG.getSetCC(OType, LHS, Zero, ISD::SETLT);
- SDValue RHSNeg = DAG.getSetCC(OType, RHS, Zero, ISD::SETLT);
- SDValue And2 = DAG.getNode(ISD::AND, OType, LHSNeg, RHSNeg);
+ SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
+ SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
- And2 = DAG.getNode(ISD::AND, OType, And2,
- DAG.getSetCC(OType, Sum, Zero, ISD::SETGE));
-
- SDValue Cmp = DAG.getNode(ISD::OR, OType, And1, And2);
+ SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
MVT ValueVTs[] = { LHS.getValueType(), OType };
SDValue Ops[] = { Sum, Cmp };
- Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
+ Result = DAG.getNode(ISD::MERGE_VALUES, dl,
+ DAG.getVTList(&ValueVTs[0], 2),
+ &Ops[0], 2);
SDNode *RNode = Result.getNode();
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
break;
}
- case ISD::UADDO: {
+ case ISD::UADDO:
+ case ISD::USUBO: {
MVT VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action not supported for this op yet!");
SDValue LHS = LegalizeOp(Node->getOperand(0));
SDValue RHS = LegalizeOp(Node->getOperand(1));
- SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
+ SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
+ ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
+ LHS, RHS);
MVT OType = Node->getValueType(1);
- SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, ISD::SETULT);
+ SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
+ Node->getOpcode () == ISD::UADDO ?
+ ISD::SETULT : ISD::SETUGT);
MVT ValueVTs[] = { LHS.getValueType(), OType };
SDValue Ops[] = { Sum, Cmp };
- Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
+ Result = DAG.getNode(ISD::MERGE_VALUES, dl,
+ DAG.getVTList(&ValueVTs[0], 2),
+ &Ops[0], 2);
SDNode *RNode = Result.getNode();
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
break;
}
+ case ISD::SMULO:
+ case ISD::UMULO: {
+ MVT VT = Node->getValueType(0);
+ switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
+ default: assert(0 && "This action is not supported at all!");
+ case TargetLowering::Custom:
+ Result = TLI.LowerOperation(Op, DAG);
+ if (Result.getNode()) break;
+ // Fall Thru
+ case TargetLowering::Legal:
+ // FIXME: According to Hacker's Delight, this can be implemented in
+ // target independent lowering, but it would be inefficient, since it
+ // requires a division + a branch.
+ assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
+ break;
+ }
+ break;
}
-
+
+ }
+
assert(Result.getValueType() == Op.getValueType() &&
"Bad legalization!");
-
+
// Make sure that the generated code is itself legal.
if (Result != Op)
Result = LegalizeOp(Result);
SDValue Tmp1, Tmp2, Tmp3;
SDValue Result;
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
if (I != PromotedNodes.end()) return I->second;
assert(0 && "Do not know how to promote this operator!");
abort();
case ISD::UNDEF:
- Result = DAG.getNode(ISD::UNDEF, NVT);
+ Result = DAG.getUNDEF(NVT);
break;
case ISD::Constant:
if (VT != MVT::i1)
- Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
+ Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
else
- Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
+ Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
break;
case ISD::ConstantFP:
- Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
+ Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
break;
- case ISD::SETCC:
- assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
+ case ISD::SETCC: {
+ MVT VT0 = Node->getOperand(0).getValueType();
+ assert(isTypeLegal(TLI.getSetCCResultType(VT0))
&& "SetCC type is not legal??");
- Result = DAG.getNode(ISD::SETCC,
- TLI.getSetCCResultType(Node->getOperand(0)),
+ Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
Node->getOperand(0), Node->getOperand(1),
Node->getOperand(2));
break;
-
+ }
case ISD::TRUNCATE:
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Legal:
assert(Result.getValueType().bitsGE(NVT) &&
"This truncation doesn't make sense!");
if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
- Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
+ Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
break;
case Promote:
// The truncation is not required, because we don't guarantee anything
case Expand:
ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
// Truncate the low part of the expanded value to the result type
- Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
+ Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
}
break;
case ISD::SIGN_EXTEND:
case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
case Legal:
// Input is legal? Just do extend all the way to the larger type.
- Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
break;
case Promote:
// Promote the reg if it's smaller.
Result = PromoteOp(Node->getOperand(0));
// The high bits are not guaranteed to be anything. Insert an extend.
if (Node->getOpcode() == ISD::SIGN_EXTEND)
- Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
DAG.getValueType(Node->getOperand(0).getValueType()));
else if (Node->getOpcode() == ISD::ZERO_EXTEND)
- Result = DAG.getZeroExtendInReg(Result,
+ Result = DAG.getZeroExtendInReg(Result, dl,
Node->getOperand(0).getValueType());
break;
}
CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
"can only promote integers");
- Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
+ Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
Node->getOperand(1), Node->getOperand(2),
Node->getOperand(3), Node->getOperand(4),
CvtCode);
}
case ISD::BIT_CONVERT:
Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
- Node->getValueType(0));
+ Node->getValueType(0), dl);
Result = PromoteOp(Result);
break;
-
+
case ISD::FP_EXTEND:
assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
case ISD::FP_ROUND:
case Legal:
if (Node->getConstantOperandVal(1) == 0) {
// Input is legal? Do an FP_ROUND_INREG.
- Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
DAG.getValueType(VT));
} else {
// Just remove the truncate, it isn't affecting the value.
- Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
+ Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
Node->getOperand(1));
}
break;
switch (getTypeAction(Node->getOperand(0).getValueType())) {
case Legal:
// No extra round required here.
- Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
break;
case Promote:
Result = PromoteOp(Node->getOperand(0));
if (Node->getOpcode() == ISD::SINT_TO_FP)
- Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
+ Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
Result,
DAG.getValueType(Node->getOperand(0).getValueType()));
else
- Result = DAG.getZeroExtendInReg(Result,
+ Result = DAG.getZeroExtendInReg(Result, dl,
Node->getOperand(0).getValueType());
// No extra round required here.
- Result = DAG.getNode(Node->getOpcode(), NVT, Result);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
break;
case Expand:
Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
- Node->getOperand(0));
+ Node->getOperand(0), dl);
// Round if we cannot tolerate excess precision.
if (NoExcessFPPrecision)
- Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
DAG.getValueType(VT));
break;
}
case ISD::SIGN_EXTEND_INREG:
Result = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
Node->getOperand(1));
break;
case ISD::FP_TO_SINT:
// we can use that instead. This allows us to generate better code for
// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
// legal, such as PowerPC.
- if (Node->getOpcode() == ISD::FP_TO_UINT &&
- !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
- (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
+ if (Node->getOpcode() == ISD::FP_TO_UINT &&
+ !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
+ (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
- Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
+ Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
} else {
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
}
break;
case ISD::FNEG:
Tmp1 = PromoteOp(Node->getOperand(0));
assert(Tmp1.getValueType() == NVT);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
// NOTE: we do not have to do any extra rounding here for
// NoExcessFPPrecision, because we know the input will have the appropriate
// precision, and these operations don't modify precision at all.
case ISD::FNEARBYINT:
Tmp1 = PromoteOp(Node->getOperand(0));
assert(Tmp1.getValueType() == NVT);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
if (NoExcessFPPrecision)
- Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
DAG.getValueType(VT));
break;
if (Node->getOpcode() == ISD::FPOW)
Tmp2 = PromoteOp(Tmp2);
assert(Tmp1.getValueType() == NVT);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
if (NoExcessFPPrecision)
- Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
DAG.getValueType(VT));
break;
}
-
- case ISD::ATOMIC_CMP_SWAP_8:
- case ISD::ATOMIC_CMP_SWAP_16:
- case ISD::ATOMIC_CMP_SWAP_32:
- case ISD::ATOMIC_CMP_SWAP_64: {
+
+ case ISD::ATOMIC_CMP_SWAP: {
AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
Tmp2 = PromoteOp(Node->getOperand(2));
Tmp3 = PromoteOp(Node->getOperand(3));
- Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
+ Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
+ AtomNode->getChain(),
AtomNode->getBasePtr(), Tmp2, Tmp3,
AtomNode->getSrcValue(),
AtomNode->getAlignment());
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
break;
}
- case ISD::ATOMIC_LOAD_ADD_8:
- case ISD::ATOMIC_LOAD_SUB_8:
- case ISD::ATOMIC_LOAD_AND_8:
- case ISD::ATOMIC_LOAD_OR_8:
- case ISD::ATOMIC_LOAD_XOR_8:
- case ISD::ATOMIC_LOAD_NAND_8:
- case ISD::ATOMIC_LOAD_MIN_8:
- case ISD::ATOMIC_LOAD_MAX_8:
- case ISD::ATOMIC_LOAD_UMIN_8:
- case ISD::ATOMIC_LOAD_UMAX_8:
- case ISD::ATOMIC_SWAP_8:
- case ISD::ATOMIC_LOAD_ADD_16:
- case ISD::ATOMIC_LOAD_SUB_16:
- case ISD::ATOMIC_LOAD_AND_16:
- case ISD::ATOMIC_LOAD_OR_16:
- case ISD::ATOMIC_LOAD_XOR_16:
- case ISD::ATOMIC_LOAD_NAND_16:
- case ISD::ATOMIC_LOAD_MIN_16:
- case ISD::ATOMIC_LOAD_MAX_16:
- case ISD::ATOMIC_LOAD_UMIN_16:
- case ISD::ATOMIC_LOAD_UMAX_16:
- case ISD::ATOMIC_SWAP_16:
- case ISD::ATOMIC_LOAD_ADD_32:
- case ISD::ATOMIC_LOAD_SUB_32:
- case ISD::ATOMIC_LOAD_AND_32:
- case ISD::ATOMIC_LOAD_OR_32:
- case ISD::ATOMIC_LOAD_XOR_32:
- case ISD::ATOMIC_LOAD_NAND_32:
- case ISD::ATOMIC_LOAD_MIN_32:
- case ISD::ATOMIC_LOAD_MAX_32:
- case ISD::ATOMIC_LOAD_UMIN_32:
- case ISD::ATOMIC_LOAD_UMAX_32:
- case ISD::ATOMIC_SWAP_32:
- case ISD::ATOMIC_LOAD_ADD_64:
- case ISD::ATOMIC_LOAD_SUB_64:
- case ISD::ATOMIC_LOAD_AND_64:
- case ISD::ATOMIC_LOAD_OR_64:
- case ISD::ATOMIC_LOAD_XOR_64:
- case ISD::ATOMIC_LOAD_NAND_64:
- case ISD::ATOMIC_LOAD_MIN_64:
- case ISD::ATOMIC_LOAD_MAX_64:
- case ISD::ATOMIC_LOAD_UMIN_64:
- case ISD::ATOMIC_LOAD_UMAX_64:
- case ISD::ATOMIC_SWAP_64: {
+ case ISD::ATOMIC_LOAD_ADD:
+ case ISD::ATOMIC_LOAD_SUB:
+ case ISD::ATOMIC_LOAD_AND:
+ case ISD::ATOMIC_LOAD_OR:
+ case ISD::ATOMIC_LOAD_XOR:
+ case ISD::ATOMIC_LOAD_NAND:
+ case ISD::ATOMIC_LOAD_MIN:
+ case ISD::ATOMIC_LOAD_MAX:
+ case ISD::ATOMIC_LOAD_UMIN:
+ case ISD::ATOMIC_LOAD_UMAX:
+ case ISD::ATOMIC_SWAP: {
AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
Tmp2 = PromoteOp(Node->getOperand(2));
- Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
+ Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
+ AtomNode->getChain(),
AtomNode->getBasePtr(), Tmp2,
AtomNode->getSrcValue(),
AtomNode->getAlignment());
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
break;
case ISD::FADD:
case ISD::FSUB:
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
-
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
+
// Floating point operations will give excess precision that we may not be
// able to tolerate. If we DO allow excess precision, just leave it,
// otherwise excise it.
// FIXME: Why would we need to round FP ops more than integer ones?
// Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
if (NoExcessFPPrecision)
- Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
DAG.getValueType(VT));
break;
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
if (NVT.isInteger()) {
- Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
+ Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
DAG.getValueType(VT));
- Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
+ Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
DAG.getValueType(VT));
}
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
// Perform FP_ROUND: this is probably overly pessimistic.
if (NVT.isFloatingPoint() && NoExcessFPPrecision)
- Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
DAG.getValueType(VT));
break;
case ISD::FDIV:
case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
}
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
-
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
+
// Perform FP_ROUND: this is probably overly pessimistic.
if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
- Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
+ Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
DAG.getValueType(VT));
break;
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
assert(NVT.isInteger() && "Operators don't apply to FP!");
- Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
- Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
- Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
+ Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
+ Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
+ Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
break;
case ISD::SHL:
Tmp1 = PromoteOp(Node->getOperand(0));
- Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
+ Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
break;
case ISD::SRA:
// The input value must be properly sign extended.
Tmp1 = PromoteOp(Node->getOperand(0));
- Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
+ Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
DAG.getValueType(VT));
- Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
+ Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
break;
case ISD::SRL:
// The input value must be properly zero extended.
Tmp1 = PromoteOp(Node->getOperand(0));
- Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
- Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
+ Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
+ Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
break;
case ISD::VAARG:
Tmp1 = Node->getOperand(0); // Get the chain.
Tmp2 = Node->getOperand(1); // Get the pointer.
if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
- Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
+ Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
Result = TLI.LowerOperation(Tmp3, DAG);
} else {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
+ SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
- Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
+ Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(VT.getSizeInBits()/8,
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
- Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
+ Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
// Load the actual argument out of the pointer VAList
- Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
+ Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
}
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
LoadSDNode *LD = cast<LoadSDNode>(Node);
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
? ISD::EXTLOAD : LD->getExtensionType();
- Result = DAG.getExtLoad(ExtType, NVT,
+ Result = DAG.getExtLoad(ExtType, dl, NVT,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
LD->getMemoryVT(),
// Ensure that the resulting node is at least the same size as the operands'
// value types, because we cannot assume that TLI.getSetCCValueType() is
// constant.
- Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
+ Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
break;
}
case ISD::SELECT_CC:
Tmp2 = PromoteOp(Node->getOperand(2)); // True
Tmp3 = PromoteOp(Node->getOperand(3)); // False
- Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
+ Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
break;
case ISD::BSWAP:
Tmp1 = Node->getOperand(0);
- Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
- Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
- Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
+ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
+ Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
+ Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
DAG.getConstant(NVT.getSizeInBits() -
VT.getSizeInBits(),
TLI.getShiftAmountTy()));
case ISD::CTTZ:
case ISD::CTLZ:
// Zero extend the argument
- Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
+ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
// Perform the larger operation, then subtract if needed.
- Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
+ Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
switch(Node->getOpcode()) {
case ISD::CTPOP:
Result = Tmp1;
break;
case ISD::CTTZ:
// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
- Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
+ Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
DAG.getConstant(NVT.getSizeInBits(), NVT),
ISD::SETEQ);
- Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
+ Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
break;
case ISD::CTLZ:
//Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
- Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
+ Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
DAG.getConstant(NVT.getSizeInBits() -
VT.getSizeInBits(), NVT));
break;
// Make sure the result is itself legal.
Result = LegalizeOp(Result);
-
+
// Remember that we promoted this!
AddPromotedOperand(Op, Result);
return Result;
// lower to a store then an indexed load.
SDValue Vec = Op.getOperand(0);
SDValue Idx = Op.getOperand(1);
-
+ DebugLoc dl = Op.getDebugLoc();
+
MVT TVT = Vec.getValueType();
unsigned NumElems = TVT.getVectorNumElements();
-
+
switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Custom: {
Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
Idx.getValueType());
}
-
+
// It's now an extract from the appropriate high or low part. Recurse.
Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
Op = ExpandEXTRACT_VECTOR_ELT(Op);
// Store the value to a temporary stack slot, then LOAD the scalar
// element back out.
SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
- SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
// Add the offset to the index.
unsigned EltSize = Op.getValueType().getSizeInBits()/8;
- Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
+ Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
DAG.getConstant(EltSize, Idx.getValueType()));
if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
- Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
+ Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
else
- Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
+ Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
- StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
+ StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
- Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
+ Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
}
return Op;
}
// is a constant and that the extracted result is a supported hardware type.
SDValue Vec = Op.getOperand(0);
SDValue Idx = LegalizeOp(Op.getOperand(1));
-
+
unsigned NumElems = Vec.getValueType().getVectorNumElements();
-
+
if (NumElems == Op.getValueType().getVectorNumElements()) {
// This must be an access of the desired vector length. Return it.
return Vec;
Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
Idx.getValueType());
}
-
+
// It's now an extract from the appropriate high or low part. Recurse.
Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
return ExpandEXTRACT_SUBVECTOR(Op);
/// LHS, and the SDValue returned in RHS has a nil SDNode value.
void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
SDValue &RHS,
- SDValue &CC) {
- SDValue Tmp1, Tmp2, Tmp3, Result;
-
+ SDValue &CC,
+ DebugLoc dl) {
+ SDValue Tmp1, Tmp2, Tmp3, Result;
+
switch (getTypeAction(LHS.getValueType())) {
case Legal:
Tmp1 = LegalizeOp(LHS); // LHS
// ALL of these operations will work if we either sign or zero extend
// the operands (including the unsigned comparisons!). Zero extend is
// usually a simpler/cheaper operation, so prefer it.
- Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
- Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
+ Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
+ Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
break;
case ISD::SETGE:
case ISD::SETGT:
case ISD::SETLT:
case ISD::SETLE:
- Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
+ Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
DAG.getValueType(VT));
- Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
+ Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
DAG.getValueType(VT));
Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
SDValue Dummy;
SDValue Ops[2] = { LHS, RHS };
- Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
+ Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
- Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
- CC);
- LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
+ Tmp1 = DAG.getNode(ISD::SETCC, dl,
+ TLI.getSetCCResultType(Tmp1.getValueType()),
+ Tmp1, Tmp2, CC);
+ LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
false /*sign irrelevant*/, Dummy);
- Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
- DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
- Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
+ Tmp2 = DAG.getNode(ISD::SETCC, dl,
+ TLI.getSetCCResultType(LHS.getValueType()), LHS,
+ Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
+ Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp2 = SDValue();
}
LHS = LegalizeOp(Tmp1);
// BNE crN, L:
// FCMPU crN, lo1, lo2
// The following can be improved, but not that much.
- Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
- ISD::SETOEQ);
- Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
- Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
- Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
- ISD::SETUNE);
- Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
- Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
- Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
+ Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
+ LHSHi, RHSHi, ISD::SETOEQ);
+ Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
+ LHSLo, RHSLo, CCCode);
+ Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
+ Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
+ LHSHi, RHSHi, ISD::SETUNE);
+ Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
+ LHSHi, RHSHi, CCCode);
+ Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
+ Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
Tmp2 = SDValue();
break;
}
if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
if (RHSCST->isAllOnesValue()) {
// Comparison to -1.
- Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
+ Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
Tmp2 = RHSLo;
break;
}
- Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
- Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
- Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
+ Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
+ Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
+ Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
break;
default:
// If this is a comparison of the sign bit, just look at the top part.
// X > -1, x < 0
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
- if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
+ if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
CST->isNullValue()) || // X < 0
(cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
CST->isAllOnesValue())) { // X > -1
// NOTE: on targets without efficient SELECT of bools, we can always use
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
- Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
- LowCC, false, DagCombineInfo);
+ Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
+ LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
if (!Tmp1.getNode())
- Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
- Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
- CCCode, false, DagCombineInfo);
+ Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
+ LHSLo, RHSLo, LowCC);
+ Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+ LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
if (!Tmp2.getNode())
- Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
- RHSHi,CC);
-
+ Tmp2 = DAG.getNode(ISD::SETCC, dl,
+ TLI.getSetCCResultType(LHSHi.getValueType()),
+ LHSHi, RHSHi,CC);
+
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
if ((Tmp1C && Tmp1C->isNullValue()) ||
Tmp1 = Tmp2;
Tmp2 = SDValue();
} else {
- Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
- ISD::SETEQ, false, DagCombineInfo);
+ Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
+ LHSHi, RHSHi, ISD::SETEQ, false,
+ DagCombineInfo, dl);
if (!Result.getNode())
- Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
- ISD::SETEQ);
- Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
+ Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
+ LHSHi, RHSHi, ISD::SETEQ);
+ Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
Result, Tmp1, Tmp2));
Tmp1 = Result;
Tmp2 = SDValue();
/// illegal condition code into AND / OR of multiple SETCC values.
void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
SDValue &LHS, SDValue &RHS,
- SDValue &CC) {
+ SDValue &CC,
+ DebugLoc dl) {
MVT OpVT = LHS.getValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
switch (TLI.getCondCodeAction(CCCode, OpVT)) {
// FIXME: Implement more expansions.
}
- SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
- SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
- LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
+ SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
+ SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
+ LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
RHS = SDValue();
CC = SDValue();
break;
/// The resultant code need not be legal.
SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
MVT SlotVT,
- MVT DestVT) {
+ MVT DestVT,
+ DebugLoc dl) {
// Create the stack frame object.
unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
SrcOp.getValueType().getTypeForMVT());
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
-
+
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
int SPFI = StackPtrFI->getIndex();
-
+ const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
+
unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
unsigned SlotSize = SlotVT.getSizeInBits();
unsigned DestSize = DestVT.getSizeInBits();
unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
DestVT.getTypeForMVT());
-
+
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
SDValue Store;
-
+
if (SrcSize > SlotSize)
- Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
- PseudoSourceValue::getFixedStack(SPFI), 0,
- SlotVT, false, SrcAlign);
+ Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
+ SV, 0, SlotVT, false, SrcAlign);
else {
assert(SrcSize == SlotSize && "Invalid store");
- Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
- PseudoSourceValue::getFixedStack(SPFI), 0,
- false, SrcAlign);
+ Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
+ SV, 0, false, SrcAlign);
}
-
+
// Result is a load from the stack slot.
if (SlotSize == DestSize)
- return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
-
+ return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
+
assert(SlotSize < DestSize && "Unknown extension!");
- return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
+ return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
false, DestAlign);
}
SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
+ DebugLoc dl = Node->getDebugLoc();
// Create a vector sized/aligned stack slot, store the value to element #0,
// then load the whole vector back out.
SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
int SPFI = StackPtrFI->getIndex();
- SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
+ StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
- return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
+ return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
PseudoSourceValue::getFixedStack(SPFI), 0);
}
/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
/// support the operation, but do support the resultant vector type.
SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
-
- // If the only non-undef value is the low element, turn this into a
+
+ // If the only non-undef value is the low element, turn this into a
// SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
unsigned NumElems = Node->getNumOperands();
bool isOnlyLowElement = true;
SDValue SplatValue = Node->getOperand(0);
-
+ DebugLoc dl = Node->getDebugLoc();
+
// FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
// and use a bitmask instead of a list of elements.
std::map<SDValue, std::vector<unsigned> > Values;
if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
SplatValue.getOpcode() != ISD::UNDEF)
isConstant = false;
-
+
for (unsigned i = 1; i < NumElems; ++i) {
SDValue V = Node->getOperand(i);
Values[V].push_back(i);
V.getOpcode() != ISD::UNDEF)
isConstant = false;
}
-
+
if (isOnlyLowElement) {
// If the low element is an undef too, then this whole things is an undef.
if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
- return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
+ return DAG.getUNDEF(Node->getValueType(0));
// Otherwise, turn this into a scalar_to_vector node.
- return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
Node->getOperand(0));
}
-
+
// If all elements are constants, create a load from the constant pool.
if (isConstant) {
MVT VT = Node->getValueType(0);
std::vector<Constant*> CV;
for (unsigned i = 0, e = NumElems; i != e; ++i) {
- if (ConstantFPSDNode *V =
+ if (ConstantFPSDNode *V =
dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
- } else if (ConstantSDNode *V =
+ } else if (ConstantSDNode *V =
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
} else {
assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
- const Type *OpNTy =
+ const Type *OpNTy =
Node->getOperand(0).getValueType().getTypeForMVT();
CV.push_back(UndefValue::get(OpNTy));
}
Constant *CP = ConstantVector::get(CV);
SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
- return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
}
-
+
if (SplatValue.getNode()) { // Splat of one value?
// Build the shuffle constant vector: <0, 0, 0, 0>
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
std::vector<SDValue> ZeroVec(NumElems, Zero);
- SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
- &ZeroVec[0], ZeroVec.size());
+ SDValue SplatMask = DAG.getBUILD_VECTOR(MaskVT, dl,
+ &ZeroVec[0], ZeroVec.size());
// If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
// Get the splatted value into the low element of a vector register.
- SDValue LowValVec =
- DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
-
+ SDValue LowValVec =
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
+ Node->getValueType(0), SplatValue);
+
// Return shuffle(LowValVec, undef, <0,0,0,0>)
- return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
- DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
+ Node->getValueType(0), LowValVec,
+ DAG.getUNDEF(Node->getValueType(0)),
SplatMask);
}
}
-
+
// If there are only two unique elements, we may be able to turn this into a
// vector shuffle.
if (Values.size() == 2) {
Val2 = MI->first;
else
Val2 = (++MI)->first;
-
- // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
+
+ // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
// vector shuffle has the undef vector on the RHS.
if (Val1.getOpcode() == ISD::UNDEF)
std::swap(Val1, Val2);
-
+
// Build the shuffle constant vector: e.g. <0, 4, 0, 4>
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT MaskEltVT = MaskVT.getVectorElementType();
if (Val2.getOpcode() != ISD::UNDEF)
MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
else
- MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
-
- SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
- &MaskVec[0], MaskVec.size());
+ MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
+
+ SDValue ShuffleMask = DAG.getBUILD_VECTOR(MaskVT, dl,
+ &MaskVec[0], MaskVec.size());
// If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
- if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
+ if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
+ Node->getValueType(0)) &&
isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
- Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
- Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
+ Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1);
+ Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2);
SDValue Ops[] = { Val1, Val2, ShuffleMask };
// Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
- return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
}
}
-
+
// Otherwise, we can't handle this case efficiently. Allocate a sufficiently
// aligned object on the stack, store each element into it, then load
// the result as a vector.
MVT VT = Node->getValueType(0);
// Create the stack frame object.
SDValue FIPtr = DAG.CreateStackTemporary(VT);
-
+ int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
+ const Value *SV = PseudoSourceValue::getFixedStack(FI);
+
// Emit a store of each element to the stack slot.
SmallVector<SDValue, 8> Stores;
unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
// Ignore undef elements.
if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
-
+
unsigned Offset = TypeByteSize*i;
-
+
SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
- Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
-
- Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
- NULL, 0));
+ Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
+
+ Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
+ Idx, SV, Offset));
}
-
+
SDValue StoreChain;
if (!Stores.empty()) // Not all undef elements?
- StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&Stores[0], Stores.size());
else
StoreChain = DAG.getEntryNode();
-
+
// Result is a load from the stack slot.
- return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
+ return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
}
void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
SDValue Op, SDValue Amt,
- SDValue &Lo, SDValue &Hi) {
+ SDValue &Lo, SDValue &Hi,
+ DebugLoc dl) {
// Expand the subcomponents.
SDValue LHSL, LHSH;
ExpandOp(Op, LHSL, LHSH);
SDValue Ops[] = { LHSL, LHSH, Amt };
MVT VT = LHSL.getValueType();
- Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
+ Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
Hi = Lo.getValue(1);
}
/// libcall on this target, return false. Otherwise, return true with the
/// low-parts expanded into Lo and Hi.
bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
- SDValue &Lo, SDValue &Hi) {
+ SDValue &Lo, SDValue &Hi,
+ DebugLoc dl) {
assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
"This is not a shift!");
Hi = DAG.getConstant(0, NVT);
} else if (Cst > NVTBits) {
Lo = DAG.getConstant(0, NVT);
- Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
+ Hi = DAG.getNode(ISD::SHL, dl,
+ NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
} else if (Cst == NVTBits) {
Lo = DAG.getConstant(0, NVT);
Hi = InL;
} else {
- Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
- Hi = DAG.getNode(ISD::OR, NVT,
- DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
- DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
+ Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
+ Hi = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
+ DAG.getNode(ISD::SRL, dl, NVT, InL,
+ DAG.getConstant(NVTBits-Cst, ShTy)));
}
return true;
case ISD::SRL:
Lo = DAG.getConstant(0, NVT);
Hi = DAG.getConstant(0, NVT);
} else if (Cst > NVTBits) {
- Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
+ Lo = DAG.getNode(ISD::SRL, dl, NVT,
+ InH, DAG.getConstant(Cst-NVTBits,ShTy));
Hi = DAG.getConstant(0, NVT);
} else if (Cst == NVTBits) {
Lo = InH;
Hi = DAG.getConstant(0, NVT);
} else {
- Lo = DAG.getNode(ISD::OR, NVT,
- DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
- DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
- Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
+ Lo = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
+ DAG.getNode(ISD::SHL, dl, NVT, InH,
+ DAG.getConstant(NVTBits-Cst, ShTy)));
+ Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
}
return true;
case ISD::SRA:
if (Cst > VTBits) {
- Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
+ Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else if (Cst > NVTBits) {
- Lo = DAG.getNode(ISD::SRA, NVT, InH,
+ Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
DAG.getConstant(Cst-NVTBits, ShTy));
- Hi = DAG.getNode(ISD::SRA, NVT, InH,
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else if (Cst == NVTBits) {
Lo = InH;
- Hi = DAG.getNode(ISD::SRA, NVT, InH,
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else {
- Lo = DAG.getNode(ISD::OR, NVT,
- DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
- DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
- Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
+ Lo = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
+ DAG.getNode(ISD::SHL, dl,
+ NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
}
return true;
}
}
-
+
// Okay, the shift amount isn't constant. However, if we can tell that it is
// >= 32 or < 32, we can still simplify it, without knowing the actual value.
APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
-
+
// If we know that if any of the high bits of the shift amount are one, then
// we can do this as a couple of simple shifts.
if (KnownOne.intersects(Mask)) {
// Mask out the high bit, which we know is set.
- Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
+ Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
DAG.getConstant(~Mask, Amt.getValueType()));
-
+
// Expand the incoming operand to be shifted, so that we have its parts
SDValue InL, InH;
ExpandOp(Op, InL, InH);
switch(Opc) {
case ISD::SHL:
Lo = DAG.getConstant(0, NVT); // Low part is zero.
- Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
+ Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
return true;
case ISD::SRL:
Hi = DAG.getConstant(0, NVT); // Hi part is zero.
- Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
+ Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
return true;
case ISD::SRA:
- Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
DAG.getConstant(NVTBits-1, Amt.getValueType()));
- Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
+ Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
return true;
}
}
-
+
// If we know that the high bits of the shift amount are all zero, then we can
// do this as a couple of simple shifts.
if ((KnownZero & Mask) == Mask) {
// Compute 32-amt.
- SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
+ SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
DAG.getConstant(NVTBits, Amt.getValueType()),
Amt);
-
+
// Expand the incoming operand to be shifted, so that we have its parts
SDValue InL, InH;
ExpandOp(Op, InL, InH);
switch(Opc) {
case ISD::SHL:
- Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
- Hi = DAG.getNode(ISD::OR, NVT,
- DAG.getNode(ISD::SHL, NVT, InH, Amt),
- DAG.getNode(ISD::SRL, NVT, InL, Amt2));
+ Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
+ Hi = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
+ DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
return true;
case ISD::SRL:
- Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
- Lo = DAG.getNode(ISD::OR, NVT,
- DAG.getNode(ISD::SRL, NVT, InL, Amt),
- DAG.getNode(ISD::SHL, NVT, InH, Amt2));
+ Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
+ Lo = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
+ DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
return true;
case ISD::SRA:
- Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
- Lo = DAG.getNode(ISD::OR, NVT,
- DAG.getNode(ISD::SRL, NVT, InL, Amt),
- DAG.getNode(ISD::SHL, NVT, InH, Amt2));
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
+ Lo = DAG.getNode(ISD::OR, dl, NVT,
+ DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
+ DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
return true;
}
}
-
+
return false;
}
SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
bool isSigned, SDValue &Hi) {
assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
- // The input chain to this libcall is the entry node of the function.
+ // The input chain to this libcall is the entry node of the function.
// Legalizing the call will automatically add the previous call to the
// dependence.
SDValue InChain = DAG.getEntryNode();
-
+
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
MVT ArgVT = Node->getOperand(i).getValueType();
const Type *ArgTy = ArgVT.getTypeForMVT();
- Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
+ Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
const Type *RetTy = Node->getValueType(0).getTypeForMVT();
std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
- CallingConv::C, false, Callee, Args, DAG);
+ CallingConv::C, false, Callee, Args, DAG,
+ Node->getDebugLoc());
// Legalize the call sequence, starting with the chain. This will advance
// the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
///
SDValue SelectionDAGLegalize::
-LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
+LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
+ DebugLoc dl) {
bool isCustom = false;
SDValue Tmp1;
switch (getTypeAction(Op.getValueType())) {
if (Result.getNode())
Result = DAG.UpdateNodeOperands(Result, Tmp1);
else
- Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
+ Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
DestTy, Tmp1);
if (isCustom) {
Tmp1 = TLI.LowerOperation(Result, DAG);
}
break;
case TargetLowering::Expand:
- Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
+ Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
break;
case TargetLowering::Promote:
- Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
+ Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
break;
}
break;
case Expand:
- Result = ExpandIntToFP(isSigned, DestTy, Op);
+ Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
break;
case Promote:
Tmp1 = PromoteOp(Op);
if (isSigned) {
- Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
+ Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
Tmp1, DAG.getValueType(Op.getValueType()));
} else {
- Tmp1 = DAG.getZeroExtendInReg(Tmp1,
+ Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
Op.getValueType());
}
if (Result.getNode())
Result = DAG.UpdateNodeOperands(Result, Tmp1);
else
- Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
+ Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
DestTy, Tmp1);
Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
break;
/// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
///
SDValue SelectionDAGLegalize::
-ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
+ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
MVT SourceVT = Source.getValueType();
bool ExpandSource = getTypeAction(SourceVT) == Expand;
if (DestTy.getVectorNumElements() == 1) {
SDValue Scalar = ScalarizeVectorOp(Source);
SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
- DestEltTy, Scalar);
- return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
+ DestEltTy, Scalar, dl);
+ return DAG.getBUILD_VECTOR(DestTy, dl, Result);
}
SDValue Lo, Hi;
SplitVectorOp(Source, Lo, Hi);
MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
DestTy.getVectorNumElements() / 2);
- SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
- SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
- return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
+ SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
+ Lo, dl);
+ SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
+ Hi, dl);
+ return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
HiResult));
}
if (ExpandSource) {
SDValue Lo;
ExpandOp(Source, Lo, Hi);
- Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
+ Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
} else {
// The comparison for the sign bit will use the entire operand.
Hi = Source;
case TargetLowering::Expand:
break; // This case is handled below.
case TargetLowering::Custom: {
- SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
+ SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
Source), DAG);
if (NV.getNode())
return LegalizeOp(NV);
// If this is unsigned, and not supported, first perform the conversion to
// signed, then adjust the result if the sign bit is set.
- SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
+ SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
- SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
- DAG.getConstant(0, Hi.getValueType()),
- ISD::SETLT);
+ SDValue SignSet = DAG.getSetCC(dl,
+ TLI.getSetCCResultType(Hi.getValueType()),
+ Hi, DAG.getConstant(0, Hi.getValueType()),
+ ISD::SETLT);
SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
- SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
+ SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
SignSet, Four, Zero);
uint64_t FF = 0x5f800000ULL;
if (TLI.isLittleEndian()) FF <<= 32;
SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
- CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
+ CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
if (DestTy == MVT::f32)
- FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
+ FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
else if (DestTy.bitsGT(MVT::f32))
// FIXME: Avoid the extend by construction the right constantpool?
- FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
+ FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
CPIdx,
PseudoSourceValue::getConstantPool(), 0,
MVT::f32, false, Alignment);
- else
+ else
assert(0 && "Unexpected conversion");
MVT SCVT = SignedConv.getValueType();
// constructing will be expanded into a libcall.
if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
- SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
+ SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
SignedConv, SignedConv.getValue(1));
}
- SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
+ SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
}
- return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
+ return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
}
// Check to see if the target has a custom way to lower this. If so, use it.
case TargetLowering::Expand:
break; // This case is handled below.
case TargetLowering::Custom: {
- SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
+ SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
Source), DAG);
if (NV.getNode())
return LegalizeOp(NV);
if (ExpandSource) {
SDValue SrcLo, SrcHi;
ExpandOp(Source, SrcLo, SrcHi);
- Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
+ Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
}
RTLIB::Libcall LC = isSigned ?
RTLIB::getUINTTOFP(SourceVT, DestTy);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
- Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
+ Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
SDValue HiPart;
SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
if (Result.getValueType() != DestTy && HiPart.getNode())
- Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
+ Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
return Result;
}
/// legal for the target.
SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue Op0,
- MVT DestVT) {
+ MVT DestVT,
+ DebugLoc dl) {
if (Op0.getValueType() == MVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
-
+
// Get the stack frame index of a 8 byte buffer.
SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
-
+
// word offset constant for Hi/Lo address computation
SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
// set up Hi and Lo (into buffer) address based on endian
SDValue Hi = StackSlot;
- SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
+ SDValue Lo = DAG.getNode(ISD::ADD, dl,
+ TLI.getPointerTy(), StackSlot,WordOff);
if (TLI.isLittleEndian())
std::swap(Hi, Lo);
-
+
// if signed map to unsigned space
SDValue Op0Mapped;
if (isSigned) {
// constant used to invert sign bit (signed to unsigned mapping)
SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
- Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
+ Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
} else {
Op0Mapped = Op0;
}
// store the lo of the constructed double - based on integer input
- SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
+ SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
Op0Mapped, Lo, NULL, 0);
// initial hi portion of constructed double
SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
// store the hi of the constructed double - biased exponent
- SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
+ SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
// load the constructed double
- SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result
SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL)
: BitsToDouble(0x4330000000000000ULL),
MVT::f64);
// subtract the bias
- SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
// final result
SDValue Result;
// handle final rounding
// do nothing
Result = Sub;
} else if (DestVT.bitsLT(MVT::f64)) {
- Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
+ Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
} else if (DestVT.bitsGT(MVT::f64)) {
- Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
+ Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
return Result;
}
assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
- SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
+ SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
- SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
- DAG.getConstant(0, Op0.getValueType()),
- ISD::SETLT);
+ SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
+ Op0, DAG.getConstant(0, Op0.getValueType()),
+ ISD::SETLT);
SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
- SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
+ SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
SignSet, Four, Zero);
// If the sign bit of the integer is set, the large number will be treated
SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
- CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
+ CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
if (DestVT == MVT::f32)
- FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
+ FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
else {
FudgeInReg =
- LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
+ LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
MVT::f32, false, Alignment));
}
- return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
+ return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
}
/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
/// operation that takes a larger input.
SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
MVT DestVT,
- bool isSigned) {
+ bool isSigned,
+ DebugLoc dl) {
// First step, figure out the appropriate *INT_TO_FP operation to use.
MVT NewInTy = LegalOp.getValueType();
// Okay, we found the operation and type to use. Zero extend our input to the
// desired type then run the operation on it.
- return DAG.getNode(OpToUse, DestVT,
+ return DAG.getNode(OpToUse, dl, DestVT,
DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
- NewInTy, LegalOp));
+ dl, NewInTy, LegalOp));
}
/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
/// operation that returns a larger result.
SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
MVT DestVT,
- bool isSigned) {
+ bool isSigned,
+ DebugLoc dl) {
// First step, figure out the appropriate FP_TO*INT operation to use.
MVT NewOutTy = DestVT;
// Otherwise, try a larger type.
}
-
+
// Okay, we found the operation and type to use.
- SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
+ SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
// If the operation produces an invalid type, it must be custom lowered. Use
// the target lowering hooks to expand it. Just keep the low part of the
// expanded operation, we know that we're truncating anyway.
if (getTypeAction(NewOutTy) == Expand) {
- Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
- assert(Operation.getNode() && "Didn't return anything");
+ SmallVector<SDValue, 2> Results;
+ TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
+ assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
+ Operation = Results[0];
}
// Truncate the result of the extended FP_TO_*INT operation to the desired
// size.
- return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
+ return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
}
/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
///
-SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
+SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
MVT VT = Op.getValueType();
MVT SHVT = TLI.getShiftAmountTy();
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
switch (VT.getSimpleVT()) {
default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
case MVT::i16:
- Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
- Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
- return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
+ Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
+ Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
+ return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
case MVT::i32:
- Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
- Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
- Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
- Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
- Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
- Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
- Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
- Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
- return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
+ Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
+ Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
+ Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
+ Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
+ Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
+ Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
+ Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
+ Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
+ return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
case MVT::i64:
- Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
- Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
- Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
- Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
- Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
- Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
- Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
- Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
- Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
- Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
- Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
- Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
- Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
- Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
- Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
- Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
- Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
- Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
- Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
- Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
- return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
+ Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
+ Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
+ Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
+ Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
+ Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
+ Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
+ Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
+ Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
+ Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
+ Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
+ Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
+ Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
+ Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
+ Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
+ Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
+ Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
+ Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
+ Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
+ Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
+ Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
+ return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
}
}
/// ExpandBitCount - Expand the specified bitcount instruction into operations.
///
-SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
+SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
+ DebugLoc dl) {
switch (Opc) {
default: assert(0 && "Cannot expand this yet!");
case ISD::CTPOP: {
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
- SDValue Tmp2 = DAG.getConstant(mask[i], VT);
+ unsigned EltSize = VT.isVector() ?
+ VT.getVectorElementType().getSizeInBits() : len;
+ SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
- Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
- DAG.getNode(ISD::AND, VT,
- DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
+ Op = DAG.getNode(ISD::ADD, dl, VT,
+ DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
+ DAG.getNode(ISD::AND, dl, VT,
+ DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
+ Tmp2));
}
return Op;
}
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
- Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
+ Op = DAG.getNode(ISD::OR, dl, VT, Op,
+ DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
}
- Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
- return DAG.getNode(ISD::CTPOP, VT, Op);
+ Op = DAG.getNOT(dl, Op, VT);
+ return DAG.getNode(ISD::CTPOP, dl, VT, Op);
}
case ISD::CTTZ: {
// for now, we use: { return popcount(~x & (x - 1)); }
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
MVT VT = Op.getValueType();
- SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
- SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
- DAG.getNode(ISD::XOR, VT, Op, Tmp2),
- DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
+ SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
+ DAG.getNOT(dl, Op, VT),
+ DAG.getNode(ISD::SUB, dl, VT, Op,
+ DAG.getConstant(1, VT)));
// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
- if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
- TLI.isOperationLegal(ISD::CTLZ, VT))
- return DAG.getNode(ISD::SUB, VT,
+ if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
+ TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
+ return DAG.getNode(ISD::SUB, dl, VT,
DAG.getConstant(VT.getSizeInBits(), VT),
- DAG.getNode(ISD::CTLZ, VT, Tmp3));
- return DAG.getNode(ISD::CTPOP, VT, Tmp3);
+ DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
+ return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
}
}
}
MVT VT = Op.getValueType();
MVT NVT = TLI.getTypeToTransformTo(VT);
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
assert(getTypeAction(VT) == Expand && "Not an expanded type!");
assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
VT.isVector()) && "Cannot expand to FP value or to larger int value!");
case ISD::CopyFromReg:
assert(0 && "CopyFromReg must be legal!");
case ISD::FP_ROUND_INREG:
- if (VT == MVT::ppcf128 &&
- TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
+ if (VT == MVT::ppcf128 &&
+ TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
TargetLowering::Custom) {
SDValue SrcLo, SrcHi, Src;
ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
- Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
+ Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
SDValue Result = TLI.LowerOperation(
- DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
+ DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
Lo = Result.getNode()->getOperand(0);
Hi = Result.getNode()->getOperand(1);
Lo = ExpandEXTRACT_VECTOR_ELT(Op);
return ExpandOp(Lo, Lo, Hi);
case ISD::UNDEF:
- Lo = DAG.getNode(ISD::UNDEF, NVT);
- Hi = DAG.getNode(ISD::UNDEF, NVT);
+ Lo = DAG.getUNDEF(NVT);
+ Hi = DAG.getUNDEF(NVT);
break;
case ISD::Constant: {
unsigned NVTBits = NVT.getSizeInBits();
APInt api = CFP->getValueAPF().bitcastToAPInt();
Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
MVT::f64);
- Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
+ Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
MVT::f64);
break;
}
Lo = Node->getOperand(0);
Hi = Node->getOperand(1);
break;
-
+
case ISD::MERGE_VALUES:
if (Node->getNumValues() == 1) {
ExpandOp(Op.getOperand(0), Lo, Hi);
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
break;
-
+
case ISD::SIGN_EXTEND_INREG:
ExpandOp(Node->getOperand(0), Lo, Hi);
// sext_inreg the low part if needed.
- Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
-
+ Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
+
// The high part gets the sign extension from the lo-part. This handles
// things like sextinreg V:i64 from i8.
- Hi = DAG.getNode(ISD::SRA, NVT, Lo,
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getConstant(NVT.getSizeInBits()-1,
TLI.getShiftAmountTy()));
break;
case ISD::BSWAP: {
ExpandOp(Node->getOperand(0), Lo, Hi);
- SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
- Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
+ SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
+ Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
Lo = TempLo;
break;
}
-
+
case ISD::CTPOP:
ExpandOp(Node->getOperand(0), Lo, Hi);
- Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
- DAG.getNode(ISD::CTPOP, NVT, Lo),
- DAG.getNode(ISD::CTPOP, NVT, Hi));
+ Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
+ DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
+ DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
Hi = DAG.getConstant(0, NVT);
break;
// ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
ExpandOp(Node->getOperand(0), Lo, Hi);
SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
- SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
- SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
- ISD::SETNE);
- SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
- LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
+ SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
+ SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
+ BitsC, ISD::SETNE);
+ SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
+ LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
- Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
+ Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
Hi = DAG.getConstant(0, NVT);
break;
}
// cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
ExpandOp(Node->getOperand(0), Lo, Hi);
SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
- SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
- SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
- ISD::SETNE);
- SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
- HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
+ SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
+ SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
+ BitsC, ISD::SETNE);
+ SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
+ HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
- Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
+ Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
Hi = DAG.getConstant(0, NVT);
break;
}
case ISD::VAARG: {
SDValue Ch = Node->getOperand(0); // Legalize the chain.
SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
- Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
- Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
+ Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
+ Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
// Remember that we legalized the chain.
Hi = LegalizeOp(Hi);
std::swap(Lo, Hi);
break;
}
-
+
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Node);
SDValue Ch = LD->getChain(); // Legalize the chain.
bool isVolatile = LD->isVolatile();
if (ExtType == ISD::NON_EXTLOAD) {
- Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
+ Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
isVolatile, Alignment);
if (VT == MVT::f32 || VT == MVT::f64) {
// f32->i32 or f64->i64 one to one expansion.
// Increment the pointer to the other half.
unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
- Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
Alignment = MinAlign(Alignment, IncrementSize);
- Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
+ Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
isVolatile, Alignment);
// Build a factor node to remember that this load is independent of the
// other one.
- SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Remember that we legalized the chain.
if ((VT == MVT::f64 && EVT == MVT::f32) ||
(VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
- SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
+ SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
SVOffset, isVolatile, Alignment);
// Remember that we legalized the chain.
AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
- ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
+ ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
break;
}
-
+
if (EVT == NVT)
- Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
+ Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
SVOffset, isVolatile, Alignment);
else
- Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
+ Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
SVOffset, EVT, isVolatile,
Alignment);
-
+
// Remember that we legalized the chain.
AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
// The high part is obtained by SRA'ing all but one of the bits of the
// lo part.
unsigned LoSize = Lo.getValueType().getSizeInBits();
- Hi = DAG.getNode(ISD::SRA, NVT, Lo,
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
} else if (ExtType == ISD::ZEXTLOAD) {
// The high part is just a zero.
Hi = DAG.getConstant(0, NVT);
} else /* if (ExtType == ISD::EXTLOAD) */ {
// The high part is undefined.
- Hi = DAG.getNode(ISD::UNDEF, NVT);
+ Hi = DAG.getUNDEF(NVT);
}
}
break;
SDValue LL, LH, RL, RH;
ExpandOp(Node->getOperand(0), LL, LH);
ExpandOp(Node->getOperand(1), RL, RH);
- Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
- Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
+ Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
+ Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
break;
}
case ISD::SELECT: {
ExpandOp(Node->getOperand(2), RL, RH);
if (getTypeAction(NVT) == Expand)
NVT = TLI.getTypeToExpandTo(NVT);
- Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
+ Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
if (VT != MVT::f32)
- Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
+ Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
break;
}
case ISD::SELECT_CC: {
ExpandOp(Node->getOperand(3), FL, FH);
if (getTypeAction(NVT) == Expand)
NVT = TLI.getTypeToExpandTo(NVT);
- Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
+ Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
Node->getOperand(1), TL, FL, Node->getOperand(4));
if (VT != MVT::f32)
- Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
+ Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
Node->getOperand(1), TH, FH, Node->getOperand(4));
break;
}
case ISD::ANY_EXTEND:
// The low part is any extension of the input (which degenerates to a copy).
- Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
+ Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
// The high part is undefined.
- Hi = DAG.getNode(ISD::UNDEF, NVT);
+ Hi = DAG.getUNDEF(NVT);
break;
case ISD::SIGN_EXTEND: {
// The low part is just a sign extension of the input (which degenerates to
// a copy).
- Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
+ Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
// The high part is obtained by SRA'ing all but one of the bits of the lo
// part.
unsigned LoSize = Lo.getValueType().getSizeInBits();
- Hi = DAG.getNode(ISD::SRA, NVT, Lo,
+ Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
break;
}
case ISD::ZERO_EXTEND:
// The low part is just a zero extension of the input (which degenerates to
// a copy).
- Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
+ Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
// The high part is just a zero.
Hi = DAG.getConstant(0, NVT);
break;
-
+
case ISD::TRUNCATE: {
// The input value must be larger than this value. Expand *it*.
SDValue NewLo;
ExpandOp(Node->getOperand(0), NewLo, Hi);
-
+
// The low part is now either the right size, or it is closer. If not the
// right size, make an illegal truncate so we recursively expand it.
if (NewLo.getValueType() != Node->getValueType(0))
- NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
+ NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
ExpandOp(NewLo, Lo, Hi);
break;
}
-
+
case ISD::BIT_CONVERT: {
SDValue Tmp;
if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
}
- Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
+ Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
}
// f32 / f64 must be expanded to i32 / i64.
if (VT == MVT::f32 || VT == MVT::f64) {
- Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
if (getTypeAction(NVT) == Expand)
ExpandOp(Lo, Lo, Hi);
break;
// Turn this into a load/store pair by default.
if (Tmp.getNode() == 0)
- Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
-
+ Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
+
ExpandOp(Tmp, Lo, Hi);
break;
}
case ISD::READCYCLECOUNTER: {
- assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
+ assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
TargetLowering::Custom &&
"Must custom expand ReadCycleCounter");
SDValue Tmp = TLI.LowerOperation(Op, DAG);
break;
}
- case ISD::ATOMIC_CMP_SWAP_64: {
+ case ISD::ATOMIC_CMP_SWAP: {
// This operation does not need a loop.
SDValue Tmp = TLI.LowerOperation(Op, DAG);
assert(Tmp.getNode() && "Node must be custom expanded!");
break;
}
- case ISD::ATOMIC_LOAD_ADD_64:
- case ISD::ATOMIC_LOAD_SUB_64:
- case ISD::ATOMIC_LOAD_AND_64:
- case ISD::ATOMIC_LOAD_OR_64:
- case ISD::ATOMIC_LOAD_XOR_64:
- case ISD::ATOMIC_LOAD_NAND_64:
- case ISD::ATOMIC_SWAP_64: {
+ case ISD::ATOMIC_LOAD_ADD:
+ case ISD::ATOMIC_LOAD_SUB:
+ case ISD::ATOMIC_LOAD_AND:
+ case ISD::ATOMIC_LOAD_OR:
+ case ISD::ATOMIC_LOAD_XOR:
+ case ISD::ATOMIC_LOAD_NAND:
+ case ISD::ATOMIC_SWAP: {
// These operations require a loop to be generated. We can't do that yet,
// so substitute a target-dependent pseudo and expand that later.
SDValue In2Lo, In2Hi, In2;
ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
- In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
+ In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
- SDValue Replace =
- DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
+ SDValue Replace =
+ DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
+ Op.getOperand(0), Op.getOperand(1), In2,
Anode->getSrcValue(), Anode->getAlignment());
SDValue Result = TLI.LowerOperation(Replace, DAG);
ExpandOp(Result.getValue(0), Lo, Hi);
case Promote: Op = PromoteOp (Node->getOperand(0)); break;
}
- Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
+ Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
// Now that the custom expander is done, expand the result, which is still
// VT.
case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
case Promote: Op = PromoteOp (Node->getOperand(0)); break;
}
-
- Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
+
+ Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
// Now that the custom expander is done, expand the result.
if (Op.getNode()) {
// If the target wants custom lowering, do so.
SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
- SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
+ SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
Op = TLI.LowerOperation(Op, DAG);
if (Op.getNode()) {
// Now that the custom expander is done, expand the result, which is
break;
}
}
-
- // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
+
+ // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
// this X << 1 as X+X.
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
- if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
- TLI.isOperationLegal(ISD::ADDE, NVT)) {
+ if (ShAmt->getAPIntValue() == 1 &&
+ TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
+ TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
SDValue LoOps[2], HiOps[3];
ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
LoOps[1] = LoOps[0];
- Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
+ Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[1] = HiOps[0];
HiOps[2] = Lo.getValue(1);
- Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
+ Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
break;
}
}
-
+
// If we can emit an efficient shift operation, do so now.
- if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
+ if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
break;
// If this target supports SHL_PARTS, use it.
TLI.getOperationAction(ISD::SHL_PARTS, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
- ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
+ ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
+ ShiftAmt, Lo, Hi, dl);
break;
}
// If the target wants custom lowering, do so.
SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
- SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
+ SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
Op = TLI.LowerOperation(Op, DAG);
if (Op.getNode()) {
// Now that the custom expander is done, expand the result, which is
break;
}
}
-
+
// If we can emit an efficient shift operation, do so now.
- if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
+ if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
break;
// If this target supports SRA_PARTS, use it.
TLI.getOperationAction(ISD::SRA_PARTS, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
- ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
+ ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
+ ShiftAmt, Lo, Hi, dl);
break;
}
// If the target wants custom lowering, do so.
SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
- SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
+ SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
Op = TLI.LowerOperation(Op, DAG);
if (Op.getNode()) {
// Now that the custom expander is done, expand the result, which is
}
// If we can emit an efficient shift operation, do so now.
- if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
+ if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
break;
// If this target supports SRL_PARTS, use it.
TLI.getOperationAction(ISD::SRL_PARTS, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
- ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
+ ExpandShiftParts(ISD::SRL_PARTS,
+ Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
break;
}
SDValue LHSL, LHSH, RHSL, RHSH;
ExpandOp(Node->getOperand(0), LHSL, LHSH);
ExpandOp(Node->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[2], HiOps[3];
LoOps[0] = LHSL;
LoOps[1] = RHSL;
bool hasCarry = false;
for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
MVT AVT = MVT::getIntegerVT(BitSize);
- if (TLI.isOperationLegal(OpV, AVT)) {
+ if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
hasCarry = true;
break;
}
}
if(hasCarry) {
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
if (Node->getOpcode() == ISD::ADD) {
- Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
+ Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
- Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
+ Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
} else {
- Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
+ Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
- Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
+ Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
}
break;
} else {
if (Node->getOpcode() == ISD::ADD) {
- Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
- Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
- SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
+ Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
+ Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
+ SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
Lo, LoOps[0], ISD::SETULT);
- SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
- DAG.getConstant(1, NVT),
+ SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
+ DAG.getConstant(1, NVT),
DAG.getConstant(0, NVT));
- SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
+ SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
Lo, LoOps[1], ISD::SETULT);
- SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
- DAG.getConstant(1, NVT),
+ SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
+ DAG.getConstant(1, NVT),
Carry1);
- Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
+ Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
} else {
- Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
- Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
- SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
- SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
- DAG.getConstant(1, NVT),
+ Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
+ Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
+ SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
+ SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
+ DAG.getConstant(1, NVT),
DAG.getConstant(0, NVT));
- Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
+ Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
}
break;
}
}
-
+
case ISD::ADDC:
case ISD::SUBC: {
// Expand the subcomponents.
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
-
+
if (Node->getOpcode() == ISD::ADDC) {
- Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
+ Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
- Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
+ Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
} else {
- Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
+ Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
- Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
+ Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
}
// Remember that we legalized the flag.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
SDValue HiOps[3] = { LHSH, RHSH };
-
- Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
+
+ Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
HiOps[2] = Lo.getValue(1);
- Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
-
+ Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
+
// Remember that we legalized the flag.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
break;
break;
}
}
-
- bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
- bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
- bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
- bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
+
+ bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
+ bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
+ bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
+ bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
SDValue LL, LH, RL, RH;
ExpandOp(Node->getOperand(0), LL, LH);
// The inputs are both zero-extended.
if (HasUMUL_LOHI) {
// We can emit a umul_lohi.
- Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
+ Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
Hi = SDValue(Lo.getNode(), 1);
break;
}
if (HasMULHU) {
// We can emit a mulhu+mul.
- Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
- Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
+ Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
+ Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
break;
}
}
// The input values are both sign-extended.
if (HasSMUL_LOHI) {
// We can emit a smul_lohi.
- Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
+ Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
Hi = SDValue(Lo.getNode(), 1);
break;
}
if (HasMULHS) {
// We can emit a mulhs+mul.
- Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
- Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
+ Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
+ Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
break;
}
}
if (HasUMUL_LOHI) {
// Lo,Hi = umul LHS, RHS.
- SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
+ SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
DAG.getVTList(NVT, NVT), LL, RL);
Lo = UMulLOHI;
Hi = UMulLOHI.getValue(1);
- RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
- LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
- Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
- Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
+ RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
+ LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
+ Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
+ Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
break;
}
if (HasMULHU) {
- Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
- Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
- RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
- LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
- Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
- Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
+ Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
+ Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
+ RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
+ LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
+ Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
+ Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
break;
}
}
Node->getOperand(0).getValueType()==MVT::f64);
const uint64_t zero = 0;
if (Node->getOperand(0).getValueType()==MVT::f32)
- Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
+ Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
else
Hi = Node->getOperand(0);
Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
}
case ISD::FSQRT:
case ISD::FSIN:
- case ISD::FCOS:
+ case ISD::FCOS:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
if (VT == MVT::ppcf128) {
SDValue Tmp;
ExpandOp(Node->getOperand(0), Lo, Tmp);
- Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
+ Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
// lo = hi==fabs(hi) ? lo : -lo;
- Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
- Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
+ Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
+ Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
DAG.getCondCode(ISD::SETEQ));
break;
}
SDValue Mask = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
: DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
- Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
- Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
- Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
+ Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
+ Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
if (getTypeAction(NVT) == Expand)
ExpandOp(Lo, Lo, Hi);
break;
case ISD::FNEG: {
if (VT == MVT::ppcf128) {
ExpandOp(Node->getOperand(0), Lo, Hi);
- Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
- Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
+ Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
+ Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
break;
}
SDValue Mask = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
: DAG.getConstantFP(BitsToFloat(1U << 31), VT);
- Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
- Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
- Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
+ Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
+ Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
if (getTypeAction(NVT) == Expand)
ExpandOp(Lo, Lo, Hi);
break;
if (getTypeAction(SrcVT) == Promote) {
SDValue Tmp = PromoteOp(Node->getOperand(0));
Tmp = isSigned
- ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
+ ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
DAG.getValueType(SrcVT))
- : DAG.getZeroExtendInReg(Tmp, SrcVT);
+ : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
SrcVT = Node->getOperand(0).getValueType();
}
if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
static const uint64_t zero = 0;
if (isSigned) {
- Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
+ Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
Node->getOperand(0)));
Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
} else {
static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
- Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
+ Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
Node->getOperand(0)));
Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
- Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
+ Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
// X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
- ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
- DAG.getConstant(0, MVT::i32),
- DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
+ ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
+ MVT::ppcf128, Node->getOperand(0),
+ DAG.getConstant(0, MVT::i32),
+ DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
DAG.getConstantFP(
APFloat(APInt(128, 2, TwoE32)),
MVT::ppcf128)),
if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
// si64->ppcf128 done by libcall, below
static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
- ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
- Lo, Hi);
- Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
+ ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
+ Node->getOperand(0)), Lo, Hi);
+ Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
// x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
- ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
- DAG.getConstant(0, MVT::i64),
- DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
+ ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
+ Node->getOperand(0),
+ DAG.getConstant(0, MVT::i64),
+ DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
DAG.getConstantFP(
APFloat(APInt(128, 2, TwoE64)),
MVT::ppcf128)),
}
Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
- Node->getOperand(0));
+ Node->getOperand(0), dl);
if (getTypeAction(Lo.getValueType()) == Expand)
// float to i32 etc. can be 'expanded' to a single node.
ExpandOp(Lo, Lo, Hi);
SDValue &Hi) {
assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
unsigned NumElements = Op.getValueType().getVectorNumElements();
assert(NumElements > 1 && "Cannot split a single element vector!");
Hi = I->second.second;
return;
}
-
+
switch (Node->getOpcode()) {
- default:
+ default:
#ifndef NDEBUG
Node->dump(&DAG);
#endif
assert(0 && "Unhandled operation in SplitVectorOp!");
case ISD::UNDEF:
- Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
- Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
+ Lo = DAG.getUNDEF(NewVT_Lo);
+ Hi = DAG.getUNDEF(NewVT_Hi);
break;
case ISD::BUILD_PAIR:
Lo = Node->getOperand(0);
unsigned Index = Idx->getZExtValue();
SDValue ScalarOp = Node->getOperand(1);
if (Index < NewNumElts_Lo)
- Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
+ Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
DAG.getIntPtrConstant(Index));
else
- Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
+ Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
DAG.getIntPtrConstant(Index - NewNumElts_Lo));
break;
}
SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
Node->getOperand(1),
- Node->getOperand(2));
+ Node->getOperand(2), dl);
SplitVectorOp(Tmp, Lo, Hi);
break;
}
SDValue Mask = Node->getOperand(2);
SmallVector<SDValue, 8> Ops;
MVT PtrVT = TLI.getPointerTy();
-
- // Insert all of the elements from the input that are needed. We use
+
+ // Insert all of the elements from the input that are needed. We use
// buildvector of extractelement here because the input vectors will have
// to be legalized, so this makes the code simpler.
for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
SDValue IdxNode = Mask.getOperand(i);
if (IdxNode.getOpcode() == ISD::UNDEF) {
- Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
+ Ops.push_back(DAG.getUNDEF(NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
InVec = Node->getOperand(1);
Idx -= NumElements;
}
- Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
+ Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
DAG.getConstant(Idx, PtrVT)));
}
- Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
+ Lo = DAG.getBUILD_VECTOR(NewVT_Lo, dl, &Ops[0], Ops.size());
Ops.clear();
-
+
for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
SDValue IdxNode = Mask.getOperand(i);
if (IdxNode.getOpcode() == ISD::UNDEF) {
- Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
+ Ops.push_back(DAG.getUNDEF(NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
InVec = Node->getOperand(1);
Idx -= NumElements;
}
- Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
+ Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
DAG.getConstant(Idx, PtrVT)));
}
- Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
+ Hi = DAG.getBUILD_VECTOR(NewVT_Hi, dl, &Ops[0], Ops.size());
break;
}
case ISD::BUILD_VECTOR: {
- SmallVector<SDValue, 8> LoOps(Node->op_begin(),
+ SmallVector<SDValue, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumElts_Lo);
- Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
+ Lo = DAG.getBUILD_VECTOR(NewVT_Lo, dl, &LoOps[0], LoOps.size());
- SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
+ SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
Node->op_end());
- Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
+ Hi = DAG.getBUILD_VECTOR(NewVT_Hi, dl, &HiOps[0], HiOps.size());
break;
}
case ISD::CONCAT_VECTORS: {
} else {
SmallVector<SDValue, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumSubvectors);
- Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
+ Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
+ &LoOps[0], LoOps.size());
SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
Node->op_end());
- Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
+ Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
+ &HiOps[0], HiOps.size());
}
break;
}
SDValue Idx = Op.getOperand(1);
MVT IdxVT = Idx.getValueType();
- Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
+ Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
if (CIdx) {
- Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
+ Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
IdxVT));
} else {
- Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
+ Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
DAG.getConstant(NewNumElts_Lo, IdxVT));
- Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
+ Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
}
break;
}
// Handle a vector merge.
SDValue CL, CH;
SplitVectorOp(Cond, CL, CH);
- Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
- Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
+ Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
+ Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
} else {
// Handle a simple select with vector operands.
- Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
- Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
+ Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
+ Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
}
break;
}
SDValue CondLHS = Node->getOperand(0);
SDValue CondRHS = Node->getOperand(1);
SDValue CondCode = Node->getOperand(4);
-
+
SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(2), LL, LH);
SplitVectorOp(Node->getOperand(3), RL, RH);
-
+
// Handle a simple select with vector operands.
- Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
+ Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
LL, RL, CondCode);
- Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
+ Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
LH, RH, CondCode);
break;
}
SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH);
- Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
- Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
+ Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
+ Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
break;
}
case ISD::ADD:
case ISD::XOR:
case ISD::UREM:
case ISD::SREM:
- case ISD::FREM: {
+ case ISD::FREM:
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL: {
SDValue LL, LH, RL, RH;
SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH);
-
- Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
- Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
+
+ Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
+ Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
break;
}
case ISD::FP_ROUND:
SDValue L, H;
SplitVectorOp(Node->getOperand(0), L, H);
- Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
- Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
+ Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
+ Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
break;
}
case ISD::CTTZ:
SDValue L, H;
SplitVectorOp(Node->getOperand(0), L, H);
- Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
- Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
+ Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
+ Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
break;
}
case ISD::CONVERT_RNDSAT: {
SDValue RndOp = Node->getOperand(3);
SDValue SatOp = Node->getOperand(4);
- Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
+ Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
RndOp, SatOp, CvtCode);
- Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
+ Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
RndOp, SatOp, CvtCode);
break;
}
bool isVolatile = LD->isVolatile();
assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
- SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
MVT MemNewEltVT = MemoryVT.getVectorElementType();
MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
- Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
+ Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
NewVT_Lo, Ch, Ptr, Offset,
SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
- Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
Alignment = MinAlign(Alignment, IncrementSize);
- Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
+ Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
NewVT_Hi, Ch, Ptr, Offset,
SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
-
+
// Build a factor node to remember that this load is independent of the
// other one.
- SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
-
+
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
break;
SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
- SDValue St = DAG.getStore(DAG.getEntryNode(),
+ SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
InOp, Ptr,
PseudoSourceValue::getFixedStack(FI), 0);
- InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
+ InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
PseudoSourceValue::getFixedStack(FI), 0);
}
// Split the vector and convert each of the pieces now.
SplitVectorOp(InOp, Lo, Hi);
- Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
- Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
+ Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
break;
}
}
-
+
// Remember in a map if the values will be reused later.
- bool isNew =
+ bool isNew =
SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
assert(isNew && "Value already split?!?");
isNew = isNew;
SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
MVT NewVT = Op.getValueType().getVectorElementType();
assert(Op.getValueType().getVectorNumElements() == 1);
-
+
// See if we already scalarized it.
std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
if (I != ScalarizedNodes.end()) return I->second;
-
+
SDValue Result;
switch (Node->getOpcode()) {
- default:
+ default:
#ifndef NDEBUG
Node->dump(&DAG); cerr << "\n";
#endif
case ISD::AND:
case ISD::OR:
case ISD::XOR:
- Result = DAG.getNode(Node->getOpcode(),
- NewVT,
+ Result = DAG.getNode(Node->getOpcode(), dl,
+ NewVT,
ScalarizeVectorOp(Node->getOperand(0)),
ScalarizeVectorOp(Node->getOperand(1)));
break;
case ISD::ANY_EXTEND:
case ISD::TRUNCATE:
case ISD::FP_EXTEND:
- Result = DAG.getNode(Node->getOpcode(),
- NewVT,
+ Result = DAG.getNode(Node->getOpcode(), dl,
+ NewVT,
ScalarizeVectorOp(Node->getOperand(0)));
break;
case ISD::CONVERT_RNDSAT: {
SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
- Result = DAG.getConvertRndSat(NewVT, Op0,
+ Result = DAG.getConvertRndSat(NewVT, dl, Op0,
DAG.getValueType(NewVT),
DAG.getValueType(Op0.getValueType()),
Node->getOperand(3),
}
case ISD::FPOWI:
case ISD::FP_ROUND:
- Result = DAG.getNode(Node->getOpcode(),
- NewVT,
+ Result = DAG.getNode(Node->getOpcode(), dl,
+ NewVT,
ScalarizeVectorOp(Node->getOperand(0)),
Node->getOperand(1));
break;
bool isVolatile = LD->isVolatile();
assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
- SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
-
- Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
+ SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
+
+ Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
NewVT, Ch, Ptr, Offset, SV, SVOffset,
MemoryVT.getVectorElementType(),
isVolatile, Alignment);
break;
}
case ISD::EXTRACT_SUBVECTOR:
- Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
- Node->getOperand(1));
+ Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
+ Node->getOperand(0), Node->getOperand(1));
break;
case ISD::BIT_CONVERT: {
SDValue Op0 = Op.getOperand(0);
if (Op0.getValueType().getVectorNumElements() == 1)
Op0 = ScalarizeVectorOp(Op0);
- Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
break;
}
case ISD::SELECT:
- Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
+ Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
ScalarizeVectorOp(Op.getOperand(1)),
ScalarizeVectorOp(Op.getOperand(2)));
break;
case ISD::SELECT_CC:
- Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
+ Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
Node->getOperand(1),
ScalarizeVectorOp(Op.getOperand(2)),
ScalarizeVectorOp(Op.getOperand(3)),
case ISD::VSETCC: {
SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
- Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
- Op.getOperand(2));
- Result = DAG.getNode(ISD::SELECT, NewVT, Result,
+ Result = DAG.getNode(ISD::SETCC, dl,
+ TLI.getSetCCResultType(Op0.getValueType()),
+ Op0, Op1, Op.getOperand(2));
+ Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
DAG.getConstant(-1ULL, NewVT),
DAG.getConstant(0ULL, NewVT));
break;
SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
if (I != WidenNodes.end()) return I->second;
-
+
MVT VT = Op.getValueType();
assert(VT.isVector() && "Cannot widen non-vector type!");
SDValue Result;
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
MVT EVT = VT.getVectorElementType();
unsigned NumElts = VT.getVectorNumElements();
// code to pack/unpack the results. It is the function that calls widen
// that is responsible for seeing this doesn't happen.
switch (Node->getOpcode()) {
- default:
+ default:
#ifndef NDEBUG
Node->dump(&DAG);
#endif
assert(0 && "Unexpected operation in WidenVectorOp!");
break;
case ISD::UNDEF:
- Result = DAG.getNode(ISD::UNDEF, WidenVT);
+ Result = DAG.getUNDEF(WidenVT);
break;
case ISD::BUILD_VECTOR: {
// Build a vector with undefined for the new nodes
SDValueVector NewOps(Node->op_begin(), Node->op_end());
for (unsigned i = NumElts; i < NewNumElts; ++i) {
- NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
+ NewOps.push_back(DAG.getUNDEF(EVT));
}
- Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
+ Result = DAG.getBUILD_VECTOR(WidenVT, dl, &NewOps[0], NewOps.size());
break;
}
case ISD::INSERT_VECTOR_ELT: {
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
- Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
+ Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
Node->getOperand(1), Node->getOperand(2));
break;
}
NewOps.push_back(PermOp.getOperand(i));
} else {
unsigned Idx =
- cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
+ cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
if (Idx < NumElts) {
NewOps.push_back(PermOp.getOperand(i));
}
else {
NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
PermOp.getOperand(i).getValueType()));
- }
+ }
}
}
for (unsigned i = NumElts; i < NewNumElts; ++i) {
- NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
+ NewOps.push_back(DAG.getUNDEF(PVT));
}
-
- SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
- MVT::getVectorVT(PVT, NewOps.size()),
- &NewOps[0], NewOps.size());
-
- Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
+
+ SDValue Tmp3 = DAG.getBUILD_VECTOR(MVT::getVectorVT(PVT, NewOps.size()), dl,
+ &NewOps[0], NewOps.size());
+
+ Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
break;
}
case ISD::LOAD: {
SDValue Tmp1 = Node->getOperand(0);
// Converts between two different types so we need to determine
// the correct widen type for the input operand.
- MVT TVT = Tmp1.getValueType();
- assert(TVT.isVector() && "can not widen non vector type");
- MVT TEVT = TVT.getVectorElementType();
- assert(WidenVT.getSizeInBits() % EVT.getSizeInBits() == 0 &&
- "can not widen bit bit convert that are not multiple of element type");
- MVT TWidenVT = MVT::getVectorVT(TEVT,
- WidenVT.getSizeInBits()/EVT.getSizeInBits());
- Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
- assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
+ MVT InVT = Tmp1.getValueType();
+ unsigned WidenSize = WidenVT.getSizeInBits();
+ if (InVT.isVector()) {
+ MVT InEltVT = InVT.getVectorElementType();
+ unsigned InEltSize = InEltVT.getSizeInBits();
+ assert(WidenSize % InEltSize == 0 &&
+ "can not widen bit convert that are not multiple of element type");
+ MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
+ Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
+ assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
+ } else {
+ // If the result size is a multiple of the input size, widen the input
+ // and then convert.
+ unsigned InSize = InVT.getSizeInBits();
+ assert(WidenSize % InSize == 0 &&
+ "can not widen bit convert that are not multiple of element type");
+ unsigned NewNumElts = WidenSize / InSize;
+ SmallVector<SDValue, 16> Ops(NewNumElts);
+ SDValue UndefVal = DAG.getUNDEF(InVT);
+ Ops[0] = Tmp1;
+ for (unsigned i = 1; i < NewNumElts; ++i)
+ Ops[i] = UndefVal;
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
+ MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
+ Result = DAG.getBUILD_VECTOR(NewInVT, dl, &Ops[0], NewNumElts);
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
}
break;
}
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT: {
+ case ISD::FP_TO_UINT:
+ case ISD::FP_ROUND: {
SDValue Tmp1 = Node->getOperand(0);
// Converts between two different types so we need to determine
// the correct widen type for the input operand.
MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
-
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
- }
+ Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
break;
}
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND:
- case ISD::FP_ROUND:
case ISD::SIGN_EXTEND_INREG:
case ISD::FABS:
case ISD::FNEG:
case ISD::CTTZ:
case ISD::CTLZ: {
// Unary op widening
- SDValue Tmp1;
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
-
+ SDValue Tmp1;
Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
assert(Tmp1.getValueType() == WidenVT);
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
- }
+ Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
break;
}
case ISD::CONVERT_RNDSAT: {
SDValue RndOp = Node->getOperand(3);
SDValue SatOp = Node->getOperand(4);
-
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
-
SDValue SrcOp = Node->getOperand(0);
// Converts between two different types so we need to determine
SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
- Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
+ Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
RndOp, SatOp, CvtCode);
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
- }
break;
}
case ISD::FPOW:
- case ISD::FPOWI:
+ case ISD::FPOWI:
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
case ISD::UREM:
case ISD::BSWAP: {
// Binary op widening
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
-
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code by first
- // Widening to the right type and then unroll the beast.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
- }
+ Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
break;
}
case ISD::SHL:
case ISD::SRA:
case ISD::SRL: {
- // Binary op with one non vector operand
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
-
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
assert(Tmp1.getValueType() == WidenVT);
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Node->getOperand(1));
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
- }
+ SDValue ShOp = Node->getOperand(1);
+ MVT ShVT = ShOp.getValueType();
+ MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
+ WidenVT.getVectorNumElements());
+ ShOp = WidenVectorOp(ShOp, NewShVT);
+ assert(ShOp.getValueType() == NewShVT);
+ Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
break;
}
+
case ISD::EXTRACT_VECTOR_ELT: {
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
assert(Tmp1.getValueType() == WidenVT);
- Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
+ Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
break;
}
case ISD::CONCAT_VECTORS: {
// We could widen on a multiple of the incoming operand if necessary.
unsigned NumConcat = NewNumElts / NumElts;
assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
- std::vector<SDValue> UnOps(NumElts, DAG.getNode(ISD::UNDEF,
- VT.getVectorElementType()));
- SDValue UndefVal = DAG.getNode(ISD::BUILD_VECTOR, VT,
- &UnOps[0], UnOps.size());
+ SDValue UndefVal = DAG.getUNDEF(VT);
SmallVector<SDValue, 8> MOps;
MOps.push_back(Op);
for (unsigned i = 1; i != NumConcat; ++i) {
MOps.push_back(UndefVal);
}
- Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
+ Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
&MOps[0], MOps.size()));
break;
}
if (Tmp1VTNumElts < NewNumElts)
Result = WidenVectorOp(Tmp1, WidenVT);
else
- Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
+ Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
}
} else if (NewNumElts % NumElts == 0) {
// Widen the extracted subvector.
unsigned NumConcat = NewNumElts / NumElts;
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
+ SDValue UndefVal = DAG.getUNDEF(VT);
SmallVector<SDValue, 8> MOps;
MOps.push_back(Op);
for (unsigned i = 1; i != NumConcat; ++i) {
MOps.push_back(UndefVal);
}
- Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
+ Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
&MOps[0], MOps.size()));
} else {
assert(0 && "can not widen extract subvector");
}
case ISD::SELECT: {
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
-
// Determine new condition widen type and widen
SDValue Cond1 = Node->getOperand(0);
MVT CondVT = Cond1.getValueType();
SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code by first
- // Widening to the right type and then unroll the beast.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
- }
+ Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
break;
}
-
- case ISD::SELECT_CC: {
- TargetLowering::LegalizeAction action =
- TLI.getOperationAction(Node->getOpcode(), WidenVT);
+ case ISD::SELECT_CC: {
// Determine new condition widen type and widen
SDValue Cond1 = Node->getOperand(0);
SDValue Cond2 = Node->getOperand(1);
SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
"operands not widen");
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
+ Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
Tmp2, Node->getOperand(4));
- switch (action) {
- default: assert(0 && "action not supported");
- case TargetLowering::Legal:
- break;
- case TargetLowering::Promote:
- // We defer the promotion to when we legalize the op
- break;
- case TargetLowering::Expand:
- // Expand the operation into a bunch of nasty scalar code by first
- // Widening to the right type and then unroll the beast.
- Result = LegalizeOp(UnrollVectorOp(Result));
- break;
- }
break;
}
case ISD::VSETCC: {
MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
- Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
+ Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
Node->getOperand(2));
break;
}
- case ISD::ATOMIC_CMP_SWAP_8:
- case ISD::ATOMIC_CMP_SWAP_16:
- case ISD::ATOMIC_CMP_SWAP_32:
- case ISD::ATOMIC_CMP_SWAP_64:
- case ISD::ATOMIC_LOAD_ADD_8:
- case ISD::ATOMIC_LOAD_SUB_8:
- case ISD::ATOMIC_LOAD_AND_8:
- case ISD::ATOMIC_LOAD_OR_8:
- case ISD::ATOMIC_LOAD_XOR_8:
- case ISD::ATOMIC_LOAD_NAND_8:
- case ISD::ATOMIC_LOAD_MIN_8:
- case ISD::ATOMIC_LOAD_MAX_8:
- case ISD::ATOMIC_LOAD_UMIN_8:
- case ISD::ATOMIC_LOAD_UMAX_8:
- case ISD::ATOMIC_SWAP_8:
- case ISD::ATOMIC_LOAD_ADD_16:
- case ISD::ATOMIC_LOAD_SUB_16:
- case ISD::ATOMIC_LOAD_AND_16:
- case ISD::ATOMIC_LOAD_OR_16:
- case ISD::ATOMIC_LOAD_XOR_16:
- case ISD::ATOMIC_LOAD_NAND_16:
- case ISD::ATOMIC_LOAD_MIN_16:
- case ISD::ATOMIC_LOAD_MAX_16:
- case ISD::ATOMIC_LOAD_UMIN_16:
- case ISD::ATOMIC_LOAD_UMAX_16:
- case ISD::ATOMIC_SWAP_16:
- case ISD::ATOMIC_LOAD_ADD_32:
- case ISD::ATOMIC_LOAD_SUB_32:
- case ISD::ATOMIC_LOAD_AND_32:
- case ISD::ATOMIC_LOAD_OR_32:
- case ISD::ATOMIC_LOAD_XOR_32:
- case ISD::ATOMIC_LOAD_NAND_32:
- case ISD::ATOMIC_LOAD_MIN_32:
- case ISD::ATOMIC_LOAD_MAX_32:
- case ISD::ATOMIC_LOAD_UMIN_32:
- case ISD::ATOMIC_LOAD_UMAX_32:
- case ISD::ATOMIC_SWAP_32:
- case ISD::ATOMIC_LOAD_ADD_64:
- case ISD::ATOMIC_LOAD_SUB_64:
- case ISD::ATOMIC_LOAD_AND_64:
- case ISD::ATOMIC_LOAD_OR_64:
- case ISD::ATOMIC_LOAD_XOR_64:
- case ISD::ATOMIC_LOAD_NAND_64:
- case ISD::ATOMIC_LOAD_MIN_64:
- case ISD::ATOMIC_LOAD_MAX_64:
- case ISD::ATOMIC_LOAD_UMIN_64:
- case ISD::ATOMIC_LOAD_UMAX_64:
- case ISD::ATOMIC_SWAP_64: {
+ case ISD::ATOMIC_CMP_SWAP:
+ case ISD::ATOMIC_LOAD_ADD:
+ case ISD::ATOMIC_LOAD_SUB:
+ case ISD::ATOMIC_LOAD_AND:
+ case ISD::ATOMIC_LOAD_OR:
+ case ISD::ATOMIC_LOAD_XOR:
+ case ISD::ATOMIC_LOAD_NAND:
+ case ISD::ATOMIC_LOAD_MIN:
+ case ISD::ATOMIC_LOAD_MAX:
+ case ISD::ATOMIC_LOAD_UMIN:
+ case ISD::ATOMIC_LOAD_UMAX:
+ case ISD::ATOMIC_SWAP: {
// For now, we assume that using vectors for these operations don't make
// much sense so we just split it. We return an empty result
SDValue X, Y;
} // end switch (Node->getOpcode())
- assert(Result.getNode() && "Didn't set a result!");
+ assert(Result.getNode() && "Didn't set a result!");
if (Result != Op)
Result = LegalizeOp(Result);
// Width: Preferred width of element type
// VVT: Vector value type whose size we must match.
// Returns VecEVT and EVT - the vector type and its associated element type
-static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
+static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
MVT& EVT, MVT& VecEVT) {
// We start with the preferred width, make it a power of 2 and see if
// we can find a vector type of that width. If not, we reduce it by
unsigned Alignment,
bool isVolatile,
unsigned LdWidth,
- MVT ResType) {
+ MVT ResType,
+ DebugLoc dl) {
// We assume that we have good rules to handle loading power of two loads so
// we break down the operations to power of 2 loads. The strategy is to
// load the largest power of 2 that we can easily transform to a legal vector
FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
EVTWidth = EVT.getSizeInBits();
- SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
+ SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
isVolatile, Alignment);
- SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
+ SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
LdChain.push_back(LdOp.getValue(1));
-
+
// Check if we can load the element with one instruction
if (LdWidth == EVTWidth) {
- return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
}
// The vector element order is endianness dependent.
unsigned Idx = 1;
LdWidth -= EVTWidth;
unsigned Offset = 0;
-
+
while (LdWidth > 0) {
unsigned Increment = EVTWidth / 8;
Offset += Increment;
- BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
+ BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
DAG.getIntPtrConstant(Increment));
if (LdWidth < EVTWidth) {
EVTWidth = EVT.getSizeInBits();
// Readjust position and vector position based on new load type
Idx = Idx * (oEVTWidth/EVTWidth);
- VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
+ VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
}
-
- SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
+
+ SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
SVOffset+Offset, isVolatile,
MinAlign(Alignment, Offset));
LdChain.push_back(LdOp.getValue(1));
- VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
+ VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
DAG.getIntPtrConstant(Idx++));
-
+
LdWidth -= EVTWidth;
}
- return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
}
bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
// to memory mapping is strange (e.g., vector elements are not
// stored in some sequential order).
- // It must be true that the widen vector type is bigger than where
+ // It must be true that the widen vector type is bigger than where
// we need to load from.
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
MVT LdVT = LD->getMemoryVT();
+ DebugLoc dl = LD->getDebugLoc();
assert(LdVT.isVector() && NVT.isVector());
assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
-
+
// Load information
SDValue Chain = LD->getChain();
SDValue BasePtr = LD->getBasePtr();
bool isVolatile = LD->isVolatile();
const Value *SV = LD->getSrcValue();
unsigned int LdWidth = LdVT.getSizeInBits();
-
+
// Load value as a large register
SDValueVector LdChain;
Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
- Alignment, isVolatile, LdWidth, NVT);
+ Alignment, isVolatile, LdWidth, NVT, dl);
if (LdChain.size() == 1) {
TFOp = LdChain[0];
return true;
}
else {
- TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
+ TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &LdChain[0], LdChain.size());
return false;
}
}
unsigned Alignment,
bool isVolatile,
SDValue ValOp,
- unsigned StWidth) {
+ unsigned StWidth,
+ DebugLoc dl) {
// Breaks the stores into a series of power of 2 width stores. For any
// width, we convert the vector to the vector of element size that we
// want to store. This avoids requiring a stack convert.
-
+
// Find a width of the element type we can store with
MVT VVT = ValOp.getValueType();
MVT EVT, VecEVT;
FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
EVTWidth = EVT.getSizeInBits();
- SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
- SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
+ SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
+ SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
DAG.getIntPtrConstant(0));
- SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
+ SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
isVolatile, Alignment);
StChain.push_back(StOp);
if (StWidth == EVTWidth) {
return;
}
-
+
unsigned Idx = 1;
StWidth -= EVTWidth;
unsigned Offset = 0;
-
+
while (StWidth > 0) {
unsigned Increment = EVTWidth / 8;
Offset += Increment;
- BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
+ BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
DAG.getIntPtrConstant(Increment));
-
+
if (StWidth < EVTWidth) {
// Our current type we are using is too large, use a smaller size by
// using a smaller power of 2
EVTWidth = EVT.getSizeInBits();
// Readjust position and vector position based on new load type
Idx = Idx * (oEVTWidth/EVTWidth);
- VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
+ VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
}
-
- EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
+
+ EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
DAG.getIntPtrConstant(Idx++));
- StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
+ StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
SVOffset + Offset, isVolatile,
MinAlign(Alignment, Offset)));
StWidth -= EVTWidth;
// be stored as a word). This will not work when a vector register
// to memory mapping is strange (e.g., vector elements are not
// stored in some sequential order).
-
+
MVT StVT = ST->getMemoryVT();
SDValue ValOp = ST->getValue();
+ DebugLoc dl = ST->getDebugLoc();
// Check if we have widen this node with another value
std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
if (I != WidenNodes.end())
ValOp = I->second;
-
+
MVT VVT = ValOp.getValueType();
// It must be true that we the widen vector type is bigger than where
// we need to store.
assert(StVT.isVector() && VVT.isVector());
- assert(StVT.getSizeInBits() < VVT.getSizeInBits());
+ assert(StVT.bitsLT(VVT));
assert(StVT.getVectorElementType() == VVT.getVectorElementType());
// Store value
SDValueVector StChain;
genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->getAlignment(),
- ST->isVolatile(), ValOp, StVT.getSizeInBits());
+ ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
if (StChain.size() == 1)
return StChain[0];
- else
- return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
+ else
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &StChain[0], StChain.size());
}
// SelectionDAG::Legalize - This is the entry point for the file.
//
-void SelectionDAG::Legalize() {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
/// run - This is the main entry point to this class.
///
- SelectionDAGLegalize(*this).LegalizeDAG();
+ SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();
}
projects / oota-llvm.git / blobdiff