#include "llvm/Target/TargetMachine.h"
using namespace llvm;
+unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &ValueMap) {
+ unsigned &Reg = ValueMap[V];
+ if (Reg != 0)
+ return Reg;
+
+ MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+ if (CI->getValue().getActiveBits() > 64)
+ return 0;
+ Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
+ } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
+ Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
+
+ if (!Reg) {
+ const APFloat &Flt = CF->getValueAPF();
+ MVT IntVT = TLI.getPointerTy();
+
+ uint64_t x[2];
+ uint32_t IntBitWidth = IntVT.getSizeInBits();
+ if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
+ APFloat::rmTowardZero) != APFloat::opOK)
+ return 0;
+ APInt IntVal(IntBitWidth, 2, x);
+
+ unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
+ ISD::Constant, IntVal.getZExtValue());
+ if (IntegerReg == 0)
+ return 0;
+ Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
+ if (Reg == 0)
+ return 0;
+ }
+ }
+
+ return Reg;
+}
+
/// SelectBinaryOp - Select and emit code for a binary operator instruction,
/// which has an opcode which directly corresponds to the given ISD opcode.
///
if (!TLI.isTypeLegal(VT))
return false;
- unsigned Op0 = ValueMap[I->getOperand(0)];
+ unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
if (Op0 == 0)
// Unhandled operand. Halt "fast" selection and bail.
return false;
// Check if the second operand is a constant and handle it appropriately.
if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
- unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
- CI->getZExtValue(), VT.getSimpleVT());
- if (ResultReg == 0)
- // Target-specific code wasn't able to find a machine opcode for
- // the given ISD opcode and type. Halt "fast" selection and bail.
- return false;
+ unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
+ ISDOpcode, Op0, CI->getZExtValue());
+ if (ResultReg != 0) {
+ // We successfully emitted code for the given LLVM Instruction.
+ ValueMap[I] = ResultReg;
+ return true;
+ }
+ }
- // We successfully emitted code for the given LLVM Instruction.
- ValueMap[I] = ResultReg;
- return true;
+ // Check if the second operand is a constant float.
+ if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
+ unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
+ ISDOpcode, Op0, CF);
+ if (ResultReg != 0) {
+ // We successfully emitted code for the given LLVM Instruction.
+ ValueMap[I] = ResultReg;
+ return true;
+ }
}
- unsigned Op1 = ValueMap[I->getOperand(1)];
+ unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
if (Op1 == 0)
// Unhandled operand. Halt "fast" selection and bail.
return false;
+ // Now we have both operands in registers. Emit the instruction.
unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
ISDOpcode, Op0, Op1);
if (ResultReg == 0)
bool FastISel::SelectGetElementPtr(Instruction *I,
DenseMap<const Value*, unsigned> &ValueMap) {
- unsigned N = ValueMap[I->getOperand(0)];
+ unsigned N = getRegForValue(I->getOperand(0), ValueMap);
if (N == 0)
// Unhandled operand. Halt "fast" selection and bail.
return false;
// N = N + Idx * ElementSize;
uint64_t ElementSize = TD.getABITypeSize(Ty);
- unsigned IdxN = ValueMap[Idx];
+ unsigned IdxN = getRegForValue(Idx, ValueMap);
if (IdxN == 0)
// Unhandled operand. Halt "fast" selection and bail.
return false;
return true;
}
-bool FastISel::SelectBitCast(Instruction *I,
- DenseMap<const Value*, unsigned> &ValueMap) {
- // BitCast consists of either an immediate to register move
- // or a register to register move.
- if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
- if (I->getType()->isInteger()) {
- MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
- unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
- ISD::Constant,
- CI->getZExtValue());
- if (!result)
- return false;
-
- ValueMap[I] = result;
- return true;
- }
-
- // TODO: Support vector and fp constants.
- return false;
- }
-
- if (!isa<Constant>(I->getOperand(0))) {
- // Bitcasts of non-constant values become reg-reg copies.
- MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
- MVT DstVT = MVT::getMVT(I->getType());
-
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
- !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
- // Unhandled type. Halt "fast" selection and bail.
- return false;
+bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
+ DenseMap<const Value*, unsigned> &ValueMap) {
+ MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ MVT DstVT = TLI.getValueType(I->getType());
- unsigned Op0 = ValueMap[I->getOperand(0)];
- if (Op0 == 0)
- // Unhandled operand. Halt "fast" selection and bail.
- return false;
+ if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+ DstVT == MVT::Other || !DstVT.isSimple() ||
+ !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+ // Unhandled type. Halt "fast" selection and bail.
+ return false;
- // First, try to perform the bitcast by inserting a reg-reg copy.
- unsigned ResultReg = 0;
- if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
- TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
- TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
- ResultReg = createResultReg(DstClass);
-
- bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- Op0, DstClass, SrcClass);
- if (!InsertedCopy)
- ResultReg = 0;
- }
+ unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
+ if (!InputReg)
+ // Unhandled operand. Halt "fast" selection and bail.
+ return false;
- // If the reg-reg copy failed, select a BIT_CONVERT opcode.
- if (!ResultReg)
- ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
- ISD::BIT_CONVERT, Op0);
+ unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
+ DstVT.getSimpleVT(),
+ Opcode,
+ InputReg);
+ if (!ResultReg)
+ return false;
- if (!ResultReg)
+ ValueMap[I] = ResultReg;
+ return true;
+}
+
+bool FastISel::SelectBitCast(Instruction *I,
+ DenseMap<const Value*, unsigned> &ValueMap) {
+ // If the bitcast doesn't change the type, just use the operand value.
+ if (I->getType() == I->getOperand(0)->getType()) {
+ unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
+ if (Reg == 0)
return false;
-
- ValueMap[I] = ResultReg;
+ ValueMap[I] = Reg;
return true;
}
- // TODO: Casting a non-integral constant?
- return false;
+ // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
+ MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ MVT DstVT = TLI.getValueType(I->getType());
+
+ if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
+ DstVT == MVT::Other || !DstVT.isSimple() ||
+ !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
+ // Unhandled type. Halt "fast" selection and bail.
+ return false;
+
+ unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
+ if (Op0 == 0)
+ // Unhandled operand. Halt "fast" selection and bail.
+ return false;
+
+ // First, try to perform the bitcast by inserting a reg-reg copy.
+ unsigned ResultReg = 0;
+ if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
+ TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
+ TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
+ ResultReg = createResultReg(DstClass);
+
+ bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+ Op0, DstClass, SrcClass);
+ if (!InsertedCopy)
+ ResultReg = 0;
+ }
+
+ // If the reg-reg copy failed, select a BIT_CONVERT opcode.
+ if (!ResultReg)
+ ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
+ ISD::BIT_CONVERT, Op0);
+
+ if (!ResultReg)
+ return false;
+
+ ValueMap[I] = ResultReg;
+ return true;
}
BasicBlock::iterator
break;
case Instruction::BitCast:
- if (!SelectBitCast(I, ValueMap)) return I;
- break;
+ if (!SelectBitCast(I, ValueMap)) return I; break;
case Instruction::FPToSI:
- if (!isa<ConstantFP>(I->getOperand(0))) {
- MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
- MVT DstVT = MVT::getMVT(I->getType());
-
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
- !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
- // Unhandled type. Halt "fast" selection and bail.
- return I;
-
- unsigned InputReg = ValueMap[I->getOperand(0)];
- if (!InputReg)
- // Unhandled operand. Halt "fast" selection and bail.
- return I;
-
- unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
- DstVT.getSimpleVT(),
- ISD::FP_TO_SINT,
- InputReg);
- if (!ResultReg)
- return I;
-
- ValueMap[I] = ResultReg;
- break;
- } else
- // TODO: Materialize the FP constant and then convert,
- // or attempt constant folding.
- return I;
-
+ if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
+ break;
case Instruction::ZExt:
- if (!isa<ConstantInt>(I->getOperand(0))) {
- MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
- MVT DstVT = MVT::getMVT(I->getType());
-
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
- !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
- // Unhandled type. Halt "fast" selection and bail.
- return I;
-
- unsigned InputReg = ValueMap[I->getOperand(0)];
- if (!InputReg)
- // Unhandled operand. Halt "fast" selection and bail.
- return I;
-
- unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
- DstVT.getSimpleVT(),
- ISD::ZERO_EXTEND,
- InputReg);
- if (!ResultReg)
- return I;
-
- ValueMap[I] = ResultReg;
- break;
- } else
- // TODO: Support constant operands
- return I;
-
+ if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
+ break;
+ case Instruction::SExt:
+ if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
+ break;
+ case Instruction::Trunc:
+ if (!SelectCast(I, ISD::TRUNCATE, ValueMap)) return I;
+ break;
case Instruction::SIToFP:
- if (!isa<ConstantInt>(I->getOperand(0))) {
- MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
- MVT DstVT = MVT::getMVT(I->getType());
-
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
- !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
- // Unhandled type. Halt "fast" selection and bail.
- return I;
-
- unsigned InputReg = ValueMap[I->getOperand(0)];
- if (!InputReg)
- // Unhandled operan. Halt "fast" selection and bail.
- return I;
-
- unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
- DstVT.getSimpleVT(),
- ISD::SINT_TO_FP,
- InputReg);
- if (!ResultReg)
+ if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
+ break;
+
+ case Instruction::IntToPtr: // Deliberate fall-through.
+ case Instruction::PtrToInt: {
+ MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ MVT DstVT = TLI.getValueType(I->getType());
+ if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
+ if (ValueMap[I->getOperand(0)]) {
+ ValueMap[I] = ValueMap[I->getOperand(0)];
+ break;
+ } else
+ // Unhandled operand
return I;
-
- ValueMap[I] = ResultReg;
+ } else if (DstVT.bitsGT(SrcVT)) {
+ if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
break;
} else {
- // Materialize constant and convert to FP.
- // TODO: Attempt constant folding?
- ConstantInt* CI = cast<ConstantInt>(I->getOperand(0));
- MVT SrcVT = MVT::getMVT(CI->getType());
- MVT DstVT = MVT::getMVT(I->getType());
-
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
- !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
- // Unhandled type. Halt "fast" selection and bail.
- return I;
-
- unsigned ResultReg1 = FastEmit_i(SrcVT.getSimpleVT(),
- SrcVT.getSimpleVT(),
- ISD::Constant, CI->getZExtValue());
- if (!ResultReg1)
- return I;
-
- unsigned ResultReg2 = FastEmit_r(SrcVT.getSimpleVT(),
- DstVT.getSimpleVT(),
- ISD::SINT_TO_FP,
- ResultReg1);
- if (!ResultReg2)
- return I;
-
- ValueMap[I] = ResultReg2;
- break;
+ // TODO: Handle SrcVT > DstVT, where truncation is needed.
+ return I;
}
-
+ }
+
default:
// Unhandled instruction. Halt "fast" selection and bail.
return I;
return 0;
}
+unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
+ ISD::NodeType, ConstantFP * /*FPImm*/) {
+ return 0;
+}
+
unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/,
uint64_t /*Imm*/) {
return 0;
}
+unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
+ ISD::NodeType, unsigned /*Op0*/,
+ ConstantFP * /*FPImm*/) {
+ return 0;
+}
+
unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
ISD::NodeType,
unsigned /*Op0*/, unsigned /*Op1*/,
unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
MVT::SimpleValueType ImmType) {
- unsigned ResultReg = 0;
// First check if immediate type is legal. If not, we can't use the ri form.
- if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
- ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
+ unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
if (ResultReg != 0)
return ResultReg;
unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
}
+/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
+/// to emit an instruction with a floating-point immediate operand using
+/// FastEmit_rf. If that fails, it materializes the immediate into a register
+/// and try FastEmit_rr instead.
+unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
+ unsigned Op0, ConstantFP *FPImm,
+ MVT::SimpleValueType ImmType) {
+ // First check if immediate type is legal. If not, we can't use the rf form.
+ unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
+ if (ResultReg != 0)
+ return ResultReg;
+
+ // Materialize the constant in a register.
+ unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
+ if (MaterialReg == 0) {
+ // If the target doesn't have a way to directly enter a floating-point
+ // value into a register, use an alternate approach.
+ // TODO: The current approach only supports floating-point constants
+ // that can be constructed by conversion from integer values. This should
+ // be replaced by code that creates a load from a constant-pool entry,
+ // which will require some target-specific work.
+ const APFloat &Flt = FPImm->getValueAPF();
+ MVT IntVT = TLI.getPointerTy();
+
+ uint64_t x[2];
+ uint32_t IntBitWidth = IntVT.getSizeInBits();
+ if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
+ APFloat::rmTowardZero) != APFloat::opOK)
+ return 0;
+ APInt IntVal(IntBitWidth, 2, x);
+
+ unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
+ ISD::Constant, IntVal.getZExtValue());
+ if (IntegerReg == 0)
+ return 0;
+ MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
+ ISD::SINT_TO_FP, IntegerReg);
+ if (MaterialReg == 0)
+ return 0;
+ }
+ return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
+}
+
unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
return MRI.createVirtualRegister(RC);
}
return ResultReg;
}
+unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC,
+ unsigned Op0, ConstantFP *FPImm) {
+ unsigned ResultReg = createResultReg(RC);
+ const TargetInstrDesc &II = TII.get(MachineInstOpcode);
+
+ BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
+ return ResultReg;
+}
+
unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1, uint64_t Imm) {
BuildMI(MBB, II, ResultReg).addImm(Imm);
return ResultReg;
}
+
+unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
+ const TargetRegisterClass* RC = MRI.getRegClass(Op0);
+ const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
+
+ unsigned ResultReg = createResultReg(SRC);
+ const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
+
+ BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
+ return ResultReg;
+}
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