Fix a thinko: When lowering fneg with xor, bitcast the operands

[oota-llvm.git] / lib / CodeGen / SelectionDAG / FastISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index f0c7086184330326a9a008c740bc6bcec9c9b27b..8550ea9813dd272812b6c262b27ca59d64a73952 100644 (file)
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -615,12 +615,25 @@ FastISel::SelectFNeg(User *I) {
   unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
   if (OpReg == 0) return false;
 
-  // Twiddle the sign bit with xor.
+  // Bitcast the value to integer, twiddle the sign bit with xor,
+  // and then bitcast it back to floating-point.
   EVT VT = TLI.getValueType(I->getType());
   if (VT.getSizeInBits() > 64) return false;
-  unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISD::XOR, OpReg,
-                                    UINT64_C(1) << (VT.getSizeInBits()-1),
-                                    VT.getSimpleVT());
+  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
+
+  unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
+                               ISD::BIT_CONVERT, OpReg);
+  if (IntReg == 0)
+    return false;
+
+  unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
+                                       UINT64_C(1) << (VT.getSizeInBits()-1),
+                                       IntVT.getSimpleVT());
+  if (IntResultReg == 0)
+    return false;
+
+  unsigned ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
+                                  ISD::BIT_CONVERT, IntResultReg);
   if (ResultReg == 0)
     return false;