//
// FIXME: select C, pow2, pow2 -> something smart
// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
-// FIXME: (select C, load A, load B) -> load (select C, A, B)
// FIXME: Dead stores -> nuke
-// FIXME: shr X, (and Y,31) -> shr X, Y
-// FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller)
+// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
// FIXME: mul (x, const) -> shifts + adds
// FIXME: undef values
// FIXME: make truncate see through SIGN_EXTEND and AND
// FIXME: divide by zero is currently left unfolded. do we want to turn this
// into an undef?
// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
-// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetLowering.h"
#include <algorithm>
#include <cmath>
+#include <iostream>
using namespace llvm;
namespace {
}
SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
+ ++NodesCombined;
DEBUG(std::cerr << "\nReplacing "; N->dump();
std::cerr << "\nWith: "; To[0].Val->dump();
std::cerr << " and " << To.size()-1 << " other values\n");
return SDOperand(N, 0);
}
+ bool DemandedBitsAreZero(SDOperand Op, uint64_t DemandedMask) {
+ TargetLowering::TargetLoweringOpt TLO(DAG);
+ uint64_t KnownZero, KnownOne;
+ if (TLI.SimplifyDemandedBits(Op, DemandedMask, KnownZero, KnownOne, TLO)){
+ WorkList.push_back(Op.Val);
+ CombineTo(TLO.Old.Val, TLO.New);
+ return true;
+ }
+ return false;
+ }
+
+ SDOperand CombineTo(SDNode *N, SDOperand Res) {
+ std::vector<SDOperand> To;
+ To.push_back(Res);
+ return CombineTo(N, To);
+ }
+
SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
std::vector<SDOperand> To;
To.push_back(Res0);
SDOperand visitZERO_EXTEND(SDNode *N);
SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
SDOperand visitTRUNCATE(SDNode *N);
-
+ SDOperand visitBIT_CONVERT(SDNode *N);
SDOperand visitFADD(SDNode *N);
SDOperand visitFSUB(SDNode *N);
SDOperand visitFMUL(SDNode *N);
SDOperand visitBRCONDTWOWAY(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
SDOperand visitBRTWOWAY_CC(SDNode *N);
-
SDOperand visitLOAD(SDNode *N);
+ SDOperand visitSTORE(SDNode *N);
+ SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
+
+ bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
SDOperand N3, ISD::CondCode CC);
SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans = true);
+
+ SDOperand BuildSDIV(SDNode *N);
+ SDOperand BuildUDIV(SDNode *N);
public:
DAGCombiner(SelectionDAG &D)
: DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
};
}
-/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
-/// this predicate to simplify operations downstream. Op and Mask are known to
-/// be the same type.
-static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
- const TargetLowering &TLI) {
- unsigned SrcBits;
- if (Mask == 0) return true;
-
- // If we know the result of a setcc has the top bits zero, use this info.
- switch (Op.getOpcode()) {
- case ISD::Constant:
- return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
- case ISD::SETCC:
- return ((Mask & 1) == 0) &&
- TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
- case ISD::ZEXTLOAD:
- SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
- return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
- case ISD::ZERO_EXTEND:
- SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
- return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
- case ISD::AssertZext:
- SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
- return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
- case ISD::AND:
- // If either of the operands has zero bits, the result will too.
- if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
- MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
- return true;
- // (X & C1) & C2 == 0 iff C1 & C2 == 0.
- if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
- return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
- return false;
- case ISD::OR:
- case ISD::XOR:
- return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
- MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
- case ISD::SELECT:
- return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
- MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
- case ISD::SELECT_CC:
- return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
- MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
- case ISD::SRL:
- // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
- if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- uint64_t NewVal = Mask << ShAmt->getValue();
- SrcBits = MVT::getSizeInBits(Op.getValueType());
- if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
- return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
+struct ms {
+ int64_t m; // magic number
+ int64_t s; // shift amount
+};
+
+struct mu {
+ uint64_t m; // magic number
+ int64_t a; // add indicator
+ int64_t s; // shift amount
+};
+
+/// magic - calculate the magic numbers required to codegen an integer sdiv as
+/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
+/// or -1.
+static ms magic32(int32_t d) {
+ int32_t p;
+ uint32_t ad, anc, delta, q1, r1, q2, r2, t;
+ const uint32_t two31 = 0x80000000U;
+ struct ms mag;
+
+ ad = abs(d);
+ t = two31 + ((uint32_t)d >> 31);
+ anc = t - 1 - t%ad; // absolute value of nc
+ p = 31; // initialize p
+ q1 = two31/anc; // initialize q1 = 2p/abs(nc)
+ r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
+ q2 = two31/ad; // initialize q2 = 2p/abs(d)
+ r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
+ do {
+ p = p + 1;
+ q1 = 2*q1; // update q1 = 2p/abs(nc)
+ r1 = 2*r1; // update r1 = rem(2p/abs(nc))
+ if (r1 >= anc) { // must be unsigned comparison
+ q1 = q1 + 1;
+ r1 = r1 - anc;
}
- return false;
- case ISD::SHL:
- // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
- if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- uint64_t NewVal = Mask >> ShAmt->getValue();
- return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
+ q2 = 2*q2; // update q2 = 2p/abs(d)
+ r2 = 2*r2; // update r2 = rem(2p/abs(d))
+ if (r2 >= ad) { // must be unsigned comparison
+ q2 = q2 + 1;
+ r2 = r2 - ad;
}
- return false;
- case ISD::ADD:
- // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
- if ((Mask&(Mask+1)) == 0) { // All low bits
- if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
- MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
- return true;
+ delta = ad - r2;
+ } while (q1 < delta || (q1 == delta && r1 == 0));
+
+ mag.m = (int32_t)(q2 + 1); // make sure to sign extend
+ if (d < 0) mag.m = -mag.m; // resulting magic number
+ mag.s = p - 32; // resulting shift
+ return mag;
+}
+
+/// magicu - calculate the magic numbers required to codegen an integer udiv as
+/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
+static mu magicu32(uint32_t d) {
+ int32_t p;
+ uint32_t nc, delta, q1, r1, q2, r2;
+ struct mu magu;
+ magu.a = 0; // initialize "add" indicator
+ nc = - 1 - (-d)%d;
+ p = 31; // initialize p
+ q1 = 0x80000000/nc; // initialize q1 = 2p/nc
+ r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
+ q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
+ r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
+ do {
+ p = p + 1;
+ if (r1 >= nc - r1 ) {
+ q1 = 2*q1 + 1; // update q1
+ r1 = 2*r1 - nc; // update r1
}
- break;
- case ISD::SUB:
- if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
- // We know that the top bits of C-X are clear if X contains less bits
- // than C (i.e. no wrap-around can happen). For example, 20-X is
- // positive if we can prove that X is >= 0 and < 16.
- unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
- if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
- unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
- uint64_t MaskV = (1ULL << (63-NLZ))-1;
- if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
- // High bits are clear this value is known to be >= C.
- unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
- if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
- return true;
- }
- }
+ else {
+ q1 = 2*q1; // update q1
+ r1 = 2*r1; // update r1
}
- break;
- case ISD::CTTZ:
- case ISD::CTLZ:
- case ISD::CTPOP:
- // Bit counting instructions can not set the high bits of the result
- // register. The max number of bits sets depends on the input.
- return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
-
- // TODO we could handle some SRA cases here.
- default: break;
- }
- return false;
+ if (r2 + 1 >= d - r2) {
+ if (q2 >= 0x7FFFFFFF) magu.a = 1;
+ q2 = 2*q2 + 1; // update q2
+ r2 = 2*r2 + 1 - d; // update r2
+ }
+ else {
+ if (q2 >= 0x80000000) magu.a = 1;
+ q2 = 2*q2; // update q2
+ r2 = 2*r2 + 1; // update r2
+ }
+ delta = d - 1 - r2;
+ } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
+ magu.m = q2 + 1; // resulting magic number
+ magu.s = p - 32; // resulting shift
+ return magu;
+}
+
+/// magic - calculate the magic numbers required to codegen an integer sdiv as
+/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
+/// or -1.
+static ms magic64(int64_t d) {
+ int64_t p;
+ uint64_t ad, anc, delta, q1, r1, q2, r2, t;
+ const uint64_t two63 = 9223372036854775808ULL; // 2^63
+ struct ms mag;
+
+ ad = d >= 0 ? d : -d;
+ t = two63 + ((uint64_t)d >> 63);
+ anc = t - 1 - t%ad; // absolute value of nc
+ p = 63; // initialize p
+ q1 = two63/anc; // initialize q1 = 2p/abs(nc)
+ r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
+ q2 = two63/ad; // initialize q2 = 2p/abs(d)
+ r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
+ do {
+ p = p + 1;
+ q1 = 2*q1; // update q1 = 2p/abs(nc)
+ r1 = 2*r1; // update r1 = rem(2p/abs(nc))
+ if (r1 >= anc) { // must be unsigned comparison
+ q1 = q1 + 1;
+ r1 = r1 - anc;
+ }
+ q2 = 2*q2; // update q2 = 2p/abs(d)
+ r2 = 2*r2; // update r2 = rem(2p/abs(d))
+ if (r2 >= ad) { // must be unsigned comparison
+ q2 = q2 + 1;
+ r2 = r2 - ad;
+ }
+ delta = ad - r2;
+ } while (q1 < delta || (q1 == delta && r1 == 0));
+
+ mag.m = q2 + 1;
+ if (d < 0) mag.m = -mag.m; // resulting magic number
+ mag.s = p - 64; // resulting shift
+ return mag;
+}
+
+/// magicu - calculate the magic numbers required to codegen an integer udiv as
+/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
+static mu magicu64(uint64_t d)
+{
+ int64_t p;
+ uint64_t nc, delta, q1, r1, q2, r2;
+ struct mu magu;
+ magu.a = 0; // initialize "add" indicator
+ nc = - 1 - (-d)%d;
+ p = 63; // initialize p
+ q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
+ r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
+ q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
+ r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
+ do {
+ p = p + 1;
+ if (r1 >= nc - r1 ) {
+ q1 = 2*q1 + 1; // update q1
+ r1 = 2*r1 - nc; // update r1
+ }
+ else {
+ q1 = 2*q1; // update q1
+ r1 = 2*r1; // update r1
+ }
+ if (r2 + 1 >= d - r2) {
+ if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
+ q2 = 2*q2 + 1; // update q2
+ r2 = 2*r2 + 1 - d; // update r2
+ }
+ else {
+ if (q2 >= 0x8000000000000000ull) magu.a = 1;
+ q2 = 2*q2; // update q2
+ r2 = 2*r2 + 1; // update r2
+ }
+ delta = d - 1 - r2;
+ } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
+ magu.m = q2 + 1; // resulting magic number
+ magu.s = p - 64; // resulting shift
+ return magu;
}
// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
}
}
+SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
+ MVT::ValueType VT = N0.getValueType();
+ // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
+ // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
+ if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
+ if (isa<ConstantSDNode>(N1)) {
+ SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
+ WorkList.push_back(OpNode.Val);
+ return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
+ } else if (N0.hasOneUse()) {
+ SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
+ WorkList.push_back(OpNode.Val);
+ return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
+ }
+ }
+ // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
+ // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
+ if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
+ if (isa<ConstantSDNode>(N0)) {
+ SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
+ WorkList.push_back(OpNode.Val);
+ return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
+ } else if (N1.hasOneUse()) {
+ SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
+ WorkList.push_back(OpNode.Val);
+ return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
+ }
+ }
+ return SDOperand();
+}
+
void DAGCombiner::Run(bool RunningAfterLegalize) {
// set the instance variable, so that the various visit routines may use it.
AfterLegalize = RunningAfterLegalize;
// Add all the dag nodes to the worklist.
- WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
+ for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+ E = DAG.allnodes_end(); I != E; ++I)
+ WorkList.push_back(I);
// Create a dummy node (which is not added to allnodes), that adds a reference
// to the root node, preventing it from being deleted, and tracking any
case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
case ISD::TRUNCATE: return visitTRUNCATE(N);
+ case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
case ISD::FADD: return visitFADD(N);
case ISD::FSUB: return visitFSUB(N);
case ISD::FMUL: return visitFMUL(N);
case ISD::BR_CC: return visitBR_CC(N);
case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
case ISD::LOAD: return visitLOAD(N);
+ case ISD::STORE: return visitSTORE(N);
}
return SDOperand();
}
SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
+ std::vector<SDOperand> Ops;
+ bool Changed = false;
+
// If the token factor has two operands and one is the entry token, replace
// the token factor with the other operand.
if (N->getNumOperands() == 2) {
if (N->getOperand(1).getOpcode() == ISD::EntryToken)
return N->getOperand(0);
}
+
+ // fold (tokenfactor (tokenfactor)) -> tokenfactor
+ for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
+ SDOperand Op = N->getOperand(i);
+ if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
+ Changed = true;
+ for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
+ Ops.push_back(Op.getOperand(j));
+ } else {
+ Ops.push_back(Op);
+ }
+ }
+ if (Changed)
+ return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
return SDOperand();
}
// fold (add c1, c2) -> c1+c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
+ return DAG.getNode(ISD::ADD, VT, N0, N1);
// canonicalize constant to RHS
- if (N0C && !N1C) {
- std::swap(N0, N1);
- std::swap(N0C, N1C);
- }
+ if (N0C && !N1C)
+ return DAG.getNode(ISD::ADD, VT, N1, N0);
// fold (add x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
- // fold (add (add x, c1), c2) -> (add x, c1+c2)
- if (N1C && N0.getOpcode() == ISD::ADD) {
- ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
- ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
- if (N00C)
- return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
- DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
- if (N01C)
- return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
- DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
- }
+ // fold ((c1-A)+c2) -> (c1+c2)-A
+ if (N1C && N0.getOpcode() == ISD::SUB)
+ if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
+ return DAG.getNode(ISD::SUB, VT,
+ DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
+ N0.getOperand(1));
+ // reassociate add
+ SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
+ if (RADD.Val != 0)
+ return RADD;
// fold ((0-A) + B) -> B-A
if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+ MVT::ValueType VT = N0.getValueType();
+ // fold (sub x, x) -> 0
+ if (N0 == N1)
+ return DAG.getConstant(0, N->getValueType(0));
// fold (sub c1, c2) -> c1-c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() - N1C->getValue(),
- N->getValueType(0));
- // fold (sub x, 0) -> x
- if (N1C && N1C->isNullValue())
- return N0;
+ return DAG.getNode(ISD::SUB, VT, N0, N1);
+ // fold (sub x, c) -> (add x, -c)
+ if (N1C)
+ return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
// fold (A+B)-A -> B
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
return N0.getOperand(1);
// fold (mul c1, c2) -> c1*c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() * N1C->getValue(),
- N->getValueType(0));
+ return DAG.getNode(ISD::MUL, VT, N0, N1);
// canonicalize constant to RHS
- if (N0C && !N1C) {
- std::swap(N0, N1);
- std::swap(N0C, N1C);
- }
+ if (N0C && !N1C)
+ return DAG.getNode(ISD::MUL, VT, N1, N0);
// fold (mul x, 0) -> 0
if (N1C && N1C->isNullValue())
return N1;
// fold (mul x, -1) -> 0-x
if (N1C && N1C->isAllOnesValue())
- return DAG.getNode(ISD::SUB, N->getValueType(0),
- DAG.getConstant(0, N->getValueType(0)), N0);
+ return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
// fold (mul x, (1 << c)) -> x << c
if (N1C && isPowerOf2_64(N1C->getValue()))
- return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
+ return DAG.getNode(ISD::SHL, VT, N0,
DAG.getConstant(Log2_64(N1C->getValue()),
TLI.getShiftAmountTy()));
- // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
- if (N1C && N0.getOpcode() == ISD::MUL) {
- ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
- ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
- if (N00C)
- return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
- DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
- if (N01C)
- return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
- DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
+ // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
+ if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
+ // FIXME: If the input is something that is easily negated (e.g. a
+ // single-use add), we should put the negate there.
+ return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
+ DAG.getNode(ISD::SHL, VT, N0,
+ DAG.getConstant(Log2_64(-N1C->getSignExtended()),
+ TLI.getShiftAmountTy())));
}
+ // reassociate mul
+ SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
+ if (RMUL.Val != 0)
+ return RMUL;
return SDOperand();
}
SDOperand DAGCombiner::visitSDIV(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
- MVT::ValueType VT = N->getValueType(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+ MVT::ValueType VT = N->getValueType(0);
// fold (sdiv c1, c2) -> c1/c2
if (N0C && N1C && !N1C->isNullValue())
- return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
- N->getValueType(0));
+ return DAG.getNode(ISD::SDIV, VT, N0, N1);
+ // fold (sdiv X, 1) -> X
+ if (N1C && N1C->getSignExtended() == 1LL)
+ return N0;
+ // fold (sdiv X, -1) -> 0-X
+ if (N1C && N1C->isAllOnesValue())
+ return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
// If we know the sign bits of both operands are zero, strength reduce to a
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
- if (MaskedValueIsZero(N1, SignBit, TLI) &&
- MaskedValueIsZero(N0, SignBit, TLI))
+ if (TLI.MaskedValueIsZero(N1, SignBit) &&
+ TLI.MaskedValueIsZero(N0, SignBit))
return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
+ // fold (sdiv X, pow2) -> simple ops after legalize
+ if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
+ (isPowerOf2_64(N1C->getSignExtended()) ||
+ isPowerOf2_64(-N1C->getSignExtended()))) {
+ // If dividing by powers of two is cheap, then don't perform the following
+ // fold.
+ if (TLI.isPow2DivCheap())
+ return SDOperand();
+ int64_t pow2 = N1C->getSignExtended();
+ int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
+ unsigned lg2 = Log2_64(abs2);
+ // Splat the sign bit into the register
+ SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
+ DAG.getConstant(MVT::getSizeInBits(VT)-1,
+ TLI.getShiftAmountTy()));
+ WorkList.push_back(SGN.Val);
+ // Add (N0 < 0) ? abs2 - 1 : 0;
+ SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
+ DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
+ TLI.getShiftAmountTy()));
+ SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
+ WorkList.push_back(SRL.Val);
+ WorkList.push_back(ADD.Val); // Divide by pow2
+ SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
+ DAG.getConstant(lg2, TLI.getShiftAmountTy()));
+ // If we're dividing by a positive value, we're done. Otherwise, we must
+ // negate the result.
+ if (pow2 > 0)
+ return SRA;
+ WorkList.push_back(SRA.Val);
+ return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
+ }
+ // if integer divide is expensive and we satisfy the requirements, emit an
+ // alternate sequence.
+ if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
+ !TLI.isIntDivCheap()) {
+ SDOperand Op = BuildSDIV(N);
+ if (Op.Val) return Op;
+ }
return SDOperand();
}
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+ MVT::ValueType VT = N->getValueType(0);
// fold (udiv c1, c2) -> c1/c2
if (N0C && N1C && !N1C->isNullValue())
- return DAG.getConstant(N0C->getValue() / N1C->getValue(),
- N->getValueType(0));
+ return DAG.getNode(ISD::UDIV, VT, N0, N1);
// fold (udiv x, (1 << c)) -> x >>u c
if (N1C && isPowerOf2_64(N1C->getValue()))
- return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
+ return DAG.getNode(ISD::SRL, VT, N0,
DAG.getConstant(Log2_64(N1C->getValue()),
TLI.getShiftAmountTy()));
+ // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
+ if (N1.getOpcode() == ISD::SHL) {
+ if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
+ if (isPowerOf2_64(SHC->getValue())) {
+ MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
+ SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
+ DAG.getConstant(Log2_64(SHC->getValue()),
+ ADDVT));
+ WorkList.push_back(Add.Val);
+ return DAG.getNode(ISD::SRL, VT, N0, Add);
+ }
+ }
+ }
+ // fold (udiv x, c) -> alternate
+ if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
+ SDOperand Op = BuildUDIV(N);
+ if (Op.Val) return Op;
+ }
return SDOperand();
}
SDOperand DAGCombiner::visitSREM(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
- MVT::ValueType VT = N->getValueType(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+ MVT::ValueType VT = N->getValueType(0);
// fold (srem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
- return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
- N->getValueType(0));
+ return DAG.getNode(ISD::SREM, VT, N0, N1);
// If we know the sign bits of both operands are zero, strength reduce to a
// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
- if (MaskedValueIsZero(N1, SignBit, TLI) &&
- MaskedValueIsZero(N0, SignBit, TLI))
- return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1);
+ if (TLI.MaskedValueIsZero(N1, SignBit) &&
+ TLI.MaskedValueIsZero(N0, SignBit))
+ return DAG.getNode(ISD::UREM, VT, N0, N1);
return SDOperand();
}
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+ MVT::ValueType VT = N->getValueType(0);
// fold (urem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
- return DAG.getConstant(N0C->getValue() % N1C->getValue(),
- N->getValueType(0));
+ return DAG.getNode(ISD::UREM, VT, N0, N1);
// fold (urem x, pow2) -> (and x, pow2-1)
if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
- return DAG.getNode(ISD::AND, N0.getValueType(), N0,
- DAG.getConstant(N1C->getValue()-1, N1.getValueType()));
+ return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
+ // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+ if (N1.getOpcode() == ISD::SHL) {
+ if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
+ if (isPowerOf2_64(SHC->getValue())) {
+ SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
+ WorkList.push_back(Add.Val);
+ return DAG.getNode(ISD::AND, VT, N0, Add);
+ }
+ }
+ }
return SDOperand();
}
// fold (and c1, c2) -> c1&c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
+ return DAG.getNode(ISD::AND, VT, N0, N1);
// canonicalize constant to RHS
- if (N0C && !N1C) {
- std::swap(N0, N1);
- std::swap(N0C, N1C);
- }
+ if (N0C && !N1C)
+ return DAG.getNode(ISD::AND, VT, N1, N0);
// fold (and x, -1) -> x
if (N1C && N1C->isAllOnesValue())
return N0;
// if (and x, c) is known to be zero, return 0
- if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
+ if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return DAG.getConstant(0, VT);
- // fold (and x, c) -> x iff (x & ~c) == 0
- if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
- TLI))
- return N0;
- // fold (and (and x, c1), c2) -> (and x, c1^c2)
- if (N1C && N0.getOpcode() == ISD::AND) {
- ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
- ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
- if (N00C)
- return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
- DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
- if (N01C)
- return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
- DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
- }
- // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- unsigned ExtendBits =
- MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
- if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
- return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
- }
+ // reassociate and
+ SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
+ if (RAND.Val != 0)
+ return RAND;
// fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
- if (N0.getOpcode() == ISD::OR)
+ if (N1C && N0.getOpcode() == ISD::OR)
if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
return N1;
+ // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
+ if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
+ unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType());
+ if (TLI.MaskedValueIsZero(N0.getOperand(0),
+ ~N1C->getValue() & ((1ULL << InBits)-1))) {
+ // We actually want to replace all uses of the any_extend with the
+ // zero_extend, to avoid duplicating things. This will later cause this
+ // AND to be folded.
+ CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
+ N0.getOperand(0)));
+ return SDOperand();
+ }
+ }
// fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
WorkList.push_back(ANDNode.Val);
return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
}
- // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
+ // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
- (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
+ (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
+ (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
N0.getOperand(1) == N1.getOperand(1)) {
SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
N0.getOperand(0), N1.getOperand(0));
WorkList.push_back(ANDNode.Val);
return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
}
+ // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
+ // fold (and (sra)) -> (and (srl)) when possible.
+ if (DemandedBitsAreZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
+ return SDOperand();
+ // fold (zext_inreg (extload x)) -> (zextload x)
+ if (N0.getOpcode() == ISD::EXTLOAD) {
+ MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
+ // If we zero all the possible extended bits, then we can turn this into
+ // a zextload if we are running before legalize or the operation is legal.
+ if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
+ (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ EVT);
+ WorkList.push_back(N);
+ CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+ return SDOperand();
+ }
+ }
+ // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
+ if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
+ MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
+ // If we zero all the possible extended bits, then we can turn this into
+ // a zextload if we are running before legalize or the operation is legal.
+ if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
+ (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ EVT);
+ WorkList.push_back(N);
+ CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+ return SDOperand();
+ }
+ }
return SDOperand();
}
// fold (or c1, c2) -> c1|c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() | N1C->getValue(),
- N->getValueType(0));
+ return DAG.getNode(ISD::OR, VT, N0, N1);
// canonicalize constant to RHS
- if (N0C && !N1C) {
- std::swap(N0, N1);
- std::swap(N0C, N1C);
- }
+ if (N0C && !N1C)
+ return DAG.getNode(ISD::OR, VT, N1, N0);
// fold (or x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
if (N1C && N1C->isAllOnesValue())
return N1;
// fold (or x, c) -> c iff (x & ~c) == 0
- if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
- TLI))
+ if (N1C &&
+ TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
return N1;
- // fold (or (or x, c1), c2) -> (or x, c1|c2)
- if (N1C && N0.getOpcode() == ISD::OR) {
- ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
- ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
- if (N00C)
- return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
- DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
- if (N01C)
- return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
- DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
+ // reassociate or
+ SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
+ if (ROR.Val != 0)
+ return ROR;
+ // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
+ if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
+ isa<ConstantSDNode>(N0.getOperand(1))) {
+ ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
+ return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
+ N1),
+ DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
}
// fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
WorkList.push_back(ORNode.Val);
return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
}
+ // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
+ if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
+ (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
+ (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
+ N0.getOperand(1) == N1.getOperand(1)) {
+ SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
+ N0.getOperand(0), N1.getOperand(0));
+ WorkList.push_back(ORNode.Val);
+ return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
+ }
+ // canonicalize shl to left side in a shl/srl pair, to match rotate
+ if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
+ std::swap(N0, N1);
+ // check for rotl, rotr
+ if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
+ N0.getOperand(0) == N1.getOperand(0) &&
+ TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
+ // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
+ if (N0.getOperand(1).getOpcode() == ISD::Constant &&
+ N1.getOperand(1).getOpcode() == ISD::Constant) {
+ uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
+ uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
+ if ((c1val + c2val) == OpSizeInBits)
+ return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
+ }
+ // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
+ if (N1.getOperand(1).getOpcode() == ISD::SUB &&
+ N0.getOperand(1) == N1.getOperand(1).getOperand(1))
+ if (ConstantSDNode *SUBC =
+ dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
+ if (SUBC->getValue() == OpSizeInBits)
+ return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
+ // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
+ if (N0.getOperand(1).getOpcode() == ISD::SUB &&
+ N1.getOperand(1) == N0.getOperand(1).getOperand(1))
+ if (ConstantSDNode *SUBC =
+ dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
+ if (SUBC->getValue() == OpSizeInBits) {
+ if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
+ return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
+ N1.getOperand(1));
+ else
+ return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
+ N0.getOperand(1));
+ }
+ }
return SDOperand();
}
// fold (xor c1, c2) -> c1^c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
+ return DAG.getNode(ISD::XOR, VT, N0, N1);
// canonicalize constant to RHS
- if (N0C && !N1C) {
- std::swap(N0, N1);
- std::swap(N0C, N1C);
- }
+ if (N0C && !N1C)
+ return DAG.getNode(ISD::XOR, VT, N1, N0);
// fold (xor x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
+ // reassociate xor
+ SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
+ if (RXOR.Val != 0)
+ return RXOR;
// fold !(x cc y) -> (x !cc y)
if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
bool isInt = MVT::isInteger(LHS.getValueType());
WorkList.push_back(XORNode.Val);
return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
}
+ // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
+ if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
+ (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
+ (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
+ N0.getOperand(1) == N1.getOperand(1)) {
+ SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
+ N0.getOperand(0), N1.getOperand(0));
+ WorkList.push_back(XORNode.Val);
+ return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
+ }
return SDOperand();
}
// fold (shl c1, c2) -> c1<<c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
+ return DAG.getNode(ISD::SHL, VT, N0, N1);
// fold (shl 0, x) -> 0
if (N0C && N0C->isNullValue())
return N0;
if (N1C && N1C->isNullValue())
return N0;
// if (shl x, c) is known to be zero, return 0
- if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
+ if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return DAG.getConstant(0, VT);
+ if (DemandedBitsAreZero(SDOperand(N,0), MVT::getIntVTBitMask(VT)))
+ return SDOperand();
// fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SHL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT::ValueType VT = N0.getValueType();
- unsigned OpSizeInBits = MVT::getSizeInBits(VT);
// fold (sra c1, c2) -> c1>>c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
+ return DAG.getNode(ISD::SRA, VT, N0, N1);
// fold (sra 0, x) -> 0
if (N0C && N0C->isNullValue())
return N0;
if (N0C && N0C->isAllOnesValue())
return N0;
// fold (sra x, c >= size(x)) -> undef
- if (N1C && N1C->getValue() >= OpSizeInBits)
+ if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
return DAG.getNode(ISD::UNDEF, VT);
// fold (sra x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
+ // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
+ // sext_inreg.
+ if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
+ unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
+ MVT::ValueType EVT;
+ switch (LowBits) {
+ default: EVT = MVT::Other; break;
+ case 1: EVT = MVT::i1; break;
+ case 8: EVT = MVT::i8; break;
+ case 16: EVT = MVT::i16; break;
+ case 32: EVT = MVT::i32; break;
+ }
+ if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
+ DAG.getValueType(EVT));
+ }
// If the sign bit is known to be zero, switch this to a SRL.
- if (N1C && MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
+ if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
return DAG.getNode(ISD::SRL, VT, N0, N1);
return SDOperand();
}
// fold (srl c1, c2) -> c1 >>u c2
if (N0C && N1C)
- return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
+ return DAG.getNode(ISD::SRL, VT, N0, N1);
// fold (srl 0, x) -> 0
if (N0C && N0C->isNullValue())
return N0;
if (N1C && N1C->isNullValue())
return N0;
// if (srl x, c) is known to be zero, return 0
- if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
+ if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
return DAG.getConstant(0, VT);
// fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SRL &&
SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (ctlz c1) -> c2
if (N0C)
- return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
- N0.getValueType());
+ return DAG.getNode(ISD::CTLZ, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (cttz c1) -> c2
if (N0C)
- return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
- N0.getValueType());
+ return DAG.getNode(ISD::CTTZ, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (ctpop c1) -> c2
if (N0C)
- return DAG.getConstant(CountPopulation_64(N0C->getValue()),
- N0.getValueType());
+ return DAG.getNode(ISD::CTPOP, VT, N0);
return SDOperand();
}
// fold X ? Y : X --> X ? Y : 0 --> X & Y
if (MVT::i1 == VT && N0 == N2)
return DAG.getNode(ISD::AND, VT, N0, N1);
+ // If we can fold this based on the true/false value, do so.
+ if (SimplifySelectOps(N, N1, N2))
+ return SDOperand();
// fold selects based on a setcc into other things, such as min/max/abs
if (N0.getOpcode() == ISD::SETCC)
- return SimplifySelect(N0, N1, N2);
+ // FIXME:
+ // Check against MVT::Other for SELECT_CC, which is a workaround for targets
+ // having to say they don't support SELECT_CC on every type the DAG knows
+ // about, since there is no way to mark an opcode illegal at all value types
+ if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
+ return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
+ N1, N2, N0.getOperand(2));
+ else
+ return SimplifySelect(N0, N1, N2);
return SDOperand();
}
// fold select_cc lhs, rhs, x, x, cc -> x
if (N2 == N3)
return N2;
+
+ // If we can fold this based on the true/false value, do so.
+ if (SimplifySelectOps(N, N2, N3))
+ return SDOperand();
+
// fold select_cc into other things, such as min/max/abs
return SimplifySelectCC(N0, N1, N2, N3, CC);
}
// fold (sext c1) -> c1
if (N0C)
- return DAG.getConstant(N0C->getSignExtended(), VT);
+ return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
// fold (sext (sext x)) -> (sext x)
if (N0.getOpcode() == ISD::SIGN_EXTEND)
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
+ // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
+ if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
+ (!AfterLegalize ||
+ TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
+ DAG.getValueType(N0.getValueType()));
+ // fold (sext (load x)) -> (sext (truncate (sextload x)))
+ if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
+ (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ N0.getValueType());
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+ return SDOperand();
+ }
+
+ // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
+ // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
+ if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
+ N0.hasOneUse()) {
+ SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ N0.getOperand(3));
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+ return SDOperand();
+ }
+
return SDOperand();
}
// fold (zext c1) -> c1
if (N0C)
- return DAG.getConstant(N0C->getValue(), VT);
+ return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
// fold (zext (zext x)) -> (zext x)
if (N0.getOpcode() == ISD::ZERO_EXTEND)
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
+ // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
+ if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
+ (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
+ return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
+ // fold (zext (load x)) -> (zext (truncate (zextload x)))
+ if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
+ (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ N0.getValueType());
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+ return SDOperand();
+ }
+
+ // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
+ // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
+ if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
+ N0.hasOneUse()) {
+ SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ N0.getOperand(3));
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ ExtLoad.getValue(1));
+ return SDOperand();
+ }
return SDOperand();
}
}
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
+ cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
return N0;
}
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
TargetLowering::ZeroOrNegativeOneSetCCResult)
return N0;
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
- if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
- return DAG.getNode(ISD::AND, N0.getValueType(), N0,
- DAG.getConstant(~0ULL >> (64-EVTBits), VT));
+ if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
+ return DAG.getZeroExtendInReg(N0, EVT);
// fold (sext_in_reg (srl x)) -> sra x
if (N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant &&
return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
N0.getOperand(1));
}
+ // fold (sext_inreg (extload x)) -> (sextload x)
+ if (N0.getOpcode() == ISD::EXTLOAD &&
+ EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
+ (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ EVT);
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+ return SDOperand();
+ }
+ // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
+ if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
+ EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
+ (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
+ N0.getOperand(1), N0.getOperand(2),
+ EVT);
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+ return SDOperand();
+ }
return SDOperand();
}
return N0;
// fold (truncate c1) -> c1
if (N0C)
- return DAG.getConstant(N0C->getValue(), VT);
+ return DAG.getNode(ISD::TRUNCATE, VT, N0);
// fold (truncate (truncate x)) -> (truncate x)
if (N0.getOpcode() == ISD::TRUNCATE)
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
// and the truncate
return N0.getOperand(0);
}
+ // fold (truncate (load x)) -> (smaller load x)
+ if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
+ assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
+ "Cannot truncate to larger type!");
+ MVT::ValueType PtrType = N0.getOperand(1).getValueType();
+ // For big endian targets, we need to add an offset to the pointer to load
+ // the correct bytes. For little endian systems, we merely need to read
+ // fewer bytes from the same pointer.
+ uint64_t PtrOff =
+ (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
+ SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
+ DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
+ DAG.getConstant(PtrOff, PtrType));
+ WorkList.push_back(NewPtr.Val);
+ SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
+ WorkList.push_back(N);
+ CombineTo(N0.Val, Load, Load.getValue(1));
+ return SDOperand();
+ }
+ return SDOperand();
+}
+
+SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
+ SDOperand N0 = N->getOperand(0);
+ MVT::ValueType VT = N->getValueType(0);
+
+ // If the input is a constant, let getNode() fold it.
+ if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
+ SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
+ if (Res.Val != N) return Res;
+ }
+
+ if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
+ return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
+
+ // fold (conv (load x)) -> (load (conv*)x)
+ // FIXME: These xforms need to know that the resultant load doesn't need a
+ // higher alignment than the original!
+ if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
+ SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
+ N0.getOperand(2));
+ WorkList.push_back(N);
+ CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
+ Load.getValue(1));
+ return Load;
+ }
+
return SDOperand();
}
SDOperand DAGCombiner::visitFADD(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT::ValueType VT = N->getValueType(0);
-
- if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
- if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
- // fold floating point (fadd c1, c2)
- return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(),
- N->getValueType(0));
- }
+
+ // fold (fadd c1, c2) -> c1+c2
+ if (N0CFP && N1CFP)
+ return DAG.getNode(ISD::FADD, VT, N0, N1);
+ // canonicalize constant to RHS
+ if (N0CFP && !N1CFP)
+ return DAG.getNode(ISD::FADD, VT, N1, N0);
// fold (A + (-B)) -> A-B
if (N1.getOpcode() == ISD::FNEG)
return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
-
// fold ((-A) + B) -> B-A
if (N0.getOpcode() == ISD::FNEG)
return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
-
return SDOperand();
}
SDOperand DAGCombiner::visitFSUB(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT::ValueType VT = N->getValueType(0);
-
- if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
- if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
- // fold floating point (fsub c1, c2)
- return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(),
- N->getValueType(0));
- }
+
+ // fold (fsub c1, c2) -> c1-c2
+ if (N0CFP && N1CFP)
+ return DAG.getNode(ISD::FSUB, VT, N0, N1);
// fold (A-(-B)) -> A+B
if (N1.getOpcode() == ISD::FNEG)
- return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0));
-
+ return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
return SDOperand();
}
SDOperand DAGCombiner::visitFMUL(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT::ValueType VT = N->getValueType(0);
- if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
- if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
- // fold floating point (fmul c1, c2)
- return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(),
- N->getValueType(0));
- }
+ // fold (fmul c1, c2) -> c1*c2
+ if (N0CFP && N1CFP)
+ return DAG.getNode(ISD::FMUL, VT, N0, N1);
+ // canonicalize constant to RHS
+ if (N0CFP && !N1CFP)
+ return DAG.getNode(ISD::FMUL, VT, N1, N0);
+ // fold (fmul X, 2.0) -> (fadd X, X)
+ if (N1CFP && N1CFP->isExactlyValue(+2.0))
+ return DAG.getNode(ISD::FADD, VT, N0, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitFDIV(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT::ValueType VT = N->getValueType(0);
- if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
- if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
- // fold floating point (fdiv c1, c2)
- return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(),
- N->getValueType(0));
- }
+ // fold (fdiv c1, c2) -> c1/c2
+ if (N0CFP && N1CFP)
+ return DAG.getNode(ISD::FDIV, VT, N0, N1);
return SDOperand();
}
SDOperand DAGCombiner::visitFREM(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
MVT::ValueType VT = N->getValueType(0);
- if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
- if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
- // fold floating point (frem c1, c2) -> fmod(c1, c2)
- return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()),
- N->getValueType(0));
- }
+ // fold (frem c1, c2) -> fmod(c1,c2)
+ if (N0CFP && N1CFP)
+ return DAG.getNode(ISD::FREM, VT, N0, N1);
return SDOperand();
}
SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (sint_to_fp c1) -> c1fp
if (N0C)
- return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
+ return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
-
+ MVT::ValueType VT = N->getValueType(0);
+
// fold (uint_to_fp c1) -> c1fp
if (N0C)
- return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
+ return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
- ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (fp_to_sint c1fp) -> c1
if (N0CFP)
- return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
+ return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
- ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (fp_to_uint c1fp) -> c1
if (N0CFP)
- return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
+ return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
- ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (fp_round c1fp) -> c1fp
if (N0CFP)
- return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
+ return DAG.getNode(ISD::FP_ROUND, VT, N0);
return SDOperand();
}
}
SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
- ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
// fold (fp_extend c1fp) -> c1fp
if (N0CFP)
- return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
+ return DAG.getNode(ISD::FP_EXTEND, VT, N0);
return SDOperand();
}
SDOperand DAGCombiner::visitFNEG(SDNode *N) {
- ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
- // fold (neg c1) -> -c1
+ SDOperand N0 = N->getOperand(0);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
+
+ // fold (fneg c1) -> -c1
if (N0CFP)
- return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
- // fold (neg (sub x, y)) -> (sub y, x)
+ return DAG.getNode(ISD::FNEG, VT, N0);
+ // fold (fneg (sub x, y)) -> (sub y, x)
if (N->getOperand(0).getOpcode() == ISD::SUB)
- return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
- N->getOperand(0));
- // fold (neg (neg x)) -> x
+ return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
+ // fold (fneg (fneg x)) -> x
if (N->getOperand(0).getOpcode() == ISD::FNEG)
return N->getOperand(0).getOperand(0);
return SDOperand();
}
SDOperand DAGCombiner::visitFABS(SDNode *N) {
- ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
+ SDOperand N0 = N->getOperand(0);
+ ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
+ MVT::ValueType VT = N->getValueType(0);
+
// fold (fabs c1) -> fabs(c1)
if (N0CFP)
- return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
+ return DAG.getNode(ISD::FABS, VT, N0);
// fold (fabs (fabs x)) -> (fabs x)
if (N->getOperand(0).getOpcode() == ISD::FABS)
return N->getOperand(0);
// fold (fabs (fneg x)) -> (fabs x)
if (N->getOperand(0).getOpcode() == ISD::FNEG)
- return DAG.getNode(ISD::FABS, N->getValueType(0),
- N->getOperand(0).getOperand(0));
+ return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
return SDOperand();
}
// unconditional branch
if (N1C && N1C->getValue() == 1)
return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
+ // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
+ // on the target.
+ if (N1.getOpcode() == ISD::SETCC &&
+ TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
+ return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
+ N1.getOperand(0), N1.getOperand(1), N2);
+ }
return SDOperand();
}
// unconditional branch to false mbb
if (N1C && N1C->isNullValue())
return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
+ // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
+ // BRTWOWAY_CC is legal on the target.
+ if (N1.getOpcode() == ISD::SETCC &&
+ TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(N1.getOperand(2));
+ Ops.push_back(N1.getOperand(0));
+ Ops.push_back(N1.getOperand(1));
+ Ops.push_back(N2);
+ Ops.push_back(N3);
+ return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
+ }
return SDOperand();
}
if (SCCC && SCCC->isNullValue())
return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
// fold to a simpler setcc
- if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
- return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
- SCC.getOperand(1), N4, N5);
+ if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(SCC.getOperand(2));
+ Ops.push_back(SCC.getOperand(0));
+ Ops.push_back(SCC.getOperand(1));
+ Ops.push_back(N4);
+ Ops.push_back(N5);
+ return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
+ }
return SDOperand();
}
return SDOperand();
}
+SDOperand DAGCombiner::visitSTORE(SDNode *N) {
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Value = N->getOperand(1);
+ SDOperand Ptr = N->getOperand(2);
+ SDOperand SrcValue = N->getOperand(3);
+
+ // If this is a store that kills a previous store, remove the previous store.
+ if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
+ Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
+ // Make sure that these stores are the same value type:
+ // FIXME: we really care that the second store is >= size of the first.
+ Value.getValueType() == Chain.getOperand(1).getValueType()) {
+ // Create a new store of Value that replaces both stores.
+ SDNode *PrevStore = Chain.Val;
+ if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
+ return Chain;
+ SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
+ PrevStore->getOperand(0), Value, Ptr,
+ SrcValue);
+ CombineTo(N, NewStore); // Nuke this store.
+ CombineTo(PrevStore, NewStore); // Nuke the previous store.
+ return SDOperand(N, 0);
+ }
+
+ // If this is a store of a bit convert, store the input value.
+ // FIXME: This needs to know that the resultant store does not need a
+ // higher alignment than the original.
+ if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
+ return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
+ Ptr, SrcValue);
+
+ return SDOperand();
+}
+
SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
return SDOperand();
}
+/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
+/// are the two values being selected between, see if we can simplify the
+/// select.
+///
+bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
+ SDOperand RHS) {
+
+ // If this is a select from two identical things, try to pull the operation
+ // through the select.
+ if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
+#if 0
+ std::cerr << "SELECT: ["; LHS.Val->dump();
+ std::cerr << "] ["; RHS.Val->dump();
+ std::cerr << "]\n";
+#endif
+
+ // If this is a load and the token chain is identical, replace the select
+ // of two loads with a load through a select of the address to load from.
+ // This triggers in things like "select bool X, 10.0, 123.0" after the FP
+ // constants have been dropped into the constant pool.
+ if ((LHS.getOpcode() == ISD::LOAD ||
+ LHS.getOpcode() == ISD::EXTLOAD ||
+ LHS.getOpcode() == ISD::ZEXTLOAD ||
+ LHS.getOpcode() == ISD::SEXTLOAD) &&
+ // Token chains must be identical.
+ LHS.getOperand(0) == RHS.getOperand(0) &&
+ // If this is an EXTLOAD, the VT's must match.
+ (LHS.getOpcode() == ISD::LOAD ||
+ LHS.getOperand(3) == RHS.getOperand(3))) {
+ // FIXME: this conflates two src values, discarding one. This is not
+ // the right thing to do, but nothing uses srcvalues now. When they do,
+ // turn SrcValue into a list of locations.
+ SDOperand Addr;
+ if (TheSelect->getOpcode() == ISD::SELECT)
+ Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
+ TheSelect->getOperand(0), LHS.getOperand(1),
+ RHS.getOperand(1));
+ else
+ Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
+ TheSelect->getOperand(0),
+ TheSelect->getOperand(1),
+ LHS.getOperand(1), RHS.getOperand(1),
+ TheSelect->getOperand(4));
+
+ SDOperand Load;
+ if (LHS.getOpcode() == ISD::LOAD)
+ Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
+ Addr, LHS.getOperand(2));
+ else
+ Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
+ LHS.getOperand(0), Addr, LHS.getOperand(2),
+ cast<VTSDNode>(LHS.getOperand(3))->getVT());
+ // Users of the select now use the result of the load.
+ CombineTo(TheSelect, Load);
+
+ // Users of the old loads now use the new load's chain. We know the
+ // old-load value is dead now.
+ CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
+ CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
+ return true;
+ }
+ }
+
+ return false;
+}
+
SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
SDOperand N2, SDOperand N3,
ISD::CondCode CC) {
DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
ExtDstTy),
Cond);
+ } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
+ (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+ (N0.getOpcode() == ISD::XOR ||
+ (N0.getOpcode() == ISD::AND &&
+ N0.getOperand(0).getOpcode() == ISD::XOR &&
+ N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
+ isa<ConstantSDNode>(N0.getOperand(1)) &&
+ cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
+ // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
+ // only do this if the top bits are known zero.
+ if (TLI.MaskedValueIsZero(N1,
+ MVT::getIntVTBitMask(N0.getValueType())-1)) {
+ // Okay, get the un-inverted input value.
+ SDOperand Val;
+ if (N0.getOpcode() == ISD::XOR)
+ Val = N0.getOperand(0);
+ else {
+ assert(N0.getOpcode() == ISD::AND &&
+ N0.getOperand(0).getOpcode() == ISD::XOR);
+ // ((X^1)&1)^1 -> X & 1
+ Val = DAG.getNode(ISD::AND, N0.getValueType(),
+ N0.getOperand(0).getOperand(0), N0.getOperand(1));
+ }
+ return DAG.getSetCC(VT, Val, N1,
+ Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
+ }
}
uint64_t MinVal, MaxVal;
// Canonicalize setgt X, Min --> setne X, Min
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
+ // Canonicalize setlt X, Max --> setne X, Max
+ if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
+ return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
// If we have setult X, 1, turn it into seteq X, 0
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
return DAG.getConstant(UOF, VT);
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
// if it is not already.
- ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
+ ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
if (NewCond != Cond)
return DAG.getSetCC(VT, N0, N1, NewCond);
}
if (N0.getOperand(0) == N1.getOperand(1))
return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
if (N0.getOperand(1) == N1.getOperand(0))
- return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
+ return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
}
}
-
- // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
- if (N0.getOpcode() == ISD::XOR)
- if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
- if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
+
+ if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
+ if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+ // Turn (X+C1) == C2 --> X == C2-C1
+ if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
+ return DAG.getSetCC(VT, N0.getOperand(0),
+ DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
+ N0.getValueType()), Cond);
+ }
+
+ // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
+ if (N0.getOpcode() == ISD::XOR)
// If we know that all of the inverted bits are zero, don't bother
// performing the inversion.
- if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
+ if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
return DAG.getSetCC(VT, N0.getOperand(0),
- DAG.getConstant(XORC->getValue()^RHSC->getValue(),
+ DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
N0.getValueType()), Cond);
+ }
+
+ // Turn (C1-X) == C2 --> X == C1-C2
+ if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
+ if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
+ return DAG.getSetCC(VT, N0.getOperand(1),
+ DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
+ N0.getValueType()), Cond);
}
-
+ }
+ }
+
// Simplify (X+Z) == X --> Z == 0
if (N0.getOperand(0) == N1)
return DAG.getSetCC(VT, N0.getOperand(1),
return SDOperand();
}
+/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
+/// return a DAG expression to select that will generate the same value by
+/// multiplying by a magic number. See:
+/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
+SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
+ MVT::ValueType VT = N->getValueType(0);
+
+ // Check to see if we can do this.
+ if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
+ return SDOperand(); // BuildSDIV only operates on i32 or i64
+ if (!TLI.isOperationLegal(ISD::MULHS, VT))
+ return SDOperand(); // Make sure the target supports MULHS.
+
+ int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
+ ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
+
+ // Multiply the numerator (operand 0) by the magic value
+ SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
+ DAG.getConstant(magics.m, VT));
+ // If d > 0 and m < 0, add the numerator
+ if (d > 0 && magics.m < 0) {
+ Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
+ WorkList.push_back(Q.Val);
+ }
+ // If d < 0 and m > 0, subtract the numerator.
+ if (d < 0 && magics.m > 0) {
+ Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
+ WorkList.push_back(Q.Val);
+ }
+ // Shift right algebraic if shift value is nonzero
+ if (magics.s > 0) {
+ Q = DAG.getNode(ISD::SRA, VT, Q,
+ DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
+ WorkList.push_back(Q.Val);
+ }
+ // Extract the sign bit and add it to the quotient
+ SDOperand T =
+ DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
+ TLI.getShiftAmountTy()));
+ WorkList.push_back(T.Val);
+ return DAG.getNode(ISD::ADD, VT, Q, T);
+}
+
+/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
+/// return a DAG expression to select that will generate the same value by
+/// multiplying by a magic number. See:
+/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
+SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
+ MVT::ValueType VT = N->getValueType(0);
+
+ // Check to see if we can do this.
+ if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
+ return SDOperand(); // BuildUDIV only operates on i32 or i64
+ if (!TLI.isOperationLegal(ISD::MULHU, VT))
+ return SDOperand(); // Make sure the target supports MULHU.
+
+ uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
+
+ // Multiply the numerator (operand 0) by the magic value
+ SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
+ DAG.getConstant(magics.m, VT));
+ WorkList.push_back(Q.Val);
+
+ if (magics.a == 0) {
+ return DAG.getNode(ISD::SRL, VT, Q,
+ DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
+ } else {
+ SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
+ WorkList.push_back(NPQ.Val);
+ NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
+ DAG.getConstant(1, TLI.getShiftAmountTy()));
+ WorkList.push_back(NPQ.Val);
+ NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
+ WorkList.push_back(NPQ.Val);
+ return DAG.getNode(ISD::SRL, VT, NPQ,
+ DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
+ }
+}
+
// SelectionDAG::Combine - This is the entry point for the file.
//
void SelectionDAG::Combine(bool RunningAfterLegalize) {
projects / oota-llvm.git / blobdiff