Rename APFloat::convertToAPInt to bitcastToAPInt to

[oota-llvm.git] / lib / CodeGen / SelectionDAG / DAGCombiner.cpp

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d79dc7a3b58bb106f61455cba3868ddecf2784ab..c774c6878d1fd2ff8013996881a5a0729d96a72d 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -960,7 +960,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
     return N1;
   // fold (add c1, c2) -> c1+c2
   if (N0C && N1C)
-    return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT);
+    return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::ADD, VT, N1, N0);
@@ -1111,7 +1111,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
     return DAG.getConstant(0, N->getValueType(0));
   // fold (sub c1, c2) -> c1-c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SUB, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
   // fold (sub x, c) -> (add x, -c)
   if (N1C)
     return DAG.getNode(ISD::ADD, VT, N0,
@@ -1154,7 +1154,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
     return DAG.getConstant(0, VT);
   // fold (mul c1, c2) -> c1*c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::MUL, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::MUL, VT, N1, N0);
@@ -1170,12 +1170,12 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
                        DAG.getConstant(N1C->getAPIntValue().logBase2(),
                                        TLI.getShiftAmountTy()));
   // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
-  if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
+  if (N1C && isPowerOf2_64(-N1C->getSExtValue())) {
     // FIXME: If the input is something that is easily negated (e.g. a 
     // single-use add), we should put the negate there.
     return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
                        DAG.getNode(ISD::SHL, VT, N0,
-                            DAG.getConstant(Log2_64(-N1C->getSignExtended()),
+                            DAG.getConstant(Log2_64(-N1C->getSExtValue()),
                                             TLI.getShiftAmountTy())));
   }
 
@@ -1236,9 +1236,9 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
   
   // fold (sdiv c1, c2) -> c1/c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::SDIV, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
   // fold (sdiv X, 1) -> X
-  if (N1C && N1C->getSignExtended() == 1LL)
+  if (N1C && N1C->getSExtValue() == 1LL)
     return N0;
   // fold (sdiv X, -1) -> 0-X
   if (N1C && N1C->isAllOnesValue())
@@ -1251,13 +1251,13 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
   }
   // fold (sdiv X, pow2) -> simple ops after legalize
   if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
-      (isPowerOf2_64(N1C->getSignExtended()) || 
-       isPowerOf2_64(-N1C->getSignExtended()))) {
+      (isPowerOf2_64(N1C->getSExtValue()) || 
+       isPowerOf2_64(-N1C->getSExtValue()))) {
     // If dividing by powers of two is cheap, then don't perform the following
     // fold.
     if (TLI.isPow2DivCheap())
       return SDValue();
-    int64_t pow2 = N1C->getSignExtended();
+    int64_t pow2 = N1C->getSExtValue();
     int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
     unsigned lg2 = Log2_64(abs2);
     // Splat the sign bit into the register
@@ -1283,7 +1283,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
   }
   // if integer divide is expensive and we satisfy the requirements, emit an
   // alternate sequence.
-  if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 
+  if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 
       !TLI.isIntDivCheap()) {
     SDValue Op = BuildSDIV(N);
     if (Op.getNode()) return Op;
@@ -1314,7 +1314,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
   
   // fold (udiv c1, c2) -> c1/c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::UDIV, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
   // fold (udiv x, (1 << c)) -> x >>u c
   if (N1C && N1C->getAPIntValue().isPowerOf2())
     return DAG.getNode(ISD::SRL, VT, N0, 
@@ -1359,7 +1359,7 @@ SDValue DAGCombiner::visitSREM(SDNode *N) {
   
   // fold (srem c1, c2) -> c1%c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::SREM, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
   // If we know the sign bits of both operands are zero, strength reduce to a
   // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
   if (!VT.isVector()) {
@@ -1400,7 +1400,7 @@ SDValue DAGCombiner::visitUREM(SDNode *N) {
   
   // fold (urem c1, c2) -> c1%c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::UREM, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
   // fold (urem x, pow2) -> (and x, pow2-1)
   if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
     return DAG.getNode(ISD::AND, VT, N0,
@@ -1625,7 +1625,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
     return DAG.getConstant(0, VT);
   // fold (and c1, c2) -> c1&c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::AND, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::AND, VT, N1, N0);
@@ -1824,7 +1824,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
     return DAG.getConstant(~0ULL, VT);
   // fold (or c1, c2) -> c1|c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::OR, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::OR, VT, N1, N0);
@@ -2117,7 +2117,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
     return N1;
   // fold (xor c1, c2) -> c1^c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::XOR, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::XOR, VT, N1, N0);
@@ -2295,7 +2295,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   
   // fold (shl c1, c2) -> c1<<c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SHL, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
   // fold (shl 0, x) -> 0
   if (N0C && N0C->isNullValue())
     return N0;
@@ -2312,21 +2312,17 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c))
   // iff (trunc c) == c
   if (N1.getOpcode() == ISD::TRUNCATE &&
-      N1.getOperand(0).getOpcode() == ISD::AND) {
+      N1.getOperand(0).getOpcode() == ISD::AND &&
+      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
     SDValue N101 = N1.getOperand(0).getOperand(1);
-    ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101);
-    if (N101C) {
+    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
       MVT TruncVT = N1.getValueType();
-      unsigned TruncBitSize = TruncVT.getSizeInBits();
-      APInt ShAmt = N101C->getAPIntValue();
-      if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) {
-        SDValue N100 = N1.getOperand(0).getOperand(0);
-        return DAG.getNode(ISD::SHL, VT, N0,
-                           DAG.getNode(ISD::AND, TruncVT,
-                                  DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
-                                  DAG.getConstant(N101C->getZExtValue(),
-                                                  TruncVT)));
-      }
+      SDValue N100 = N1.getOperand(0).getOperand(0);
+      return DAG.getNode(ISD::SHL, VT, N0,
+                         DAG.getNode(ISD::AND, TruncVT,
+                                     DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
+                                     DAG.getConstant(N101C->getZExtValue(),
+                                                     TruncVT)));
     }
   }
 
@@ -2374,7 +2370,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   
   // fold (sra c1, c2) -> c1>>c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SRA, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
   // fold (sra 0, x) -> 0
   if (N0C && N0C->isNullValue())
     return N0;
@@ -2444,21 +2440,17 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c))
   // iff (trunc c) == c
   if (N1.getOpcode() == ISD::TRUNCATE &&
-      N1.getOperand(0).getOpcode() == ISD::AND) {
+      N1.getOperand(0).getOpcode() == ISD::AND &&
+      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
     SDValue N101 = N1.getOperand(0).getOperand(1);
-    ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101);
-    if (N101C) {
+    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
       MVT TruncVT = N1.getValueType();
-      unsigned TruncBitSize = TruncVT.getSizeInBits();
-      APInt ShAmt = N101C->getAPIntValue();
-      if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) {
-        SDValue N100 = N1.getOperand(0).getOperand(0);
-        return DAG.getNode(ISD::SRA, VT, N0,
-                           DAG.getNode(ISD::AND, TruncVT,
-                                  DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
-                                  DAG.getConstant(N101C->getZExtValue(),
-                                                  TruncVT)));
-      }
+      SDValue N100 = N1.getOperand(0).getOperand(0);
+      return DAG.getNode(ISD::SRA, VT, N0,
+                         DAG.getNode(ISD::AND, TruncVT,
+                                     DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
+                                     DAG.getConstant(N101C->getZExtValue(),
+                                                     TruncVT)));
     }
   }
 
@@ -2484,7 +2476,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
   
   // fold (srl c1, c2) -> c1 >>u c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SRL, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
   // fold (srl 0, x) -> 0
   if (N0C && N0C->isNullValue())
     return N0;
@@ -2565,21 +2557,17 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
   // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
   // iff (trunc c) == c
   if (N1.getOpcode() == ISD::TRUNCATE &&
-      N1.getOperand(0).getOpcode() == ISD::AND) {
+      N1.getOperand(0).getOpcode() == ISD::AND &&
+      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
     SDValue N101 = N1.getOperand(0).getOperand(1);
-    ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101);
-    if (N101C) {
+    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
       MVT TruncVT = N1.getValueType();
-      unsigned TruncBitSize = TruncVT.getSizeInBits();
-      APInt ShAmt = N101C->getAPIntValue();
-      if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) {
-        SDValue N100 = N1.getOperand(0).getOperand(0);
-        return DAG.getNode(ISD::SRL, VT, N0,
-                           DAG.getNode(ISD::AND, TruncVT,
-                                  DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
-                                  DAG.getConstant(N101C->getZExtValue(),
-                                                  TruncVT)));
-      }
+      SDValue N100 = N1.getOperand(0).getOperand(0);
+      return DAG.getNode(ISD::SRL, VT, N0,
+                         DAG.getNode(ISD::AND, TruncVT,
+                                     DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
+                                     DAG.getConstant(N101C->getZExtValue(),
+                                                     TruncVT)));
     }
   }
   
@@ -4021,7 +4009,7 @@ SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
   
   // fold (fp_round_inreg c1fp) -> c1fp
   if (N0CFP) {
-    SDValue Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
+    SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
     return DAG.getNode(ISD::FP_EXTEND, VT, Round);
   }
   return SDValue();
@@ -4642,7 +4630,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
         if ((!AfterLegalize && !ST->isVolatile()) ||
             TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
           Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
-                              convertToAPInt().getZExtValue(), MVT::i32);
+                              bitcastToAPInt().getZExtValue(), MVT::i32);
           return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
                               ST->getSrcValueOffset(), ST->isVolatile(),
                               ST->getAlignment());
@@ -4651,7 +4639,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
       case MVT::f64:
         if ((!AfterLegalize && !ST->isVolatile()) ||
             TLI.isOperationLegal(ISD::STORE, MVT::i64)) {
-          Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
+          Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
                                   getZExtValue(), MVT::i64);
           return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
                               ST->getSrcValueOffset(), ST->isVolatile(),
@@ -4661,7 +4649,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
           // Many FP stores are not made apparent until after legalize, e.g. for
           // argument passing.  Since this is so common, custom legalize the
           // 64-bit integer store into two 32-bit stores.
-          uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
+          uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
           SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
           SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
           if (TLI.isBigEndian()) std::swap(Lo, Hi);