Added ARM::mls for armv6t2.

[oota-llvm.git] / lib / CodeGen / ScheduleDAG.cpp

diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp
index e309a4385e4570bfc412cc8095619bb7c6956e20..a8452dff272b8d741898d56d76efcb4c8b9d9c0f 100644 (file)
--- a/lib/CodeGen/ScheduleDAG.cpp
+++ b/lib/CodeGen/ScheduleDAG.cpp
@@ -23,12 +23,13 @@
 using namespace llvm;
 
 ScheduleDAG::ScheduleDAG(MachineFunction &mf)
-  : DAG(0), BB(0), TM(mf.getTarget()),
+  : TM(mf.getTarget()),
     TII(TM.getInstrInfo()),
     TRI(TM.getRegisterInfo()),
     TLI(TM.getTargetLowering()),
     MF(mf), MRI(mf.getRegInfo()),
-    ConstPool(MF.getConstantPool()) {
+    ConstPool(MF.getConstantPool()),
+    EntrySU(), ExitSU() {
 }
 
 ScheduleDAG::~ScheduleDAG() {}
@@ -46,14 +47,18 @@ void ScheduleDAG::dumpSchedule() const {
 
 /// Run - perform scheduling.
 ///
-void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
+void ScheduleDAG::Run(MachineBasicBlock *bb,
+                      MachineBasicBlock::iterator insertPos) {
+  BB = bb;
+  InsertPos = insertPos;
+
   SUnits.clear();
   Sequence.clear();
-  DAG = dag;
-  BB = bb;
+  EntrySU = SUnit();
+  ExitSU = SUnit();
 
   Schedule();
-  
+
   DOUT << "*** Final schedule ***\n";
   DEBUG(dumpSchedule());
   DOUT << "\n";
@@ -64,8 +69,9 @@ void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
 /// specified node.
 void SUnit::addPred(const SDep &D) {
   // If this node already has this depenence, don't add a redundant one.
-  for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
-    if (Preds[i] == D)
+  for (SmallVector<SDep, 4>::const_iterator I = Preds.begin(), E = Preds.end();
+       I != E; ++I)
+    if (*I == D)
       return;
   // Now add a corresponding succ to N.
   SDep P = D;