using namespace llvm;
ScheduleDAG::ScheduleDAG(MachineFunction &mf)
- : DAG(0), BB(0), TM(mf.getTarget()),
+ : TM(mf.getTarget()),
TII(TM.getInstrInfo()),
TRI(TM.getRegisterInfo()),
TLI(TM.getTargetLowering()),
MF(mf), MRI(mf.getRegInfo()),
- ConstPool(MF.getConstantPool()) {
+ ConstPool(MF.getConstantPool()),
+ EntrySU(), ExitSU() {
}
ScheduleDAG::~ScheduleDAG() {}
/// Run - perform scheduling.
///
-void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb,
- MachineBasicBlock::iterator begin,
- MachineBasicBlock::iterator end) {
- assert((!dag || begin == end) &&
- "An instruction range was given for SelectionDAG scheduling!");
+void ScheduleDAG::Run(MachineBasicBlock *bb,
+ MachineBasicBlock::iterator insertPos) {
+ BB = bb;
+ InsertPos = insertPos;
SUnits.clear();
Sequence.clear();
- DAG = dag;
- BB = bb;
- Begin = begin;
- End = end;
+ EntrySU = SUnit();
+ ExitSU = SUnit();
Schedule();
-
+
DOUT << "*** Final schedule ***\n";
DEBUG(dumpSchedule());
DOUT << "\n";
/// specified node.
void SUnit::addPred(const SDep &D) {
// If this node already has this depenence, don't add a redundant one.
- for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
- if (Preds[i] == D)
+ for (SmallVector<SDep, 4>::const_iterator I = Preds.begin(), E = Preds.end();
+ I != E; ++I)
+ if (*I == D)
return;
// Now add a corresponding succ to N.
SDep P = D;