Avoid unnecessarily casting away const.

[oota-llvm.git] / lib / CodeGen / RegisterScavenging.cpp

diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index d73dd3d757e44ea1cf3c20acaef12dd04bf5fc86..aeed72cef52e955f6f97d5044d6faabaf00de54f 100644 (file)
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the Evan Cheng and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -36,7 +36,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
 
   if (!MBB) {
     NumPhysRegs = RegInfo->getNumRegs();
-    RegStates.resize(NumPhysRegs);
+    RegsAvailable.resize(NumPhysRegs);
 
     // Create reserved registers bitvector.
     ReservedRegs = RegInfo->getReservedRegs(MF);
@@ -54,10 +54,10 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
   ScavengedRC = NULL;
 
   // All registers started out unused.
-  RegStates.set();
+  RegsAvailable.set();
 
   // Reserved registers are always used.
-  RegStates ^= ReservedRegs;
+  RegsAvailable ^= ReservedRegs;
 
   // Live-in registers are in use.
   if (!MBB->livein_empty())
@@ -72,10 +72,10 @@ void RegScavenger::restoreScavengedReg() {
   if (!ScavengedReg)
     return;
 
-  RegInfo->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
+  TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
                                 ScavengingFrameIndex, ScavengedRC);
   MachineBasicBlock::iterator II = prior(MBBI);
-  RegInfo->eliminateFrameIndex(II, this);
+  RegInfo->eliminateFrameIndex(II, 0, this);
   setUsed(ScavengedReg);
   ScavengedReg = 0;
   ScavengedRC = NULL;
@@ -92,17 +92,18 @@ void RegScavenger::forward() {
   }
 
   MachineInstr *MI = MBBI;
+  const TargetInstrDesc &TID = MI->getDesc();
 
   // Reaching a terminator instruction. Restore a scavenged register (which
   // must be life out.
-  if (TII->isTerminatorInstr(MI->getOpcode()))
+  if (TID.isTerminator())
     restoreScavengedReg();
 
   // Process uses first.
   BitVector ChangedRegs(NumPhysRegs);
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isUse())
+    if (!MO.isRegister() || !MO.isUse())
       continue;
     unsigned Reg = MO.getReg();
     if (Reg == 0)
@@ -110,7 +111,7 @@ void RegScavenger::forward() {
     if (!isUsed(Reg)) {
       // Register has been scavenged. Restore it!
       if (Reg != ScavengedReg)
-        assert(false);
+        assert(false && "Using an undefined register!");
       else
         restoreScavengedReg();
     }
@@ -122,10 +123,9 @@ void RegScavenger::forward() {
   setUnused(ChangedRegs);
 
   // Process defs.
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isDef())
+    if (!MO.isRegister() || !MO.isDef())
       continue;
     unsigned Reg = MO.getReg();
     // If it's dead upon def, then it is now free.
@@ -134,11 +134,12 @@ void RegScavenger::forward() {
       continue;
     }
     // Skip two-address destination operand.
-    if (TID->findTiedToSrcOperand(i) != -1) {
-      assert(isUsed(Reg));
+    if (TID.findTiedToSrcOperand(i) != -1) {
+      assert(isUsed(Reg) && "Using an undefined register!");
       continue;
     }
-    assert(isUnused(Reg) || isReserved(Reg));
+    assert((isUnused(Reg) || isReserved(Reg)) &&
+           "Re-defining a live register!");
     setUsed(Reg);
   }
 }
@@ -151,13 +152,13 @@ void RegScavenger::backward() {
 
   MachineInstr *MI = MBBI;
   // Process defs first.
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  const TargetInstrDesc &TID = MI->getDesc();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isDef())
+    if (!MO.isRegister() || !MO.isDef())
       continue;
     // Skip two-address destination operand.
-    if (TID->findTiedToSrcOperand(i) != -1)
+    if (TID.findTiedToSrcOperand(i) != -1)
       continue;
     unsigned Reg = MO.getReg();
     assert(isUsed(Reg));
@@ -169,7 +170,7 @@ void RegScavenger::backward() {
   BitVector ChangedRegs(NumPhysRegs);
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isUse())
+    if (!MO.isRegister() || !MO.isUse())
       continue;
     unsigned Reg = MO.getReg();
     if (Reg == 0)
@@ -180,6 +181,13 @@ void RegScavenger::backward() {
   setUsed(ChangedRegs);
 }
 
+void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
+  if (includeReserved)
+    used = ~RegsAvailable;
+  else
+    used = ~RegsAvailable & ~ReservedRegs;
+}
+
 /// CreateRegClassMask - Set the bits that represent the registers in the
 /// TargetRegisterClass.
 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
@@ -191,32 +199,32 @@ static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
                                      const BitVector &Candidates) const {
   // Mask off the registers which are not in the TargetRegisterClass.
-  BitVector RegStatesCopy(NumPhysRegs, false);
-  CreateRegClassMask(RegClass, RegStatesCopy);
-  RegStatesCopy &= RegStates;
+  BitVector RegsAvailableCopy(NumPhysRegs, false);
+  CreateRegClassMask(RegClass, RegsAvailableCopy);
+  RegsAvailableCopy &= RegsAvailable;
 
   // Restrict the search to candidates.
-  RegStatesCopy &= Candidates;
+  RegsAvailableCopy &= Candidates;
 
   // Returns the first unused (bit is set) register, or 0 is none is found.
-  int Reg = RegStatesCopy.find_first();
+  int Reg = RegsAvailableCopy.find_first();
   return (Reg == -1) ? 0 : Reg;
 }
 
 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
                                      bool ExCalleeSaved) const {
   // Mask off the registers which are not in the TargetRegisterClass.
-  BitVector RegStatesCopy(NumPhysRegs, false);
-  CreateRegClassMask(RegClass, RegStatesCopy);
-  RegStatesCopy &= RegStates;
+  BitVector RegsAvailableCopy(NumPhysRegs, false);
+  CreateRegClassMask(RegClass, RegsAvailableCopy);
+  RegsAvailableCopy &= RegsAvailable;
 
   // If looking for a non-callee-saved register, mask off all the callee-saved
   // registers.
   if (ExCalleeSaved)
-    RegStatesCopy &= ~CalleeSavedRegs;
+    RegsAvailableCopy &= ~CalleeSavedRegs;
 
   // Returns the first unused (bit is set) register, or 0 is none is found.
-  int Reg = RegStatesCopy.find_first();
+  int Reg = RegsAvailableCopy.find_first();
   return (Reg == -1) ? 0 : Reg;
 }
 
@@ -228,7 +236,7 @@ static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
   I = next(I);
   while (I != MBB->end()) {
     Dist++;
-    if (I->findRegisterUseOperand(Reg))
+    if (I->findRegisterUseOperandIdx(Reg) != -1)
         return Dist;
     I = next(I);    
   }
@@ -236,7 +244,8 @@ static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
 }
 
 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
-                                        MachineBasicBlock::iterator I) {
+                                        MachineBasicBlock::iterator I,
+                                        int SPAdj) {
   assert(ScavengingFrameIndex >= 0 &&
          "Cannot scavenge a register without an emergency spill slot!");
 
@@ -248,7 +257,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
   // Exclude all the registers being used by the instruction.
   for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = I->getOperand(i);
-    if (MO.isReg())
+    if (MO.isRegister())
       Candidates.reset(MO.getReg());
   }
 
@@ -267,15 +276,15 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
 
   if (ScavengedReg != 0) {
     // First restore previously scavenged register.
-    RegInfo->loadRegFromStackSlot(*MBB, I, ScavengedReg,
+    TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
                                   ScavengingFrameIndex, ScavengedRC);
     MachineBasicBlock::iterator II = prior(I);
-    RegInfo->eliminateFrameIndex(II, this);
+    RegInfo->eliminateFrameIndex(II, SPAdj, this);
   }
 
-  RegInfo->storeRegToStackSlot(*MBB, I, SReg, ScavengingFrameIndex, RC);
+  TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
   MachineBasicBlock::iterator II = prior(I);
-  RegInfo->eliminateFrameIndex(II, this);
+  RegInfo->eliminateFrameIndex(II, SPAdj, this);
   ScavengedReg = SReg;
   ScavengedRC = RC;