Do not unconditionally redefine vec_ext_v16qi and

[oota-llvm.git] / lib / CodeGen / RegisterScavenging.cpp

diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 9e917bd0bab705364fe1bc7c7c393cad44fd0110..aeed72cef52e955f6f97d5044d6faabaf00de54f 100644 (file)
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -92,10 +92,11 @@ void RegScavenger::forward() {
   }
 
   MachineInstr *MI = MBBI;
+  const TargetInstrDesc &TID = MI->getDesc();
 
   // Reaching a terminator instruction. Restore a scavenged register (which
   // must be life out.
-  if (TII->isTerminatorInstr(MI->getOpcode()))
+  if (TID.isTerminator())
     restoreScavengedReg();
 
   // Process uses first.
@@ -122,7 +123,6 @@ void RegScavenger::forward() {
   setUnused(ChangedRegs);
 
   // Process defs.
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isRegister() || !MO.isDef())
@@ -134,7 +134,7 @@ void RegScavenger::forward() {
       continue;
     }
     // Skip two-address destination operand.
-    if (TID->findTiedToSrcOperand(i) != -1) {
+    if (TID.findTiedToSrcOperand(i) != -1) {
       assert(isUsed(Reg) && "Using an undefined register!");
       continue;
     }
@@ -152,13 +152,13 @@ void RegScavenger::backward() {
 
   MachineInstr *MI = MBBI;
   // Process defs first.
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  const TargetInstrDesc &TID = MI->getDesc();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isRegister() || !MO.isDef())
       continue;
     // Skip two-address destination operand.
-    if (TID->findTiedToSrcOperand(i) != -1)
+    if (TID.findTiedToSrcOperand(i) != -1)
       continue;
     unsigned Reg = MO.getReg();
     assert(isUsed(Reg));