//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "reg-scavenging"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
+#define DEBUG_TYPE "reg-scavenging"
+
/// setUsed - Set the register and its sub-registers as being used.
void RegScavenger::setUsed(unsigned Reg) {
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
}
void RegScavenger::initRegState() {
- for (SmallVector<ScavengedInfo, 2>::iterator I = Scavenged.begin(),
- IE = Scavenged.end(); I != IE; ++I) {
+ for (SmallVectorImpl<ScavengedInfo>::iterator I = Scavenged.begin(),
+ IE = Scavenged.end(); I != IE; ++I) {
I->Reg = 0;
- I->Restore = NULL;
+ I->Restore = nullptr;
}
// All registers started out unused.
// Create callee-saved registers bitvector.
CalleeSavedRegs.resize(NumPhysRegs);
- const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
- if (CSRegs != NULL)
+ const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
+ if (CSRegs != nullptr)
for (unsigned i = 0; CSRegs[i]; ++i)
CalleeSavedRegs.set(CSRegs[i]);
}
}
if (MBBI == MBB->begin()) {
- MBBI = MachineBasicBlock::iterator(NULL);
+ MBBI = MachineBasicBlock::iterator(nullptr);
Tracking = false;
} else
--MBBI;
Tracking = true;
} else {
assert(MBBI != MBB->end() && "Already past the end of the basic block!");
- MBBI = llvm::next(MBBI);
+ MBBI = std::next(MBBI);
}
assert(MBBI != MBB->end() && "Already at the end of the basic block!");
MachineInstr *MI = MBBI;
- for (SmallVector<ScavengedInfo, 2>::iterator I = Scavenged.begin(),
- IE = Scavenged.end(); I != IE; ++I) {
+ for (SmallVectorImpl<ScavengedInfo>::iterator I = Scavenged.begin(),
+ IE = Scavenged.end(); I != IE; ++I) {
if (I->Restore != MI)
continue;
I->Reg = 0;
- I->Restore = NULL;
+ I->Restore = nullptr;
}
if (MI->isDebugValue())
break;
}
if (!SubUsed) {
- MBB->getParent()->verify(NULL, "In Register Scavenger");
+ MBB->getParent()->verify(nullptr, "In Register Scavenger");
llvm_unreachable("Using an undefined register!");
}
(void)SubUsed;
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
- if (MO.isReg() && MO.getReg() != 0 &&
+ if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Candidates.reset(MO.getReg());
}
"Cannot scavenge register without an emergency spill slot!");
TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
RC, TRI);
- MachineBasicBlock::iterator II = prior(I);
+ MachineBasicBlock::iterator II = std::prev(I);
unsigned FIOperandNum = getFrameIndexOperandNum(II);
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
// Restore the scavenged register before its use (or first terminator).
TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
RC, TRI);
- II = prior(UseMI);
+ II = std::prev(UseMI);
FIOperandNum = getFrameIndexOperandNum(II);
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
}
- Scavenged[SI].Restore = prior(UseMI);
+ Scavenged[SI].Restore = std::prev(UseMI);
// Doing this here leads to infinite regress.
// Scavenged[SI].Reg = SReg;