/// LaneMask are split as necessary. @p LaneMask are the lanes that
/// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
/// lanemasks already adjusted to the coalesced register.
- /// @returns false if live range conflicts couldn't get resolved.
- bool mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
+ void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
LaneBitmask LaneMask, CoalescerPair &CP);
/// Join the liveranges of two subregisters. Joins @p RRange into
/// @p LRange, @p RRange may be invalid afterwards.
- /// @returns false if live range conflicts couldn't get resolved.
- bool joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
+ void joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
LaneBitmask LaneMask, const CoalescerPair &CP);
/// We found a non-trivially-coalescable copy. If the source value number is
unsigned UseOpIdx;
if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
return false;
- unsigned Op1, Op2, NewDstIdx;
- if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
- return false;
- if (Op1 == UseOpIdx)
- NewDstIdx = Op2;
- else if (Op2 == UseOpIdx)
- NewDstIdx = Op1;
- else
+
+ // FIXME: The code below tries to commute 'UseOpIdx' operand with some other
+ // commutable operand which is expressed by 'CommuteAnyOperandIndex'value
+ // passed to the method. That _other_ operand is chosen by
+ // the findCommutedOpIndices() method.
+ //
+ // That is obviously an area for improvement in case of instructions having
+ // more than 2 operands. For example, if some instruction has 3 commutable
+ // operands then all possible variants (i.e. op#1<->op#2, op#1<->op#3,
+ // op#2<->op#3) of commute transformation should be considered/tried here.
+ unsigned NewDstIdx = TargetInstrInfo::CommuteAnyOperandIndex;
+ if (!TII->findCommutedOpIndices(DefMI, UseOpIdx, NewDstIdx))
return false;
MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
// At this point we have decided that it is legal to do this
// transformation. Start by commuting the instruction.
MachineBasicBlock *MBB = DefMI->getParent();
- MachineInstr *NewMI = TII->commuteInstruction(DefMI);
+ MachineInstr *NewMI =
+ TII->commuteInstruction(DefMI, false, UseOpIdx, NewDstIdx);
if (!NewMI)
return false;
if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
}
}
-bool RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
+void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
LaneBitmask LaneMask,
const CoalescerPair &CP) {
SmallVector<VNInfo*, 16> NewVNInfo;
// ranges get mapped to the "overflow" lane mask bit which creates unexpected
// interferences.
if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals)) {
- DEBUG(dbgs() << "*** Couldn't join subrange!\n");
- return false;
+ // We already determined that it is legal to merge the intervals, so this
+ // should never fail.
+ llvm_unreachable("*** Couldn't join subrange!\n");
}
if (!LHSVals.resolveConflicts(RHSVals) ||
!RHSVals.resolveConflicts(LHSVals)) {
- DEBUG(dbgs() << "*** Couldn't join subrange!\n");
- return false;
+ // We already determined that it is legal to merge the intervals, so this
+ // should never fail.
+ llvm_unreachable("*** Couldn't join subrange!\n");
}
// The merging algorithm in LiveInterval::join() can't handle conflicting
DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n");
if (EndPoints.empty())
- return true;
+ return;
// Recompute the parts of the live range we had to remove because of
// CR_Replace conflicts.
DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
<< " points: " << LRange << '\n');
LIS->extendToIndices(LRange, EndPoints);
- return true;
}
-bool RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
+void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
const LiveRange &ToMerge,
LaneBitmask LaneMask,
CoalescerPair &CP) {
CommonRange = &R;
}
LiveRange RangeCopy(ToMerge, Allocator);
- if (!joinSubRegRanges(*CommonRange, RangeCopy, Common, CP))
- return false;
+ joinSubRegRanges(*CommonRange, RangeCopy, Common, CP);
LaneMask &= ~RMask;
}
DEBUG(dbgs() << "\t\tNew Lane " << PrintLaneMask(LaneMask) << '\n');
LI.createSubRangeFrom(Allocator, LaneMask, ToMerge);
}
- return true;
}
bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
// Determine lanemasks of RHS in the coalesced register and merge subranges.
unsigned SrcIdx = CP.getSrcIdx();
- bool Abort = false;
if (!RHS.hasSubRanges()) {
LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
: TRI->getSubRegIndexLaneMask(SrcIdx);
- if (!mergeSubRangeInto(LHS, RHS, Mask, CP))
- Abort = true;
+ mergeSubRangeInto(LHS, RHS, Mask, CP);
} else {
// Pair up subranges and merge.
for (LiveInterval::SubRange &R : RHS.subranges()) {
LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
- if (!mergeSubRangeInto(LHS, R, Mask, CP)) {
- Abort = true;
- break;
- }
+ mergeSubRangeInto(LHS, R, Mask, CP);
}
}
- if (Abort) {
- // This shouldn't have happened :-(
- // However we are aware of at least one existing problem where we
- // can't merge subranges when multiple ranges end up in the
- // "overflow bit" 32. As a workaround we drop all subregister ranges
- // which means we loose some precision but are back to a well defined
- // state.
- assert(TargetRegisterInfo::isImpreciseLaneMask(
- CP.getNewRC()->getLaneMask())
- && "SubRange merge should only fail when merging into bit 32.");
- DEBUG(dbgs() << "\tSubrange join aborted!\n");
- LHS.clearSubRanges();
- RHS.clearSubRanges();
- } else {
- DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n");
+ DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n");
- LHSVals.pruneSubRegValues(LHS, ShrinkMask);
- RHSVals.pruneSubRegValues(LHS, ShrinkMask);
- }
+ LHSVals.pruneSubRegValues(LHS, ShrinkMask);
+ RHSVals.pruneSubRegValues(LHS, ShrinkMask);
}
// The merging algorithm in LiveInterval::join() can't handle conflicting
std::vector<MBBPriorityInfo> MBBs;
MBBs.reserve(MF->size());
- for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
- MachineBasicBlock *MBB = I;
+ for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
+ MachineBasicBlock *MBB = &*I;
MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
JoinSplitEdges && isSplitEdge(MBB)));
}
if (MRI->recomputeRegClass(Reg)) {
DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
<< TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
+ ++NumInflated;
+
LiveInterval &LI = LIS->getInterval(Reg);
- LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
- if (MaxMask == 0) {
+ if (LI.hasSubRanges()) {
// If the inflated register class does not support subregisters anymore
// remove the subranges.
- LI.clearSubRanges();
- } else {
+ if (!MRI->shouldTrackSubRegLiveness(Reg)) {
+ LI.clearSubRanges();
+ } else {
#ifndef NDEBUG
- // If subranges are still supported, then the same subregs should still
- // be supported.
- for (LiveInterval::SubRange &S : LI.subranges()) {
- assert ((S.LaneMask & ~MaxMask) == 0);
- }
+ LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
+ // If subranges are still supported, then the same subregs
+ // should still be supported.
+ for (LiveInterval::SubRange &S : LI.subranges()) {
+ assert((S.LaneMask & ~MaxMask) == 0);
+ }
#endif
+ }
}
- ++NumInflated;
}
}