//
//===----------------------------------------------------------------------===//
-#include "RegisterClassInfo.h"
+#define DEBUG_TYPE "regalloc"
+#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
+static cl::opt<unsigned>
+StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
+ cl::desc("Limit all regclasses to N registers"));
+
RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
{}
}
// Does this MF have different CSRs?
- const unsigned *CSR = TRI->getCalleeSavedRegs(MF);
+ const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
if (Update || CSR != CalleeSaved) {
// Build a CSRNum map. Every CSR alias gets an entry pointing to the last
// overlapping CSR.
- CSRNum.reset(new uint8_t[TRI->getNumRegs()]());
+ CSRNum.clear();
+ CSRNum.resize(TRI->getNumRegs(), 0);
for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
- for (const unsigned *AS = TRI->getOverlaps(Reg);
- unsigned Alias = *AS; ++AS)
- CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
+ for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
+ CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
Update = true;
}
CalleeSaved = CSR;
// Different reserved registers?
- BitVector RR = TRI->getReservedRegs(*MF);
- if (RR != Reserved)
+ const BitVector &RR = MF->getRegInfo().getReservedRegs();
+ if (Reserved.size() != RR.size() || RR != Reserved) {
Update = true;
- Reserved = RR;
+ Reserved = RR;
+ }
// Invalidate cached information from previous function.
if (Update)
unsigned NumRegs = RC->getNumRegs();
if (!RCI.Order)
- RCI.Order.reset(new unsigned[NumRegs]);
+ RCI.Order.reset(new MCPhysReg[NumRegs]);
unsigned N = 0;
- SmallVector<std::pair<unsigned, unsigned>, 8> CSRAlias;
+ SmallVector<MCPhysReg, 16> CSRAlias;
// FIXME: Once targets reserve registers instead of removing them from the
// allocation order, we can simply use begin/end here.
- TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
- TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
-
- for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
- unsigned PhysReg = *I;
+ ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
+ for (unsigned i = 0; i != RawOrder.size(); ++i) {
+ unsigned PhysReg = RawOrder[i];
// Remove reserved registers from the allocation order.
if (Reserved.test(PhysReg))
continue;
- if (unsigned CSR = CSRNum[PhysReg])
+ if (CSRNum[PhysReg])
// PhysReg aliases a CSR, save it for later.
- CSRAlias.push_back(std::make_pair(CSR, PhysReg));
+ CSRAlias.push_back(PhysReg);
else
RCI.Order[N++] = PhysReg;
}
RCI.NumRegs = N + CSRAlias.size();
assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
- // Sort CSR aliases acording to the CSR ordering.
- if (CSRAlias.size() >= 2)
- array_pod_sort(CSRAlias.begin(), CSRAlias.end());
+ // CSR aliases go after the volatile registers, preserve the target's order.
+ std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
+
+ // Register allocator stress test. Clip register class to N registers.
+ if (StressRA && RCI.NumRegs > StressRA)
+ RCI.NumRegs = StressRA;
+
+ // Check if RC is a proper sub-class.
+ if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
+ if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
+ RCI.ProperSubClass = true;
- for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i)
- RCI.Order[N++] = CSRAlias[i].second;
+ DEBUG({
+ dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
+ for (unsigned I = 0; I != RCI.NumRegs; ++I)
+ dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
+ dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
+ });
// RCI is now up-to-date.
RCI.Tag = Tag;