#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
+#include <map>
using namespace llvm;
STATISTIC(NumStores, "Number of stores added");
private:
MachineFunction *MF;
const TargetMachine *TM;
- const MRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
+ const TargetInstrInfo *TII;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
const TargetRegisterClass *RC) {
// Find the location VirtReg would belong...
- std::map<unsigned, int>::iterator I =
- StackSlotForVirtReg.lower_bound(VirtReg);
+ std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
- if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
+ if (I != StackSlotForVirtReg.end())
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
// Add move instruction(s)
++NumLoads;
- const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
- const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- RegsUsed.resize(MRI->getNumRegs());
+ RegsUsed.resize(TRI->getNumRegs());
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand &op = MI->getOperand(i);
+ MachineOperand &MO = MI->getOperand(i);
- if (op.isRegister() && op.getReg() &&
- MRegisterInfo::isVirtualRegister(op.getReg())) {
- unsigned virtualReg = (unsigned) op.getReg();
- DOUT << "op: " << op << "\n";
+ if (MO.isRegister() && MO.getReg() &&
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
+ unsigned virtualReg = (unsigned) MO.getReg();
+ DOUT << "op: " << MO << "\n";
DOUT << "\t inst[" << i << "]: ";
DEBUG(MI->print(*cerr.stream(), TM));
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.isDef()) {
+ if (MO.isDef()) {
int TiedOp = Desc.findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
Virt2PhysRegMap[virtualReg] = physReg;
}
}
- MI->getOperand(i).setReg(physReg);
- DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
+ MO.setReg(physReg);
+ DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n";
}
}
RegClassIdx.clear();
DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
- MRI = TM->getRegisterInfo();
+ TRI = TM->getRegisterInfo();
+ TII = TM->getInstrInfo();
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();