Was pointed out that structure alignment and type alignment are not the same

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index cd48cd2af54a4dac9215e4f7cb743b5fbde73989..4e6e1d2705e1b2e2793e6f3344cec7609f69865c 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -1,10 +1,10 @@
 //===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file implements a simple register allocator. *Very* simple: It immediate
@@ -22,9 +22,9 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
-#include "Support/Debug.h"
-#include "Support/Statistic.h"
-#include "Support/STLExtras.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/STLExtras.h"
 #include <iostream>
 using namespace llvm;
 
@@ -36,7 +36,8 @@ namespace {
     MachineFunction *MF;
     const TargetMachine *TM;
     const MRegisterInfo *RegInfo;
-    
+    bool *PhysRegsEverUsed;
+
     // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
     // these values are spilled
     std::map<unsigned, int> StackSlotForVirtReg;
@@ -91,7 +92,7 @@ namespace {
 /// getStackSpaceFor - This allocates space for the specified virtual
 /// register to be held on the stack.
 int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
-                                    const TargetRegisterClass *RC) {
+                                     const TargetRegisterClass *RC) {
   // Find the location VirtReg would belong...
   std::map<unsigned, int>::iterator I =
     StackSlotForVirtReg.lower_bound(VirtReg);
@@ -100,8 +101,9 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
     return I->second;          // Already has space allocated?
 
   // Allocate a new stack object for this spill location...
-  int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC);
-  
+  int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
+                                                       RC->getAlignment());
+
   // Assign the slot...
   StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
 
@@ -114,12 +116,14 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
   TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
 
   while (1) {
-    unsigned regIdx = RegClassIdx[RC]++; 
+    unsigned regIdx = RegClassIdx[RC]++;
     assert(RI+regIdx != RE && "Not enough registers!");
     unsigned PhysReg = *(RI+regIdx);
-    
-    if (!RegsUsed[PhysReg])
+
+    if (!RegsUsed[PhysReg]) {
+      PhysRegsEverUsed[PhysReg] = true;
       return PhysReg;
+    }
   }
 }
 
@@ -155,35 +159,37 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     std::map<unsigned, unsigned> Virt2PhysRegMap;
 
     RegsUsed.resize(RegInfo->getNumRegs());
-    
-    // a preliminary pass that will invalidate any registers that
-    // are used by the instruction (including implicit uses)
+
+    // This is a preliminary pass that will invalidate any registers that are
+    // used by the instruction (including implicit uses).
     unsigned Opcode = MI->getOpcode();
-    const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
-    const unsigned *Regs = Desc.ImplicitUses;
-    while (*Regs)
-      RegsUsed[*Regs++] = true;
-    
-    Regs = Desc.ImplicitDefs;
-    while (*Regs)
-      RegsUsed[*Regs++] = true;
-    
-    // Loop over uses, move from memory into registers
+    const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+    const unsigned *Regs;
+    for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
+      RegsUsed[*Regs] = true;
+
+    for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
+      RegsUsed[*Regs] = true;
+      PhysRegsEverUsed[*Regs] = true;
+    }
+
+    // Loop over uses, move from memory into registers.
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
       MachineOperand &op = MI->getOperand(i);
-      
-      if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
+
+      if (op.isRegister() && op.getReg() &&
+          MRegisterInfo::isVirtualRegister(op.getReg())) {
         unsigned virtualReg = (unsigned) op.getReg();
         DEBUG(std::cerr << "op: " << op << "\n");
         DEBUG(std::cerr << "\t inst[" << i << "]: ";
-              MI->print(std::cerr, *TM));
-        
+              MI->print(std::cerr, TM));
+
         // make sure the same virtual register maps to the same physical
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
           if (op.isDef()) {
-            if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) {
+            if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
               physReg = getFreeReg(virtualReg);
             } else {
               // must be same register number as the first operand
@@ -205,8 +211,8 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
             Virt2PhysRegMap[virtualReg] = physReg;
           }
         }
-        MI->SetMachineOperandReg(i, physReg);
-        DEBUG(std::cerr << "virt: " << virtualReg << 
+        MI->getOperand(i).setReg(physReg);
+        DEBUG(std::cerr << "virt: " << virtualReg <<
               ", phys: " << op.getReg() << "\n");
       }
     }
@@ -224,6 +230,10 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
   TM = &MF->getTarget();
   RegInfo = TM->getRegisterInfo();
 
+  PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
+  std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
+  Fn.setUsedPhysRegs(PhysRegsEverUsed);
+
   // Loop over all of the basic blocks, eliminating virtual register references
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
        MBB != MBBe; ++MBB)