namespace {
static RegisterRegAlloc
- simpleRegAlloc("simple", " simple register allocator",
+ simpleRegAlloc("simple", "simple register allocator",
createSimpleRegisterAllocator);
class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
+#ifndef NDEBUG
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
+#endif
while (1) {
unsigned regIdx = RegClassIdx[RC]++;
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (MO.isDef()) {
- int TiedOp = Desc.findTiedToSrcOperand(i);
- if (TiedOp == -1) {
+ unsigned TiedOp;
+ if (!MI->isRegTiedToUseOperand(i, &TiedOp)) {
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the source operand that is