Fix pr3954. The register scavenger asserts for inline assembly with

[oota-llvm.git] / lib / CodeGen / RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 9ad38405ae77eaf067976c2aecdfac114cdcef38..447e54cf790bd179d5d7677626b4a3a5c7f9ce62 100644 (file)
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -35,13 +35,13 @@ STATISTIC(NumLoads , "Number of loads added");
 
 namespace {
   static RegisterRegAlloc
-    simpleRegAlloc("simple", "  simple register allocator",
+    simpleRegAlloc("simple", "simple register allocator",
                    createSimpleRegisterAllocator);
 
   class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
   public:
     static char ID;
-    RegAllocSimple() : MachineFunctionPass((intptr_t)&ID) {}
+    RegAllocSimple() : MachineFunctionPass(&ID) {}
   private:
     MachineFunction *MF;
     const TargetMachine *TM;
@@ -122,7 +122,9 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
 unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
   TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
+#ifndef NDEBUG
   TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
+#endif
 
   while (1) {
     unsigned regIdx = RegClassIdx[RC]++;
@@ -190,7 +192,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
       MachineOperand &MO = MI->getOperand(i);
 
-      if (MO.isRegister() && MO.getReg() &&
+      if (MO.isReg() && MO.getReg() &&
           TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
         unsigned virtualReg = (unsigned) MO.getReg();
         DOUT << "op: " << MO << "\n";
@@ -202,14 +204,14 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
           if (MO.isDef()) {
-            int TiedOp = Desc.findTiedToSrcOperand(i);
-            if (TiedOp == -1) {
+            unsigned TiedOp;
+            if (!MI->isRegTiedToUseOperand(i, &TiedOp)) {
               physReg = getFreeReg(virtualReg);
             } else {
               // must be same register number as the source operand that is 
               // tied to. This maps a = b + c into b = b + c, and saves b into
               // a's spot.
-              assert(MI->getOperand(TiedOp).isRegister()  &&
+              assert(MI->getOperand(TiedOp).isReg()  &&
                      MI->getOperand(TiedOp).getReg() &&
                      MI->getOperand(TiedOp).isUse() &&
                      "Two address instruction invalid!");