//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
+#include <map>
using namespace llvm;
STATISTIC(NumStores, "Number of stores added");
namespace {
static RegisterRegAlloc
- simpleRegAlloc("simple", " simple register allocator",
+ simpleRegAlloc("simple", "simple register allocator",
createSimpleRegisterAllocator);
class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
public:
- static const char ID;
- RegAllocSimple() : MachineFunctionPass((intptr_t)&ID) {}
+ static char ID;
+ RegAllocSimple() : MachineFunctionPass(&ID) {}
private:
MachineFunction *MF;
const TargetMachine *TM;
- const MRegisterInfo *RegInfo;
+ const TargetRegisterInfo *TRI;
+ const TargetInstrInfo *TII;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg);
};
- const char RegAllocSimple::ID = 0;
+ char RegAllocSimple::ID = 0;
}
/// getStackSpaceFor - This allocates space for the specified virtual
int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
const TargetRegisterClass *RC) {
// Find the location VirtReg would belong...
- std::map<unsigned, int>::iterator I =
- StackSlotForVirtReg.lower_bound(VirtReg);
+ std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
- if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
+ if (I != StackSlotForVirtReg.end())
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
}
unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
- const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg);
+ const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
+#ifndef NDEBUG
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
+#endif
while (1) {
unsigned regIdx = RegClassIdx[RC]++;
unsigned PhysReg = *(RI+regIdx);
if (!RegsUsed[PhysReg]) {
- MF->setPhysRegUsed(PhysReg);
+ MF->getRegInfo().setPhysRegUsed(PhysReg);
return PhysReg;
}
}
unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg) {
- const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
+ const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC);
unsigned PhysReg = getFreeReg(VirtReg);
// Add move instruction(s)
++NumLoads;
- RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
- const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
+ const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
+
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumStores;
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
}
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- RegsUsed.resize(RegInfo->getNumRegs());
+ RegsUsed.resize(TRI->getNumRegs());
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
- unsigned Opcode = MI->getOpcode();
- const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
+ const TargetInstrDesc &Desc = MI->getDesc();
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
if (Desc.ImplicitDefs) {
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
RegsUsed[*Regs] = true;
- MF->setPhysRegUsed(*Regs);
+ MF->getRegInfo().setPhysRegUsed(*Regs);
}
}
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand &op = MI->getOperand(i);
+ MachineOperand &MO = MI->getOperand(i);
- if (op.isRegister() && op.getReg() &&
- MRegisterInfo::isVirtualRegister(op.getReg())) {
- unsigned virtualReg = (unsigned) op.getReg();
- DOUT << "op: " << op << "\n";
+ if (MO.isReg() && MO.getReg() &&
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
+ unsigned virtualReg = (unsigned) MO.getReg();
+ DOUT << "op: " << MO << "\n";
DOUT << "\t inst[" << i << "]: ";
DEBUG(MI->print(*cerr.stream(), TM));
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.isDef()) {
- int TiedOp = MI->getInstrDescriptor()->findTiedToSrcOperand(i);
- if (TiedOp == -1) {
+ if (MO.isDef()) {
+ unsigned TiedOp;
+ if (!MI->isRegTiedToUseOperand(i, &TiedOp)) {
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the source operand that is
// tied to. This maps a = b + c into b = b + c, and saves b into
// a's spot.
- assert(MI->getOperand(TiedOp).isRegister() &&
+ assert(MI->getOperand(TiedOp).isReg() &&
MI->getOperand(TiedOp).getReg() &&
MI->getOperand(TiedOp).isUse() &&
"Two address instruction invalid!");
Virt2PhysRegMap[virtualReg] = physReg;
}
}
- MI->getOperand(i).setReg(physReg);
- DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
+ MO.setReg(physReg);
+ DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n";
}
}
RegClassIdx.clear();
DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
- RegInfo = TM->getRegisterInfo();
+ TRI = TM->getRegisterInfo();
+ TII = TM->getInstrInfo();
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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