When deleting a machine instruction, make sure to remove it from the

[oota-llvm.git] / lib / CodeGen / RegAllocLocal.cpp

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index f84f7e82ef07f94f730036b883b53568ae2a243f..c435c34f49e0ef85368c75851a3f01c382c02aad 100644 (file)
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -19,10 +19,12 @@
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/LiveVariables.h"
+#include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Statistic.h"
 #include <algorithm>
@@ -30,11 +32,17 @@
 using namespace llvm;
 
 namespace {
-  Statistic<> NumStores("ra-local", "Number of stores added");
-  Statistic<> NumLoads ("ra-local", "Number of loads added");
-  Statistic<> NumFolded("ra-local", "Number of loads/stores folded into "
-                        "instructions");
-  class RA : public MachineFunctionPass {
+  static Statistic<> NumStores("ra-local", "Number of stores added");
+  static Statistic<> NumLoads ("ra-local", "Number of loads added");
+  static Statistic<> NumFolded("ra-local", "Number of loads/stores folded "
+                              "into instructions");
+
+  static RegisterRegAlloc
+    localRegAlloc("local", "  local register allocator",
+                  createLocalRegisterAllocator);
+
+
+  class VISIBILITY_HIDDEN RA : public MachineFunctionPass {
     const TargetMachine *TM;
     MachineFunction *MF;
     const MRegisterInfo *RegInfo;
@@ -443,7 +451,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
   // and return.
   if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
     MarkPhysRegRecentlyUsed(PR);          // Already have this value available!
-    MI->SetMachineOperandReg(OpNum, PR);  // Assign the input register
+    MI->getOperand(OpNum).setReg(PR);  // Assign the input register
     return MI;
   }
 
@@ -481,7 +489,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
   ++NumLoads;    // Update statistics
 
   PhysRegsEverUsed[PhysReg] = true;
-  MI->SetMachineOperandReg(OpNum, PhysReg);  // Assign the input register
+  MI->getOperand(OpNum).setReg(PhysReg);  // Assign the input register
   return MI;
 }
 
@@ -491,6 +499,26 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
   // loop over each instruction
   MachineBasicBlock::iterator MII = MBB.begin();
   const TargetInstrInfo &TII = *TM->getInstrInfo();
+  
+  // If this is the first basic block in the machine function, add live-in
+  // registers as active.
+  if (&MBB == &*MF->begin()) {
+    for (MachineFunction::livein_iterator I = MF->livein_begin(),
+         E = MF->livein_end(); I != E; ++I) {
+      unsigned Reg = I->first;
+      PhysRegsEverUsed[Reg] = true;
+      PhysRegsUsed[Reg] = 0;            // It is free and reserved now
+      PhysRegsUseOrder.push_back(Reg);
+      for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+           *AliasSet; ++AliasSet) {
+        PhysRegsUseOrder.push_back(*AliasSet);
+        PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+        PhysRegsEverUsed[*AliasSet] = true;
+      }
+    }    
+  }
+  
+  // Otherwise, sequentially allocate each instruction in the MBB.
   while (MII != MBB.end()) {
     MachineInstr *MI = MII++;
     const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
@@ -504,9 +532,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
 
     // Loop over the implicit uses, making sure that they are at the head of the
     // use order list, so they don't get reallocated.
-    for (const unsigned *ImplicitUses = TID.ImplicitUses;
-         *ImplicitUses; ++ImplicitUses)
-      MarkPhysRegRecentlyUsed(*ImplicitUses);
+    if (TID.ImplicitUses) {
+      for (const unsigned *ImplicitUses = TID.ImplicitUses;
+           *ImplicitUses; ++ImplicitUses)
+        MarkPhysRegRecentlyUsed(*ImplicitUses);
+    }
 
     // Get the used operands into registers.  This has the potential to spill
     // incoming values if we are out of registers.  Note that we completely
@@ -566,19 +596,21 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
     }
 
     // Loop over the implicit defs, spilling them as well.
-    for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
-         *ImplicitDefs; ++ImplicitDefs) {
-      unsigned Reg = *ImplicitDefs;
-      spillPhysReg(MBB, MI, Reg, true);
-      PhysRegsUseOrder.push_back(Reg);
-      PhysRegsUsed[Reg] = 0;            // It is free and reserved now
-      PhysRegsEverUsed[Reg] = true;
+    if (TID.ImplicitDefs) {
+      for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
+           *ImplicitDefs; ++ImplicitDefs) {
+        unsigned Reg = *ImplicitDefs;
+        spillPhysReg(MBB, MI, Reg, true);
+        PhysRegsUseOrder.push_back(Reg);
+        PhysRegsUsed[Reg] = 0;            // It is free and reserved now
+        PhysRegsEverUsed[Reg] = true;
 
-      for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
-           *AliasSet; ++AliasSet) {
-        PhysRegsUseOrder.push_back(*AliasSet);
-        PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-        PhysRegsEverUsed[*AliasSet] = true;
+        for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+             *AliasSet; ++AliasSet) {
+          PhysRegsUseOrder.push_back(*AliasSet);
+          PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+          PhysRegsEverUsed[*AliasSet] = true;
+        }
       }
     }
 
@@ -599,7 +631,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
           DestPhysReg = getReg(MBB, MI, DestVirtReg);
         PhysRegsEverUsed[DestPhysReg] = true;
         markVirtRegModified(DestVirtReg);
-        MI->SetMachineOperandReg(i, DestPhysReg);  // Assign the output register
+        MI->getOperand(i).setReg(DestPhysReg);  // Assign the output register
       }
     }
 
@@ -627,8 +659,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
     
     // Finally, if this is a noop copy instruction, zap it.
     unsigned SrcReg, DstReg;
-    if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
+    if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) {
+      LV->removeVirtualRegistersKilled(MI);
+      LV->removeVirtualRegistersDead(MI);
       MBB.erase(MI);
+    }
   }
 
   MachineBasicBlock::iterator MI = MBB.getFirstTerminator();