#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
+#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "Support/CommandLine.h"
-#include "Support/Debug.h"
-#include "Support/Statistic.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/Statistic.h"
+#include <algorithm>
#include <iostream>
using namespace llvm;
namespace {
- Statistic<> NumStores("ra-local", "Number of stores added");
- Statistic<> NumLoads ("ra-local", "Number of loads added");
- Statistic<> NumFused ("ra-local", "Number of reloads fused into instructions");
- class RA : public MachineFunctionPass {
+ static Statistic<> NumStores("ra-local", "Number of stores added");
+ static Statistic<> NumLoads ("ra-local", "Number of loads added");
+ static Statistic<> NumFolded("ra-local", "Number of loads/stores folded "
+ "into instructions");
+
+ static RegisterRegAlloc
+ localRegAlloc("local", " local register allocator",
+ createLocalRegisterAllocator);
+
+
+ class VISIBILITY_HIDDEN RA : public MachineFunctionPass {
const TargetMachine *TM;
MachineFunction *MF;
const MRegisterInfo *RegInfo;
LiveVariables *LV;
+ bool *PhysRegsEverUsed;
// StackSlotForVirtReg - Maps virtual regs to the frame index where these
// values are spilled.
std::map<unsigned, int> StackSlotForVirtReg;
// Virt2PhysRegMap - This map contains entries for each virtual register
- // that is currently available in a physical register. This is "logically"
- // a map from virtual register numbers to physical register numbers.
- // Instead of using a map, however, which is slow, we use a vector. The
- // index is the VREG number - FirstVirtualRegister. If the entry is zero,
- // then it is logically "not in the map".
- //
- std::vector<unsigned> Virt2PhysRegMap;
+ // that is currently available in a physical register.
+ DenseMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
- assert(MRegisterInfo::isVirtualRegister(VirtReg) &&"Illegal VREG #");
- assert(VirtReg-MRegisterInfo::FirstVirtualRegister <Virt2PhysRegMap.size()
- && "VirtReg not in map!");
- return Virt2PhysRegMap[VirtReg-MRegisterInfo::FirstVirtualRegister];
+ return Virt2PhysRegMap[VirtReg];
}
// PhysRegsUsed - This array is effectively a map, containing entries for
}
void MarkPhysRegRecentlyUsed(unsigned Reg) {
- assert(!PhysRegsUseOrder.empty() && "No registers used!");
- if (PhysRegsUseOrder.back() == Reg) return; // Already most recently used
+ if(PhysRegsUseOrder.empty() ||
+ PhysRegsUseOrder.back() == Reg) return; // Already most recently used
for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
/// the virtual register slot specified by VirtReg. It then updates the RA
/// data structures to indicate the fact that PhysReg is now available.
///
- void spillVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
+ void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned VirtReg, unsigned PhysReg);
/// spillPhysReg - This method spills the specified physical register into
///
MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum);
-
+
void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg);
return I->second; // Already has space allocated?
// Allocate a new stack object for this spill location...
- int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC);
+ int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
+ RC->getAlignment());
// Assign the slot...
StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
/// virtual register slot specified by VirtReg. It then updates the RA data
/// structures to indicate the fact that PhysReg is now available.
///
-void RA::spillVirtReg(MachineBasicBlock &MBB, MachineInstr *I,
+void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
assert(VirtReg && "Spilling a physical register is illegal!"
" Must not have appropriate kill for the register or use exists beyond"
///
void RA::liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg) {
- // FIXME: This code checks to see if a register is available, but it really
- // wants to know if a reg is available BEFORE the instruction executes. If
- // called after killed operands are freed, it runs the risk of reallocating a
- // used operand...
-#if 0
- if (isPhysRegAvailable(PhysReg)) return; // Already available...
-
- // Check to see if the register is directly used, not indirectly used through
- // aliases. If aliased registers are the ones actually used, we cannot be
- // sure that we will be able to save the whole thing if we do a reg-reg copy.
- if (PhysRegsUsed[PhysReg] != -1) {
- // The virtual register held...
- unsigned VirtReg = PhysRegsUsed[PhysReg]->second;
-
- // Check to see if there is a compatible register available. If so, we can
- // move the value into the new register...
- //
- const TargetRegisterClass *RC = RegInfo->getRegClass(PhysReg);
- if (unsigned NewReg = getFreeReg(RC)) {
- // Emit the code to copy the value...
- RegInfo->copyRegToReg(MBB, I, NewReg, PhysReg, RC);
-
- // Update our internal state to indicate that PhysReg is available and Reg
- // isn't.
- getVirt2PhysRegMapSlot[VirtReg] = 0;
- removePhysReg(PhysReg); // Free the physreg
-
- // Move reference over to new register...
- assignVirtToPhysReg(VirtReg, NewReg);
- return;
- }
- }
-#endif
spillPhysReg(MBB, I, PhysReg);
}
"PhysReg in PhysRegsUseOrder, but is not allocated?");
if (PhysRegsUsed[R]) {
// If the current register is compatible, use it.
- if (RegInfo->getRegClass(R) == RC) {
+ if (RC->contains(R)) {
PhysReg = R;
break;
} else {
// compatible, use it.
for (const unsigned *AliasSet = RegInfo->getAliasSet(R);
*AliasSet; ++AliasSet) {
- if (RegInfo->getRegClass(*AliasSet) == RC) {
+ if (RC->contains(*AliasSet)) {
PhysReg = *AliasSet; // Take an aliased register
break;
}
// and return.
if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
MarkPhysRegRecentlyUsed(PR); // Already have this value available!
- MI->SetMachineOperandReg(OpNum, PR); // Assign the input register
+ MI->getOperand(OpNum).setReg(PR); // Assign the input register
return MI;
}
assignVirtToPhysReg(VirtReg, PhysReg);
} else { // No registers available.
// If we can fold this spill into this instruction, do so now.
- MachineBasicBlock::iterator MII = MI;
- if (RegInfo->foldMemoryOperand(MII, OpNum, FrameIndex)) {
- ++NumFused;
+ if (MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, OpNum, FrameIndex)){
+ ++NumFolded;
// Since we changed the address of MI, make sure to update live variables
// to know that the new instruction has the properties of the old one.
- LV->instructionChanged(MI, MII);
- return MII;
+ LV->instructionChanged(MI, FMI);
+ return MBB.insert(MBB.erase(MI), FMI);
}
// It looks like we can't fold this virtual register load into this
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
- MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register
+ PhysRegsEverUsed[PhysReg] = true;
+ MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
return MI;
}
void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
- MachineBasicBlock::iterator MI = MBB.begin();
- for (; MI != MBB.end(); ++MI) {
- const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
+ MachineBasicBlock::iterator MII = MBB.begin();
+ const TargetInstrInfo &TII = *TM->getInstrInfo();
+
+ // If this is the first basic block in the machine function, add live-in
+ // registers as active.
+ if (&MBB == &*MF->begin()) {
+ for (MachineFunction::livein_iterator I = MF->livein_begin(),
+ E = MF->livein_end(); I != E; ++I) {
+ unsigned Reg = I->first;
+ PhysRegsEverUsed[Reg] = true;
+ PhysRegsUsed[Reg] = 0; // It is free and reserved now
+ PhysRegsUseOrder.push_back(Reg);
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) {
+ PhysRegsUseOrder.push_back(*AliasSet);
+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ PhysRegsEverUsed[*AliasSet] = true;
+ }
+ }
+ }
+
+ // Otherwise, sequentially allocate each instruction in the MBB.
+ while (MII != MBB.end()) {
+ MachineInstr *MI = MII++;
+ const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
std::cerr << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
// Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated.
- for (const unsigned *ImplicitUses = TID.ImplicitUses;
- *ImplicitUses; ++ImplicitUses)
- MarkPhysRegRecentlyUsed(*ImplicitUses);
+ if (TID.ImplicitUses) {
+ for (const unsigned *ImplicitUses = TID.ImplicitUses;
+ *ImplicitUses; ++ImplicitUses)
+ MarkPhysRegRecentlyUsed(*ImplicitUses);
+ }
// Get the used operands into registers. This has the potential to spill
// incoming values if we are out of registers. Note that we completely
// physical register is referenced by the instruction, that it is guaranteed
// to be live-in, or the input is badly hosed.
//
- for (unsigned i = 0; i != MI->getNumOperands(); ++i)
- if (MI->getOperand(i).isUse() &&
- !MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
- MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ // here we are looking for only used operands (never def&use)
+ if (!MO.isDef() && MO.isRegister() && MO.getReg() &&
+ MRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
+ }
// If this instruction is the last user of anything in registers, kill the
// value, freeing the register being used, so it doesn't need to be
//
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
KE = LV->killed_end(MI); KI != KE; ++KI) {
- unsigned VirtReg = KI->second;
+ unsigned VirtReg = *KI;
unsigned PhysReg = VirtReg;
if (MRegisterInfo::isVirtualRegister(VirtReg)) {
// If the virtual register was never materialized into a register, it
// Loop over all of the operands of the instruction, spilling registers that
// are defined, and marking explicit destinations in the PhysRegsUsed map.
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
- MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
- unsigned Reg = MI->getOperand(i).getReg();
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+ MRegisterInfo::isPhysicalRegister(MO.getReg())) {
+ unsigned Reg = MO.getReg();
+ PhysRegsEverUsed[Reg] = true;
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
*AliasSet; ++AliasSet) {
PhysRegsUseOrder.push_back(*AliasSet);
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ PhysRegsEverUsed[*AliasSet] = true;
}
}
+ }
// Loop over the implicit defs, spilling them as well.
- for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
- *ImplicitDefs; ++ImplicitDefs) {
- unsigned Reg = *ImplicitDefs;
- spillPhysReg(MBB, MI, Reg, true);
- PhysRegsUseOrder.push_back(Reg);
- PhysRegsUsed[Reg] = 0; // It is free and reserved now
- for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
- *AliasSet; ++AliasSet) {
- PhysRegsUseOrder.push_back(*AliasSet);
- PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ if (TID.ImplicitDefs) {
+ for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
+ *ImplicitDefs; ++ImplicitDefs) {
+ unsigned Reg = *ImplicitDefs;
+ spillPhysReg(MBB, MI, Reg, true);
+ PhysRegsUseOrder.push_back(Reg);
+ PhysRegsUsed[Reg] = 0; // It is free and reserved now
+ PhysRegsEverUsed[Reg] = true;
+
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) {
+ PhysRegsUseOrder.push_back(*AliasSet);
+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
+ PhysRegsEverUsed[*AliasSet] = true;
+ }
}
}
// Okay, we have allocated all of the source operands and spilled any values
// that would be destroyed by defs of this instruction. Loop over the
- // implicit defs and assign them to a register, spilling incoming values if
+ // explicit defs and assign them to a register, spilling incoming values if
// we need to scavenge a register.
//
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
- MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
- unsigned DestVirtReg = MI->getOperand(i).getReg();
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+ MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
// If DestVirtReg already has a value, use it.
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
DestPhysReg = getReg(MBB, MI, DestVirtReg);
+ PhysRegsEverUsed[DestPhysReg] = true;
markVirtRegModified(DestVirtReg);
- MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
+ MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
}
+ }
// If this instruction defines any registers that are immediately dead,
// kill them now.
//
for (LiveVariables::killed_iterator KI = LV->dead_begin(MI),
KE = LV->dead_end(MI); KI != KE; ++KI) {
- unsigned VirtReg = KI->second;
+ unsigned VirtReg = *KI;
unsigned PhysReg = VirtReg;
if (MRegisterInfo::isVirtualRegister(VirtReg)) {
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
removePhysReg(PhysReg);
}
}
+
+ // Finally, if this is a noop copy instruction, zap it.
+ unsigned SrcReg, DstReg;
+ if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) {
+ LV->removeVirtualRegistersKilled(MI);
+ LV->removeVirtualRegistersDead(MI);
+ MBB.erase(MI);
+ }
}
- // Rewind the iterator to point to the first flow control instruction...
- const TargetInstrInfo &TII = TM->getInstrInfo();
- MI = MBB.end();
- while (MI != MBB.begin() && TII.isTerminatorInstr((--MI)->getOpcode()));
- ++MI;
+ MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
// Spill all physical registers holding virtual registers now.
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
else
removePhysReg(i);
-#ifndef NDEBUG
+#if 0
+ // This checking code is very expensive.
bool AllOk = true;
- for (unsigned i = 0, e = Virt2PhysRegMap.size(); i != e; ++i)
+ for (unsigned i = MRegisterInfo::FirstVirtualRegister,
+ e = MF->getSSARegMap()->getLastVirtReg(); i <= e; ++i)
if (unsigned PR = Virt2PhysRegMap[i]) {
std::cerr << "Register still mapped: " << i << " -> " << PR << "\n";
AllOk = false;
RegInfo = TM->getRegisterInfo();
LV = &getAnalysis<LiveVariables>();
+ PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
+ std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
+ Fn.setUsedPhysRegs(PhysRegsEverUsed);
+
PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
// initialize the virtual->physical register map to have a 'null'
// mapping for all virtual registers
- Virt2PhysRegMap.assign(MF->getSSARegMap()->getNumVirtualRegs(), 0);
+ Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg());
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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